Bus Interface Architecture Patents (Class 710/305)
  • Patent number: 10318270
    Abstract: A method for upgrading firmware of an adapter, an apparatus, and a system are provided. The method includes receiving, by an adapter, an upgrade file in accordance with a Universal Asynchronous Receiver/Transmitter (UART) format, which is transferred by a converter, via a data line of a charging interface of the adapter, where the converter is configured to convert the upgrade file in accordance with a Universal Serial Bus (USB) in a personal computer (PC) into the upgrade file in accordance with the UART format for transmitting the upgrade file in accordance with the UART format to the adapter; and processing, by a microcontroller unit (MCU), the upgrade file in accordance with the UART format for upgrading the firmware of the adapter when the adapter is in an upgrading mode, where the MCU is built in the adapter.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 11, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP, LTD.
    Inventors: Chen Tian, Jialiang Zhang, Jun Zhang, Fuchun Liao
  • Patent number: 10311013
    Abstract: A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 4, 2019
    Assignee: Facebook, Inc.
    Inventors: Kevin Desmond Lee, Jia Ning, Narsing Vijayrao, Koh Yew Thoon
  • Patent number: 10311000
    Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Siang Lin Tan, Su Wei Lim, Ming Chew Lee, Ofer Nathan
  • Patent number: 10296061
    Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies (e.g., DC-to-DC converters), ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. In addition, the controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 21, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Srirama Chandra, Robert Bartel
  • Patent number: 10268616
    Abstract: Embodiments of systems and methods for selectively enabling and disabling protocols of a USB-C port are provided herein. According to one embodiment, a method for selectively enabling one or more protocols of a USB-C port on an information handling system (IHS) includes determining, upon system boot, if the IHS is connected via the USB-C port to a peripheral device that is authorized for use with the information handling system. If the peripheral device is not authorized for use with the IHS, the method may disable all protocols of the USB-C port. If the peripheral device is authorized for use with the IHS, the method may enable one or more protocols of the USB-C port.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 23, 2019
    Assignee: Dell Products L.P.
    Inventors: Adolfo S. Montero, James T. Gillon, Marcin M. Nowak
  • Patent number: 10254821
    Abstract: An apparatus is provided which comprises: an input/output (I/O) port; a first circuitry to update an in-band presence detect field, based on communication via an in-band channel; a second circuitry to update an out-of-band presence detect field, based on communication via an out-of-band channel; and a third circuitry to update a presence detect state change field, wherein the third circuitry is to selectively ignore the out-of-band presence detect field and utilize the in-band presence detect field, while the third circuitry is to update the presence detect state change field.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: K. L. Siva Prasad Gadey NV, Samit Mehrotra, Eric Wehage
  • Patent number: 10255224
    Abstract: An intelligent PCIe slot lane assignment method applied to a motherboard including a CPU capable of providing at least 16 lanes, a switch circuit, a PCIe slot assembly consisting of a first PCIe slot, a second PCIe slot and a third PCIe slot, and a logic controller. The intelligent control of the logic controller in detection of the insertion of a PCIe expansion card in the first PCIe slot, second PCIe slot and third PCIe slot of the PCIe slot assembly enables the switch circuit to automatically assign lanes to the first PCIe slot, second PCIe slot and third PCIe slot of the PCIe slot assembly according to the detection results, increasing the convenience of expansion application and having a higher performance and expansibility.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 9, 2019
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Hsien-Kuang Chiu, Peng-Yuan Chu, Yi-Kuo Chen, Chien-Chih Chen, Chien-Yi Hsu
  • Patent number: 10248602
    Abstract: Computing devices having slots and components for receipt of different types of peripherals are disclosed. According to an aspect, a computing device includes a body that defines an interior and comprises a rear wall defining a slot that extends into the interior. The slot is sized and shaped for receipt of two or more different types of peripherals. The computing device includes a motherboard that defines another slot being sized and shaped for receipt of the different types of peripherals. The other slot is substantially coplanar with the second slot. The computing device includes a connector operably interfaced with the motherboard and configured to interface with the different types of peripherals.
    Type: Grant
    Filed: September 19, 2015
    Date of Patent: April 2, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Paul Artman, Andrew T. Junkins, Jiabing Li, Rodrigo Samper, Marcelo Vinante
  • Patent number: 10251068
    Abstract: Spectrum access allocation processes and systems are described in which multiple tiers of predetermined transmission powers are enforced, and where access is established by transmission at or below the lowest predetermined transmission power. The allocation processes include provisioning a wireless interface between a spectrum access system and a user equipment that is not registered with the spectrum access system. The wireless interface permits data transfer at or below a first predetermined power setting. A request to register the user equipment with the spectrum access system is transmitted to a spectrum access server. The spectrum access server receives a message from the spectrum access server indicating that the user equipment has been registered with the spectrum access system. The user equipment is controlled to transmit data at a second predetermined power setting that is greater than the first predetermined power setting.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 2, 2019
    Assignee: Google LLC
    Inventors: Jibing Wang, Mitchell Trott, Yi Hsuan
  • Patent number: 10241563
    Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 26, 2019
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 10241953
    Abstract: A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt, James Lionel Panian
  • Patent number: 10235183
    Abstract: Example implementations relate to booting a system comprising a system-on-a-chip (SOC) device. For example, boot code and system code comprising at least one selected from among an operating system and hypervisor code are stored in an on-chip non-volatile memory of a SoC device. By executing the boot code from the on-chip non-volatile memory, the system is booted from a mode in which power is removed from the system, where the booting includes loading the system code in the SoC device from the on-chip non-volatile memory without accessing storage off the SoC device.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 19, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Carlos Haas Costa, Taciano Dreckmann Perez, Thiago Silva
  • Patent number: 10228745
    Abstract: As part of starting a system including a system-on-a-chip (SoC) device from a mode in which power is removed from the system, the SoC device determines, based on the metadata, whether to resume the system to a prior system state. In response to the metadata indicating that the system is to be resumed to the prior system state, the system is resumed to the prior system state using system state information stored in the on-chip non-volatile memory.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 12, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Carlos Haas Costa, Taciano Dreckmann Perez, Christian Samuel Perone, Thiago Silva, Craig A Walrath
  • Patent number: 10216678
    Abstract: In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Diana Raluca Murtaza, Ansgar Pottbaecker
  • Patent number: 10217499
    Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Graham Kirsch, Martin Steadman
  • Patent number: 10210121
    Abstract: A system for switching between a high performance mode and dual path mode is disclosed. The system includes a first device, a second device, a third device, and a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of the first device or one or more second lanes of the second device to third lanes of the third device to yield enabled lanes. The system also include a number of the enabled lanes is less than or equal to a number of the third lanes, and the switch is configured to route the enabled lanes associated with the first device to a first portion of the third lanes in an increasing order and to route the enabled lanes associated with the second device to a second portion of the third lanes in a decreasing order.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 19, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Wei-Yi Chu, Chia-Feng Cheng, Kai Chang, Chih-Yu Chen
  • Patent number: 10203961
    Abstract: A BIOS control method for PCI-E lanes includes the following steps. A BIOS obtains information of whether a first expansion card and a second expansion card are respectively inserted in a first PCI-E slot and a second PCI-E slot, and if the second expansion card is inserted in the second PCI-E slot, then the BIOS instructs a CPU to reverse the order of PCI-E lanes electrically connected between the CPU and the second PCI-E slot.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: February 12, 2019
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Pei-Hua Sun, Yen-Yun Chang, Weiyuan Cheng
  • Patent number: 10203897
    Abstract: Techniques for performing compression operations on persistently-stored data blocks during read/write commands. A method embodiment performs in-line data compression operations over data blocks referenced by a caller. The in-line data compression operations are performed during execution of a storage input-output (I/O) command, between the event of receipt of the storage I/O command and the event of returning status of the storage I/O command. The storage I/O operation is associated with at least one data group comprising one or more data blocks that are identified by the caller. Upon receipt of the storage I/O command, one or more compression rules are applied to the data blocks to determine one or more compression parameters, which compression parameters are used to form specific compression operations that are performed over at least a portion of the data group. The status pertaining to the execution of the storage I/O operation is returned to the caller.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 12, 2019
    Assignee: Nutanix, Inc.
    Inventors: ChernYih Cheah, Kiran Tatiparthi, Manosiz Bhattacharyya, Varun Kumar Arora
  • Patent number: 10198947
    Abstract: The disclosure describes a device for configuring an infrared (IR) emitter. The device includes a support structure and a microprocessor attached to the support structure. An interface circuit is also attached to the support structure and is configured to provide communications between the microprocessor and a portable computing device. A memory, which is attached to the support structure, is coupled to the microprocessor and is configured with instructions. Execution of the instructions by the microprocessor cause the microprocessor to communicate with an application executing on the portable computing device and initiate transmission of configuration data received from the application to the IR emitter. A transmitter is attached to the support structure and is coupled to the microprocessor. The transmitter is configured to transmit the configuration data to the IR emitter.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Global Traffic Technologies, LLC
    Inventors: Charles B. Meyer, Kevin Eichhorst, Timothy J. Hall
  • Patent number: 10198379
    Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson
  • Patent number: 10198849
    Abstract: Systems, apparatuses, and methods for preloading caches using a direct memory access (DMA) engine with a fast discard mode are disclosed. In one embodiment, a processor includes one or more compute units, a DMA engine, and one or more caches. When a shader program is detected in a sequence of instructions, the DMA engine is programmed to utilize a fast discard mode to prefetch the shader program from memory. By prefetching the shader program from memory, the one or more caches are populated with address translations and the shader program. Then, the DMA engine discards the shader program rather than writing the shader program to another location. Accordingly, when the shader program is invoked on the compute unit(s), the shader program and its translations are already preloaded in the cache(s).
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Rex Eldon McCrary, Harry J. Wise
  • Patent number: 10185618
    Abstract: Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface configuration having a first bus width to send data over the bus in response to an interface parameter indicating a first interface parameter. Selection is made of a second bus interface configuration having a second bus width to send data over the bus in response to the interface parameter indicating a second interface parameter, wherein the first bus width has fewer bits than the second bus width.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 22, 2019
    Assignee: INTEL CORPORATION
    Inventor: Bill Nale
  • Patent number: 10186010
    Abstract: Embodiments of the present invention disclose an electronic device and a graphics processing unit card, which can improve data input and output capabilities. The electronic device includes a graphics processing unit card and a mainboard. The graphics processing unit card includes a main chip and M first PCIe interfaces electrically connected to the main chip, where M is an integer greater than or equal to 2. The mainboard includes a processing unit and M second PCIe interfaces connected to the processing unit, and the M second PCIe interfaces are respectively connected to the M first PCIe interfaces.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 22, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wenliang Liang, Liang Zhuang
  • Patent number: 10182100
    Abstract: A communication device is provided. The communication device includes an IC chip configured to read out information stored in an external device; and a communication unit configured to download an agent via a network, wherein the agent includes an application software configured to operate the IC chip as a reader, and wherein a role is provided as data associated with the application software in which at least part of a processing of the reader is performed by the agent, and wherein the communication device is configured to read out the information from the external device and to perform a predetermined processing based on the information.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 15, 2019
    Assignee: Felica Networks, Inc.
    Inventor: Naoto Tobita
  • Patent number: 10180917
    Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 15, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Jochen Sauer, Robert Leinfellner, Matthias Klemm, Thorsten Brehm, Robert Polnau, Matthias Schmitz
  • Patent number: 10169273
    Abstract: Systems, methods, and apparatus are described that enable a physical layer interface of a device coupled to a serial bus to combine two or more single-byte write transactions to obtain a multi-byte write transaction. A method includes buffering a first single-byte transaction addressed to a first register at a first address of a slave device in a first-in-first-out buffer of the physical layer, receiving at the physical layer a second single-byte transaction addressed to a second register at a second address of the slave device coupled to the serial bus, determining in the physical layer whether the second address is incrementally greater than the first address, combining the second single-byte transaction with the first single-byte transaction to obtain a multi-byte transaction, replacing the first single-byte transaction with the multi-byte transaction in the first-in-first-out buffer, and transmitting a sequence of transactions output by the first-in-first-out buffer over the serial bus.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: January 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Inyoung Woo, Young Hoon Kang
  • Patent number: 10165611
    Abstract: A Bluetooth pairing system includes an external device and a host device. The external device includes a Bluetooth module, a first transmission interface and a USB controller. When the external device is connected with the host device, a standard handshaking message complying with a USB communication protocol is issued from the processor to the external device. After the standard handshaking message is received by the USB controller of the external device, a device descriptor of the external device is transmitted from the USB controller to the host device. The device descriptor contains a vendor identification code, a product identification code, a product string and a product type of the external device and a target communication address of the Bluetooth module. The host device analyzes the device descriptor to acquire the target communication address of the Bluetooth module.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: December 25, 2018
    Assignee: Primax Electronics Ltd.
    Inventors: Chih-Feng Chien, Chen-Ming Chang, Chia-Shyang Hsu, Wen-Shih Lee
  • Patent number: 10152445
    Abstract: A semiconductor die assembled in a wafer-level package includes a processing circuit, a multiplexer, and a transmit interface. The processing circuit generates a plurality of signal outputs. The multiplexer multiplexes the signal outputs into a multiplexed signal. The transmit interface transmits the multiplexed signal to another semiconductor die assembled in the wafer-level package.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: December 11, 2018
    Assignee: MEDIATEK INC.
    Inventor: Yao-Chun Su
  • Patent number: 10152030
    Abstract: A safety relay configuration system for configuring safety functions to be carried out by a safety relay is provided. The configuration system comprises a number of features that facilitate intuitive and simplified configuration of an industrial safety relay, including but not limited to features that guide the user through the configuration process using an intuitive sequential procedure that provides feedback and prompts based on user interaction, enforce design consistency throughout the configuration project by intelligently limiting user selections, and visually organize configuration and status information in a manner that efficiently utilizes display space and allows the user to quickly evaluate available configuration options.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: December 11, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Bradley A. Prosak, Thomas Helpenstein, Rudolf Papenbreer, Dirk Lorenz, Oliver Heckel, Carol Knez, Christopher Burke, Todd Bubar, Nhat Nam Trinh
  • Patent number: 10152527
    Abstract: In one aspect, a method includes selecting a C-module; sending a write from a host to the selected C-module; selecting a D-module to commit a page related to the write; selecting a R-module to transmit data from the write to the target; writing the data from the write to target location; and writing the data to an address-to-hash table after acknowledgement that the data has been written to the target location and after the D-module acknowledges that the page is committed.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 11, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: David Meiri, Irit Lempel
  • Patent number: 10146726
    Abstract: A motherboard an electronic device using the same are provided. The motherboard includes a motherboard and a control chip. The processor is adapted to be inserted to a processor base including a plurality of pins. The pins is divided to defined pins and undefined pins. The processor base includes a plurality of electrical contacts. A first part of the electrical contacts are corresponding to the defined pins, and a second part of the electrical contacts are corresponding to the undefined pins. The control chip determines whether to make the motherboard enter an overclocking operation mode according to a control command. When the motherboard is set to be at the overclocking operation mode, the control chip transmits a control signal to the undefined pins of the processor via the second part of the electrical contacts, and then the processor improves operating efficiency.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 4, 2018
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Ji-Kuang Tan, Yu-Chen Lee, Bing-Min Lin, Ming-Hung Chung
  • Patent number: 10148618
    Abstract: One or more techniques and/or systems are provided for network isolation. For example, nodes within a mesh of devices may be configured with routing rules, main routing tables, and alternative routing tables, such as at a layer-3 network layer. The routing rules may specify that packets received from downstream are to be routed upstream to either a gateway or a backhaul device for evaluation as to whether such packets are allowed to be communicated back downstream to destination recipients using main routing tables. An isolation rule may be configured to specify whether to block or allow packets. In an example, the gateway may either block or allow packets based upon whether a source and destination are within a same virtual local area network or are within different virtual local area networks. In this way, selective device isolation may be provided, such as at the layer-3 network layer.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 4, 2018
    Assignee: ABB Schweiz AG
    Inventors: Danurahardjo Tjahjono, Prabhat Regmi
  • Patent number: 10146554
    Abstract: Systems and methods for specifying extended descriptor information in a device accessed using a communication interface are disclosed. One method includes transmitting a request to a device from a host computing system, and receiving an extended capability descriptor identifying to the host computing system at least one extended descriptor set stored on the device. The extended capability descriptor identifies a minimum operating system version able to support a corresponding extended descriptor set.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: December 4, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Martin Richard Borve, Andrea A. Keating, Philip Albert Froese, Randall Aull, Firdosh K. Bhesania, Eliyas Yakub, Robert Harris, Jr., Vivek Gupta
  • Patent number: 10146709
    Abstract: A method for operating a memory system including a memory controller and a memory module, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventor: Chan-Jong Woo
  • Patent number: 10146439
    Abstract: A method for accessing data stored in a target of a data storage system includes: running a plurality of transport threads on a first group of CPUs, wherein each of the plurality of transport threads comprises a command receiver path and a command transmitter path; running a plurality of data path threads on a second group of CPUs, wherein each of the plurality of data path threads comprises a command issue path and a command completion path; posting an I/O command to an I/O command issue queue using the command receive path of a transport thread, and processing the I/O command using the command issue path of a data path thread; and posting an I/O completion notification to an I/O completion queue using the command completion path of the data path thread, and processing the I/O completion notification using the command transmitter path of the transport thread.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkata Bhanu Prakash Gollapudi, Vijaya Jakkula
  • Patent number: 10127176
    Abstract: In accordance with an embodiment, a receiver includes a receiving unit configured to receive a first received bus signal and a second received bus signal based on a bus input signal. The receiver also includes a first state machine configured to determine that a first output signal is a first symbol in response to the first received bus signal transitioning from a first bus state to a second bus state and staying in the second bus state for less than a first predetermined period of time, and a second symbol in response to the first received bus signal transitioning from the first bus state to the second bus state and staying in the second bus state for at least the first predetermined period of time. Additionally, the receiver includes a second state machine.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 13, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Paul Wallner, Dieter Metzner, Martin Streibl
  • Patent number: 10114436
    Abstract: A computing device including an AUX (auxiliary) power controller connected to the expansion slot to supply aux power to the expansion slot intermittently based on instructions from a baseboard management controllers (BMC).
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 30, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: Justin E York
  • Patent number: 10102088
    Abstract: A cluster system includes server apparatuses (10,20) connected by communication paths. Each server apparatus includes: a signal transmission unit (11) that transmits a signal indicating a self-presence to the other server apparatus via the communication paths (30-50); a reliability determination unit (12) that determines whether the communication paths (30-50) are reliable; and a processing management unit (13) that, in a state where the signal is not receivable from the other server apparatus, checks whether the communication paths to the other server apparatus have been determined to be reliable, and stops processing that is being executed when the result of the check shows that the communication paths have not been determined to be reliable.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 16, 2018
    Assignee: NEC Solution Innovators, Ltd.
    Inventor: Katsushi Shimodoi
  • Patent number: 10101764
    Abstract: A method for automatic clock configurations is performed by a system having a host and a peripheral device. The host indicates on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports a first clock configuration. The peripheral device receives from the first GPIO whether the host supports the first clock configuration. The peripheral device selects, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device. The peripheral device selects, in response to the host not supporting the first clock configuration, use of a common clock of the host.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 16, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Le-Sheng Chou, Sz-Chin Shih
  • Patent number: 10102089
    Abstract: A method for building a configuration signature for an input/output (I/O) device is described herein. The configuration signature is built based on descriptors of an I/O device and save to a host after an initial connection. After the initial connection, the I/O device may be subjected to modifications. To determine if such modifications exist, the descriptors of the I/O device are compared to the configuration signature after the initial connection.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventor: Steven McGowan
  • Patent number: 10097508
    Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey D. Haggar, Bruce Ratcliff, Benjamin T. Rau, Jerry W. Stevens
  • Patent number: 10091083
    Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey D. Haggar, Bruce Ratcliff, Benjamin T. Rau, Jerry W. Stevens
  • Patent number: 10083053
    Abstract: A system for virtual machine live migration includes a management node, a source server, a destination server, a peripheral component interconnect express (PCIe) switch, and an single root input/output virtualization (SR-IOV) network adapter, where the source server includes a virtual machine (VM) before live migration; the destination server includes a VM after live migration; the management node is adapted to configure, using the PCIe switch, a connection relationship between a virtual function (VF) module used by the VM before live migration and the source server as a connection relationship between the VF module and the destination server; and the destination server, using the PCIe switch and according to the connection relationship with the VF module configured by the management node, uses the VF module to complete virtual machine live migration. By switching the connection relationships, the system ensures that a data packet receiving and sending service is not uninterrupted.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 25, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Yijian Dong
  • Patent number: 10083147
    Abstract: Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10073807
    Abstract: A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Chaitanya Sreerama, Stephen H. Hall
  • Patent number: 10057365
    Abstract: Technologies are disclosed herein for asynchronous provision of resource status data. A resource status application can submit a request to a resource status service for status data regarding one or more computing resources provided by network services in a service provider network. In response thereto, the resource status service can submit synchronous requests to the network services for the status data. The resource status service can also provide a reply to the resource status application that includes an identifier (ID) that can be utilized to retrieve all or a portion of the status data at a future time. The reply might also specify a period of time that the resource status application is to wait before submitting another request for the status data to the resource status service. Subsequently, the resource status application can submit additional requests for the status data to the resource status service that include the identifier.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 21, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: David Whitney, Donley Ray P'Simer, Asa Denton
  • Patent number: 10042415
    Abstract: The discussion makes reference to methods and apparatuses for network controlled computer power down. The link layer in computer networking can be used to save power in computers.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: August 7, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Stephen Wilson Bailey, Karen Marie Schramm
  • Patent number: 10042571
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining a region of the memory for which to store information, inserting the information into the region of the memory, and applying one or more characteristics to the region of the memory via an instruction set architecture (ISA) operation, the one or more characteristics comprising an immutable characteristic to prevent modification of the information in the region of the memory.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 7, 2018
    Assignee: INTEL CORPORATION
    Inventors: Kirk D. Brannock, Barry E. Huntley
  • Patent number: 10033581
    Abstract: A method for retrieval of device-type managers is provided. A historical information of user's historical selection to device-type-managers (DTMs) is identified. The historical information represents a selected DTM and a VMR information of the selected DTM. The VMR information is related to vendor, model and revision of a field device. The VMR information of the selected DTM is associated with the selected DTM. The VMR information is retrieved. The DTMs to be recommended are evaluated, based on the historical information and the VMR information associated with the DTM. A result of evaluation on the DTMs to be recommended is generated. Based on the result of evaluation, a recommend list including one or more recommended DTMs to be launched by at least one of the plurality of client devices is generated.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 24, 2018
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Robert Figueroa, Anthony Benson Wong
  • Patent number: RE47083
    Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 9, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Eric C. Gaalaas, Mark Stewart Cantrell