Bus Interface Architecture Patents (Class 710/305)
  • Patent number: 11150842
    Abstract: A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sesibhushana Rao Bommana, Mukesh Panda
  • Patent number: 11137995
    Abstract: Embodiments of the invention provide a computer-implemented method for updating firmware of a Universal Serial Bus (USB) device. The USB device is configured to execute one or more applications of the USB device in a normal mode of operation of the USB device. The USB device includes a device descriptor indicative of one or more configuration descriptors, wherein a configuration descriptor is indicative of endpoints for data and command exchange. The device descriptor can be modified by adding a predefined bootloader configuration descriptor to the configurations descriptors for updating the firmware.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Andreas Christian Doering
  • Patent number: 11106611
    Abstract: Systems, methods, and devices are provided for migrating field device data signals from a first control system to a second control system using an interface card. An interface card can be configured to couple to a first and second terminal block cable assembly, respectively associated with a first and second control system. The interface card and system herein can maintain a field device data channel assignment configuration when migrating control and data I/O of the field device from the first control system to the second control system.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Baker Hughes Oilfield Operations LLC
    Inventor: Chad Michael Shryock
  • Patent number: 11100035
    Abstract: A hot-pluggable barrel jack connection system includes a male barrel jack connector including a tip connector at a distal end of the male barrel jack connector and configured to conduct a ground reference voltage, a first ring connector electrically isolated from the tip connector by a first insulator, and configured to conduct a first data signal, and a sleeve connector adjacent to a base of the male barrel jack connector electrically isolated from the first ring connector, and configured to conduct a power signal.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 24, 2021
    Assignee: ERP POWER, LLC
    Inventor: James H. Mohan
  • Patent number: 11073881
    Abstract: To make is possible to use a peripheral device that consumes a current exceeding the rated current allocated to each port in a simpler system configuration in an electronic apparatus having a plurality of external interfaces.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: July 27, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Motoki Koshigaya
  • Patent number: 11068435
    Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Suzanne Mary Vining, Yonghui Tang, Douglas Edward Wente, Huanzhang Huang
  • Patent number: 11064630
    Abstract: A system for supplying power to at least one power distribution and data hub using a portable battery pack including a battery enclosed by a wearable and replaceable pouch or skin is disclosed, wherein the pouch or skin can be provided in different colors and/or patterns. Further, the pouch or skin can be MOLLE-compatible. The battery comprises a battery element housed between a battery cover and a back plate, wherein the battery element, battery cover, and back plate have a slight curvature or contour. Further, the battery comprises flexible leads.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: July 13, 2021
    Assignee: LAT Enterprises, Inc.
    Inventors: Laura Thiel, Giancarlo Urzi, Carlos Cid
  • Patent number: 11041889
    Abstract: Disclosed are a method for estimating a load current of a power supply, and a USB-type converter. The method includes steps described below. After an input port of a USB connection line is connected to the power supply and an output port of the USB connection line is connected to a load, the power supply supplies power to the load through the USB connection line to obtain an initial load current value; an actual voltage value of the input port is detected, when the actual voltage value of the input port is less than a preset voltage value, the initial load current value is adjusted until the actual voltage value of the input port corresponding to an adjusted load current value is not less than the preset voltage value, and the adjusted load current value is output as a load current value of the power supply.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 22, 2021
    Assignee: SHENZHEN LEGENDARY TECHNOLOGY CO., LTD
    Inventor: Xiaoling Liu
  • Patent number: 11036853
    Abstract: A system for preventing cyber security attacks over the CAN bus of a vehicle, from carrying out their plot. The system includes a teleprocessing device that is provided with the message identifier of at least one ECU to be blocked. The teleprocessing device is configured to read the message identifier of CAN messages, to thereby identify the at least one ECU to be blocked. Upon determining that the vehicle is under a cyber security attack, the ECU blocking device is activated. Upon identifying that a message was transmitted by the at least one ECU to be blocked, then during the CAN bus ‘bit monitoring’ process, before the at least one ECU to be blocked reads back the transmitted signal, the ECU blocking device alters one or more bits of the transmitted signal, to thereby force the message to be an erroneous CAN message.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 15, 2021
    Assignee: ENIGMATOS LTD.
    Inventors: Eyal Kamir, Alexander Fok, Yaniv Tuchman, Avi Bitton, Uriel Friedman, Meni Dali, Yoni Malka
  • Patent number: 11039301
    Abstract: Apparatuses, methods, and systems are provided for configuring a “SIM-less” System-on-Chip (S2oC) with integrated reprogrammable cellular network connectivity. Digitally issued Subscriber Identity Module (SIM) cards may be digitally issued by a remote server and downloaded and managed by the S2oC. A virtual SIM card container may be packaged in the S2oC and hosts an identity manager used by a plurality of applications residing in the multi-core processor of the S2oC. A virtual modem with a custom communication protocol allows the multi-core processor applications to exchange data with the virtual SIM card container.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Simless, Inc.
    Inventor: Ismaila Wane
  • Patent number: 11012256
    Abstract: A connecting unit to transmit process data of an automation process of an automation system to an external data infrastructure, configured as a field device for arrangement on a field level of the automation system. The connecting unit comprises a field bus module, network module and interface module. The field bus module is configured to interchange the process data via the field bus with a signal unit connected to the automation process via a field connection. The network module is configured to interchange the process data with the external data infrastructure, use the data network to transmit input process data to the external data infrastructure, and retrieve output process data from the external data infrastructure. The interface module is configured to interchange the process data between the field bus module and the network module. The interface module prompts interchange of the process data autonomously.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 18, 2021
    Assignee: Beckhoff Automation GmbH
    Inventors: Pascal Dresselhaus, Sven Goldstein, Hans Beckhoff, Ralf Vienken
  • Patent number: 11011693
    Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Thomas Francis Watson, Stephanie A. Bojarski, James S. Clarke
  • Patent number: 11011876
    Abstract: Remote management of network interface peripheral cards uses physical pin reassignment and a dedicated management network. One or more physical pins in a connector may be dynamically redefined from an interface protocol to a different interface protocol. The dynamic redefinition allows existing input/output signals to be routed to the pins to provide remote management features.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: May 18, 2021
    Assignee: Dell Products L.P.
    Inventors: Andrew Butcher, Timothy M. Lambert, Lee Eric Ballard
  • Patent number: 11003612
    Abstract: A processing subsystem/endpoint subsystem connection configuration system includes a plurality of processing subsystems and a multi-endpoint adapter device that provides a plurality of endpoint subsystems. A bus exchange switch device couples the plurality of processing subsystems to the plurality of endpoint subsystems, and a connection configuration engine is coupled to the multi-endpoint adapter device and the bus exchange switch device. The connection configuration engine receives a connection resource request that requests connection resources for a first processing subsystem that is included in the plurality of processing subsystems. Based on the connection resource request, the connection configuration engine causes at least one of the plurality of endpoint subsystems to perform a first connection resource change operation. The connection configuration engine then configures the bus exchange switch device to provide the connection resources for the first processing subsystem.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Yogesh Varma, Shyamkumar T. Iyer, William Price Dawkins, Mukund P. Khatri
  • Patent number: 11003539
    Abstract: Offload processing may be provided that is not dedicated to a primary processor or a subset of primary processors. A system may have one or more offload processing devices, including one or more APUs, coupled to data storage slots of the system, which can be shared by multiple primary processors of the system. Each offload processing device may be configured to be coupled to a storage slot, for example, as if the device were a storage drive, and include an interface in conformance with a version of an NVMe specification and may have a form factor in accordance with the U.2 specification. The APU within each offload processing device may be communicatively coupled to one or more primary processors by switching fabric disposed between the one or more primary processors and the storage slot to which the offload processing device is connected.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 11, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jon I. Krasner, Jonathan P. Sprague, Jason J. Duquette
  • Patent number: 10960760
    Abstract: Provided are a vehicle control device capable of displaying a high quality seamless image without data transmission delay and a difference in image quality between a plurality of displays, and a method thereof. The vehicle control device includes a plurality of different displays installed in a vehicle and a controller generating a first image having a plurality of pieces of first information, generating a second image having a plurality of pieces of second information, merging the first and second images, dividing the merged image into a plurality of images, and displaying the plurality of divided images on a plurality of displays, respectively.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 30, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Honggul Jun, Sujin Kim, Kihyung Lee
  • Patent number: 10963406
    Abstract: Embodiments may relate to a universal serial bus (USB)-enabled apparatus that includes one or more USB devices that are coupled with a USB host controller by a persistent connection. The USB host controller may identify that the USB device is persistently coupled and then identify USB device information related to the USB device, wherein the USB device information is stored prior to the identification of the USB device. The USB host controller may then use that identified information to perform USB enumeration. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abdul Rahman Ismail, Rajaram Regupathy, Balaji Manoharan
  • Patent number: 10956025
    Abstract: Provided are a gesture control method, a gesture control device and a gesture control system. The gesture control method includes: establishing, by a mobile terminal, a wireless communication connection with a display device; displaying, by the mobile terminal, a gesture input interface corresponding to a current application of the display device; detecting, by the mobile terminal, a user gesture; converting, by the mobile terminal, the user gesture into an operation instruction corresponding to the user gesture; and transmitting, by the mobile terminal, the operation instruction to the display device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: March 23, 2021
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Zhenhua Zhu
  • Patent number: 10953485
    Abstract: A welding current source (1) having a housing (10) formed from metallic material, a welding inverter (50), a digital, electronic welding process computation unit (20) and a man-machine interface device (30), wherein the welding process computation unit (20) is set up to actuate the welding inverter (50), wherein the welding process computation unit (20) and the welding inverter (50) are arranged in the housing (10) and the man-machine interface device (30) is mounted on the welding current source (1) outside the housing (10), wherein the welding current source (1) additionally has a digital, electronic man-machine computation unit (40) mounted on the welding current source (1) outside the housing (10), and wherein the man-machine interface device (30) is connected to the man-machine computation unit (40), and wherein the man-machine computation unit (40) and the welding process computation unit (20) are networked to one another via a communication link (60) and form a computer network.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 23, 2021
    Assignee: Illinois Tool Works Inc.
    Inventor: Marcel Foh
  • Patent number: 10956351
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Parthasarathy, Ramamurthy Krithivas, Bradley Burres, Pawel Szymanski, Yi-Feng Liu
  • Patent number: 10956314
    Abstract: A method, a system and a computer program product for regression test selection in a multi-threaded distributed target program execution tested by multi-threaded test suites. The method includes monitoring changes to source code of the target program in real-time to determine changed code-modules and extracting the regression test cases which simulate the changed code-modules. A calibration engine according to an embodiment isolates test case execution flow at individual test case level and builds relationship between the test case of the multi-threaded test suite and the distributed target program code-modules simulated by the test case. The method enhances the run-time behavior of the target program execution engines and builds relationships between the threads executing in the engine through throttling mechanism without affecting the actual functional execution. It enables calibration to happen in a multi-threaded test environment.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 23, 2021
    Assignee: INFOSYS LIMITED
    Inventors: Kiran Voderhobli Holla, Pradeep S, Uday Kumar Gupta, Kasthuri Ram V., Nimisha Sharma
  • Patent number: 10949091
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
  • Patent number: 10951016
    Abstract: An example system includes an electrical enclosure. The electrical enclosure includes an identification data module, an electrical sensor, an enclosure environment sensor, and a pilot light module. The pilot light module includes (i) a pilot light and (ii) a communication module. The communication module is coupled to the identification data module, the electrical sensor, and the enclosure environment sensor. The communication module is configured to determine a visual communication signal based on information received from one or more of the identification data module, the electrical sensor, and the enclosure environment sensor, and drive the visual communication signal via the pilot light. The visual communication signal indicates one or more operational parameters within the electrical enclosure. The system further includes a client device configured to receive the visual communication from the pilot light.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 16, 2021
    Assignee: Appleton Grp LLC
    Inventor: Yicheng Peter Pan
  • Patent number: 10922071
    Abstract: A centralized flash memory module is provided. The centralized flash memory module includes flash memory components, a flash memory management controller (FMMC), and a complex programmable logic device (CPLD). Each of the flash memory components is connected to a server device separate from the centralized flash memory module. The FMMC is configured to connect to the flash memory components and to a rack management device, separate from the centralized flash memory module. The CPLD is configured to connect the FMMC to the flash memory components and connect the server device to the flash memory components.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: February 16, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ming-Hung Hung, Hsin-Hung Kuo, Chin-Fu Ou
  • Patent number: 10909060
    Abstract: A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 2, 2021
    Assignee: ATI Technologies ULC
    Inventor: James Hunkins
  • Patent number: 10909818
    Abstract: A method and a system for controlling a status indication light of a Peripheral Component Interconnect Express (PCIE) hard disk are disclosed. The method includes determining a current operation mode of the PCIE hard disk and transmitting information of the current operation mode to a southbridge chip by a CPU. The information is transmitted to a complex programmable logic device (CPLD) by the southbridge chip. The display of the status indication light corresponding to the current operation mode is controlled according to the information by the complex programmable logic device. The CPLD is controlled by the southbridge chip, to control display control of the status indication light corresponding to reset and locate operation of the PCIE hard disk. The usage status of the PCIE hard disk may be determined in real time by performing Hamming check to the information, and the accurate display of status indication light may be ensured.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 2, 2021
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Wei-Guo Zhao
  • Patent number: 10910845
    Abstract: The present disclosure provides a charging system, a terminal, a power adapter and a charging line. The terminal includes a first controller and M charging input interfaces. The power adapter includes a second controller and N charging output interfaces. When at least one of the N charging output interface is coupled to the charging input interfaces of the terminal, the second controller and the first controller communicate with each other to determine the number of charging output interfaces of the power adapter coupled to the terminal, and a charging current outputted from the power adapter to the terminal is adjusted according to the number of charging output interfaces of the power adapter coupled to the terminal.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 2, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Xinfeng Chen, Chen Tian, Jialiang Zhang
  • Patent number: 10901934
    Abstract: A USB integrated circuit (IC) includes a first USB port and a second USB port. The first USB port includes a first connecting component pair and a second connecting component pair. The second USB port includes a third connecting component pair and a fourth connecting component pair. The USB IC outputs a first differential signal pair and a third differential signal pair to the outside via the first connecting component pair and the third connecting component pair, and receives a second differential signal pair and a fourth differential signal pair from the outside via the second connecting component pair and the fourth connecting component pair. The first connecting component pair is disposed between the second connecting component pair and the third connecting component pair, and the third connecting component pair is disposed between the first connecting component pair and the fourth connecting component pair.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: January 26, 2021
    Assignee: VIA LABS, INC.
    Inventors: Chia-Ming Tu, Hsiao-Chyi Lin
  • Patent number: 10884971
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: David Harriman, Jasmin Ajanovic
  • Patent number: 10878864
    Abstract: There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 29, 2020
    Assignee: SURECORE LIMITED
    Inventor: Stefan Cosemans
  • Patent number: 10861122
    Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 8, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Mantor, Jeffrey T. Brady, Angel E. Socarras
  • Patent number: 10838762
    Abstract: A method for live migration of a virtual machine in a MR-IOV environment is provided. The method is used in a system, wherein the system includes a plurality of computing hosts, an MR-IOV device, and a management host including a physical function and configured to implement a plurality of virtual functions. Eand each computing host and the management host are coupled to the MR-IOV device. The method includes: migrating, by a source computing host of the computing hosts, a source virtual machine in the source computing host to a destination VM in a destination computing host of the computing hosts, wherein the source VM includes a source VF; transmitting, by the destination computing host, a request message to a management host and reassigning, by the management host, a first VF corresponding to the source VF in the management host to the destination VM according to the request message.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 17, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Tang Lee, Tai-Hua Hsiao, Cheng-Chun Tu, Peng-Kai Hsu
  • Patent number: 10838655
    Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Kobayashi, Jun Deguchi, Junji Wadatsumi, Takashi Toi
  • Patent number: 10831571
    Abstract: Communication between one system and another system using one communication mechanism has failed. The one communication mechanism includes an operating system service to transfer a message between the one system and the other system. Based on determining that the communication between the one system and the other system has failed, automatically switching from the one communication mechanism to another communication mechanism to communicate the message between the one system and the other system. The other communication mechanism is different from the operating system service and uses a coupling facility list structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard Schneider, Khiet Q. Nguyen
  • Patent number: 10824581
    Abstract: Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a PCIe switch coupled to a host processing system and PCIe slots may receive enumeration requests from the host processing system to identify available PCIe devices. In response to the enumeration requests, the PCIe switch may transfer responses to the host processing system indicating device identifier information for PCIe devices associated with the PCIe slots even if one or more of the PCIe devices is not currently installed.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 3, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Berck Nash, Randall Hess, Michael Walker, James Michael Reiser
  • Patent number: 10795612
    Abstract: Offload processing may be provided that is not dedicated to a primary processor or a subset of primary processors. A system may have one or more offload processors, for example, GPUs, coupled to data storage slots of the system, which can be shared by multiple primary processors of the system. The offload processor(s) may be housed within a device configured to be coupled to a storage slot, for example, as if the device were a storage drive. The one or more offload processors may be housed within a device that includes an interface in conformance with a version of an NVMe specification and may have a form factor in accordance with the U.2 specification. Offload processing devices may be communicatively coupled to one or more primary processors by switching fabric disposed between the one or more primary processors and the storage slot to which the offload processing device is connected.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 6, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Jon I Krasner, Jason J. Duquette, Jonathan P. Sprague
  • Patent number: 10789191
    Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Andium Inc.
    Inventors: Jory Schwach, Brian Bosak
  • Patent number: 10783942
    Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graham Kirsch, Martin Steadman
  • Patent number: 10776288
    Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple type
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 15, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Cheng-Yu Chen, Chih-Ching Chien
  • Patent number: 10754401
    Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 25, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Srirama Chandra, Robert Bartel
  • Patent number: 10733500
    Abstract: In one embodiment, a system includes one or more electronic neurons and one or more electronic axons. Each neuron is connected to at least one electronic axon via an electronic synapse, and at least one of the one or more electronic neurons is configured to store information in a membrane potential thereof and/or at least one of the one or more electronic axons is configured to store information in an axon delay buffer thereof to act as a memory. In another embodiment, a computer-implemented method includes storing information to a memory comprising electronic neurons and electronic axons. Information is stored in either a membrane potential of at least one of the electronic neurons or in an axon delay buffer of at least one of the electronic axons. Also, each neuron is connected to at least one electronic axon via an electronic synapse.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Andreopoulos, Andrew S. Cassidy
  • Patent number: 10734012
    Abstract: Data bus systems and methods include a device controller coupled to a first interface for digital audio data communications in accordance with a first communications protocol, the device controller including a master bus controller for controlling a multi-drop bus in accordance with a second communications protocol; and a first slave device coupled to the multi-drop bus and configured to transmit and receive digital audio data communications with the device controller in accordance with the second communications protocol. Each transmission line end is terminated using the device attached at one end of the transmission line and by another device attached at the other end and reflections due to mismatches in impedance by inclusion of intermediate signaling nodes are controlled to allow multi-drop device support and high speed signaling. The second communications protocol supports multiple audio data rates using a fixed frame format.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 4, 2020
    Assignee: SYNAPTICS INCORPORATED
    Inventor: Jens Kristian Poulsen
  • Patent number: 10721310
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a thin client. The thin client establishes a remote session with a remote machine. The thin client detects a connection of a device at a first connection port. The thin client determines a category of the device. The thin client establishes a redirection channel in the remote session with the remote machine based on the category. The thin client redirects access of the device to the remote machine.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 21, 2020
    Assignee: AMZETTA TECHNOLOGIES, LLC
    Inventors: Derek Huang, Tommy Hu, Yugender P. Subramanian, Indira Valmiki
  • Patent number: 10713203
    Abstract: This disclosure relates to methods and systems for dynamically partitioning of PCIe disk arrays based on software configuration/policy distribution. In one embodiment, at least one PCIe switch has an input port operatively connected to a respective CPU and at least one output port. A multiplexer is connected between the output port(s) of the at least one PCIe switch and a PCIe disk array, for example an NVMe SSD, and is configured to connect the PCIe disk array in a first configuration to a single PCIe switch in either one-x4 port or two x2 port mode, or in a second configuration to two PCIe switches in x2 port mode. The multiplexer can dynamically switch between the first configuration and the second configuration on the fly. Switching can occur, for example, in response to a hot-swap of an NVMe SSD or a policy change.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 14, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Yun Bai, Mengshi Li, Yang Sun, Min Wang, Yepeng Chen
  • Patent number: 10714878
    Abstract: A connector system having a plurality of high-speed connector modules, an anti-decoupling connector shell, and a multi axis backshell is provided. The high-speed module provides a low signal degradation electrically conductive signal path for terminated wires of twisted pairs of wires. The high-speed module additionally provides for dense placement of the terminated wires within the connector shell. The connector shell provides an anti-decoupling mechanism to prevent decoupling of the connector shell from a socket type connector shell resulting from typical forces applied to the connector shell. The multi-axis backshell provides mechanisms to toollessly adjust the angle of the various components making up the backshell which in turn provides a specifically angled path for cables contained within the backshell.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 14, 2020
    Assignee: PIC Wire & Cable, Inc.
    Inventors: Phong Dang, Phong Thao
  • Patent number: 10707988
    Abstract: Various solutions for transport block size (TBS) determination with respect to user equipment and network apparatus in mobile communications are described. An apparatus may determine an intermediate number of information bits. The apparatus may quantize the intermediate number of information bits. The apparatus may determine a TBS according to the quantized intermediate number of information bits. The apparatus may transmit the information bits according to the TBS.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 7, 2020
    Assignee: MediaTek Singapore Pte. Ltd
    Inventors: Abdellatif Salah, Abdelkader Medles
  • Patent number: 10704973
    Abstract: A method of timing data sampling includes, in a data acquisition device, generating sampling intervals from a system clock of the data acquisition device, sampling data at the generated sampling intervals, and receiving start of frame (SOF) signals from a port, such as a USB port. For a selected number of SOF signals received, an actual number of system clock cycles is determined for a time interval corresponding to the selected number of SOF signals. The actual number of system clock cycles is compared to a nominal number of system clock cycles and a sampling interval is adjusted based on the comparison. The actual number of system clock cycles may be determined using a count-and-capture counter. The nominal number of system clock cycles may be calculated based on a nominal system clock rate and on a known SOF interval. Generating sampling intervals may include using a divide-by-N counter.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 7, 2020
    Assignee: Advanced Mechanical Technology, Inc.
    Inventors: Albert C. Drueding, Gary M. Glass
  • Patent number: 10699013
    Abstract: A device for securing USB or Firewire port interconnections includes a microcontroller comprising a processor; a first connector/lead in communication with the microcontroller and configured to be coupled with a USB or Firewire external device; and a second connector/lead in communication with the microcontroller and configured to be coupled with a protected host. An optional user interface communicates with the microcontroller. When the microcontroller detects that the external device is coupled to the first connector/lead, the processor is configured to display a prompt on the user interface for a user to initiate inputs prior to the external device being allowed to connect with the protected host; or is configured to automatically prevent the external device from being connected with the protected host if the external device is on a blacklist of devices known to have device handlers in the protected host at a BIOS level, without modifying the protected host.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: June 30, 2020
    Assignee: Honeywell International Inc.
    Inventors: Matthew Warpinski, James Christopher Kirk, Brian Adams
  • Patent number: 10692410
    Abstract: A display panel driving apparatus includes an interface, a timing controller, a gate driver, and data driver. The interface includes a data determiner to determine whether or not input image data has a communication error and to process a packet of a data stream of the input image data, even though the input image data has the communication error. The timing controller receives the processed input image data from the interface and generates a data signal, a gate control signal, and a data control signal. The gate driver generates a gate signal based on the gate control signal. The data driver generates a data voltage based on the data control signal and the data signal.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 23, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Ho-Seok Han
  • Patent number: 10664403
    Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 26, 2020
    Assignee: ATI Technologies ULC
    Inventors: Leon King Nok Lai, Qian Ma, Jimshed B. Mirza