Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: A data transmission/reception device comprises a data bus; a data transmission circuit that recognizes standard data, receives a transmission data, loads a code data into the data bus, and generates a flag signal; and a data reception circuit that receives the flag signal and the code data transmitted through the data bus, and recovers the code data into a reception data according to the activation of the flag signal. According to the data transmission/reception device of the disclosure, current consumption may be reduced during data transmission.

Abstract: Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and prefetch one or more additional data items from memory. The first data and prefetched data are stored in a locally accessible buffer of the I/O controller. The I/O controller is then configured to convey each of the first data and one or more data items from the buffer to the I/O device at regular intervals of time during a given period of time, prior to initiating a fetch of additional data from the memory.

Abstract: An electronic device constituting a first block node included in a blockchain network of the disclosure is provided. The electronic device performs, in response to an input of requesting a transaction, obtaining first input data, output data, and a first identification value indicating a unique value capable of identifying a first smart contract, validating a blockchain application, forwarding a public key for a private key and an input data request to the second block node, based on the validation result, receiving, from the second block node, second input data encrypted with the public key and a second identification value indicating a unique value capable of identifying a second smart contract, and transmitting transaction data including the first input data and the output data to the server node, based on the comparison result of the first identification value and the second identification value.

Abstract: A data processing unit required for the data processing is started and a data processing unit not required for the data processing is stopped to change a part of the data processing settings or to add a new data processing setting without stopping the multi-stage data processing, and when the multi-stage data processing is executed, a rear-stage data processing unit reads the tag assigned in a front-stage data processing unit to discriminate the data processing unit that executes the data processing.

Abstract: A scheme to enhance USB-C port policy by dynamically entering optimal USB-C alternate mode with an informed feedback mechanism to OSPM which influences the USB-C port DPM. In some embodiments, when a USB4 device is connected to a port, the scheme parses the alternate modes and power characteristics from the class descriptor information of the enumerated device. In some embodiments, the parsed information is provided as a feedback to the OSPM that instructs the USB-C/PD DPM to enter or switch mode that shall meet the policy criteria of the OS configuration in a dynamic command control from the OS. In some embodiments, the USB-C DPM dynamically chooses to enter an optimal mode based on the power and thermal conditions information available in the embedded controller and indicate the OS about the changes. As such, the OS is aware of the USB operation mode.

Abstract: A studio control room including a first master control device, a master transmission route and a standby transmission route are provided. The first master control device is configured to transmit an audio/video broadcast control signal to a broadcast major structure through the master transmission route and the standby transmission route. The embodiment of the present disclosure further provides a broadcast major structure including a master broadcast control route and a standby broadcast control route. The master broadcast control route and the standby broadcast control route each are configured to receive the audio/video broadcast control signal sent by the studio control room and play the audio/video file according to the audio/video broadcast control signal. The embodiment of the present disclosure provides a broadcast control system including above studio control room and broadcast major structure. The studio control room is coupled to the broadcast major structure.

Abstract: A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

Abstract: A low-power radio-frequency (RF) receiver is characterized by a decreased current consumption over prior art RF receivers, such that the RF receiver may be used in control devices, such as battery-powered motorized window treatments and two-wire dimmer switches. The RF receiver uses an RF sub-sampling technique to check for the RF signals and then put the RF receiver to sleep for a sleep time that is longer than a packet length of a transmitted packet to thus conserve battery power and lengthen the lifetime of the batteries. The RF receiver compares detected RF energy to a detect threshold that may be increased to decrease the sensitivity of the RF receiver and increase the lifetime of the batteries. After detecting that an RF signal is being transmitted, the RF receiver is put to sleep for a snooze time period that is longer than the sleep time and just slightly shorter than the time between two consecutive transmitted packets to further conserve battery power.

Abstract: An ESPI-based method and device for enhancing server security, including: S100, a Complex Programmable Logic Device (CPLD) monitors packet formats and instructions on an Enhanced Serial Peripheral Interface (ESPI) bus; S200, when the CPLD monitors an abnormal firmware Flash read/write operation, the CPLD records operation-related records in a Flash which is mounted to the CPLD; S300, the CPLD lights a Light-Emitting Diode (LED) corresponding to a system error signal line or a LED corresponding to a Baseboard Management Controller (BMC) error signal line; S400, the CPLD determines whether to take over a CS0 signal or not; S500, when the CPLD determines to take over the CS0 signal, the CPLD requests to interact with a Platform Controller Hub (PCH) and warns of a system security issue.

Abstract: A data receiver, which communicates with a data transmitter through a plurality of lanes, includes: a first reception unit which receives first data through a first lane; a second reception unit which receives second data through a second lane; and a detector which compares the first data and the second data to detect a skew between the first lane and the second lane. The first reception unit includes a first clock data recovery unit which recovers a first clock and first payload data from the first data. The first reception unit controls a loop speed of the first clock data recovery unit based on a skew level of the skew.

Abstract: A system, device, and method for managing connections in an industrial installation are described. The system includes one or more field devices, one or more automation devices, and a self-configurable device. The self-configurable device is adapted to dynamically configure, based on type of the one or more field devices and the one or more automation devices, such that the self-configurable device manages a connection between the one or more field devices and the one or more automation devices. The self-configurable device is adapted to calibrate one or more field devices and manage automation functions in the industrial installation.

Abstract: A contact arrangement includes a plurality of contact groups. At least one of the contact groups includes a plurality of shared contacts, a plurality of dedicated contacts, and a plurality of ground contacts. The shared contacts in a first mode or a second mode transmit signals corresponding to the first mode or the second mode. The dedicated contacts transmit the signals corresponding to the first mode and do not transmit the signals corresponding to the second mode. The ground contacts surround the shared contacts and the dedicated contacts.

Abstract: A low voltage drive circuit (LVDC) includes a digital to analog input circuit to convert transmit digital data into combined analog outbound data, the transmit digital data has a data rate based on a host input clock, and a first portion of the combined analog outbound data has a first oscillation rate based on a first transmit channel clock and a second portion has a second oscillation rate based on a second transmit channel clock. The LVDC also includes a drive sense circuit to convert the combined analog outbound data into an analog transmit signal that is transmitted on a bus. The LVDC also includes a clock circuit to generate a transmit input clock to synchronize receiving the transmit digital data from a host, generate the first transmit channel clock based on the host input clock, and generate the second transmit channel clock based on the host input clock.

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

Abstract: According to some example embodiments, a system includes: at least one motherboard; at least one baseboard management controller (BMC); a mid-plane; and at least one storage device, wherein the at least one storage device is configured to operate in a first mode or a second mode based on a first input received from the at least one motherboard or the at least one BMC via a plurality of device ports over the mid-plane; and when operating in the second mode, the at least one storage device is configured to operate in a first speed from a plurality of operating speeds based on a second input received from the mid-plane via the plurality of device ports.

Abstract: The invention relates to an electronic system, comprising components and/or units of various kind, hence the electronic system can be called a heterogeneous system and special interfaces therein between. The invented electronic system can be applied in the electric system digital control domain and in particular it is targeting (but not limited to) control of power train of pure electric or hybrid vehicle electric motors that require hard real time and safe control.

Abstract: Embodiments of systems and methods for generating user interfaces are described. In an embodiment, a monitoring tool can observe the user's interaction with a computing device, collect input and output operation data, and calculate a user effectiveness score based on the collected data. A user interface can be generated based on the user effectiveness score to match the user's proficiency.

Abstract: A distributed control system includes a tree topology network or a daisy-chain network including a communication parent station, communication child stations, and a plurality of communication paths among the communication parent station and the communication child stations, in which the communication parent station and the communication child stations include a scheduling unit that controls a transfer cycle that is temporal intervals of data transfer. The scheduling unit sets the transfer cycle that is the fastest out of a plurality of the data as a reference cycle, counts the number of times each time the reference cycle elapses, and imparts a value of the number of times to the reference cycle as a cycle number. When the cycle number reaches an optional number, the number of times is returned to an initial value, which makes one cycle of transfer control, and the transfer control is repeatedly executed.

Abstract: An electronic device and a method of transmitting USB commands are provided. The method includes: (A) allocating a buffer area in a memory; (B) receiving a USB command; (C) retrieving control transfer information of the USB command; (D) storing the control transfer information in the buffer area; (E) repeating steps (B) to (D) until a condition for ending a control aggregation is met; (F) generating an aggregated USB command according to the content of the buffer area; and (G) transmitting the aggregated USB command.

Abstract: Systems, devices, and methods for secure communications are provided. An electronic device includes at least one wired communication port, a processor, a plurality of fiber optic communication ports, and a microcontroller. Each of the plurality of fiber optic communication ports includes an opto-electric signal converter. The microcontroller is configured to select one opto-electric signal converter by controlling power supplied to the selected opto-electric signal converter and removing power from the non-selected opto-electric signal converters. The processor is configured to route at least one of voice or data from the at least one wired communication port to the selected opto-electric signal converter.

Abstract: Multiple (e.g., two) hosts access a single memory channel (and/or device) via a memory controller. The single memory channel/device can support at most one access at a time. To reduce contention between the multiple hosts, the memory controller comprises multiple (e.g., two), independent, host ports. Each host port is associated with a write buffer(s) in the memory controller that stores write data at least until the memory controller writes the data to the memory channel. Data stored in a write buffer may be used to respond to memory access commands (e.g., reads or writes) on the ports without accessing the memory channel. In this manner, the hosts do not directly contend with each other for the single memory channel or the memory controller.

Abstract: A display device for displaying data in a process automation Ethernet network having a specified physical layer and one or more different higher layer network protocols, the display device being arranged to detect one or more subscriber devices of the network and to display measured values of the one or more subscriber devices.

Abstract: According to an aspect, a data inversion circuit configured to perform DBI-DC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal and a data transmission unit comprising, an auxiliary signal generation unit configured to generate an auxiliary signal that determines whether to perform encoding on the input data by analyzing a plurality of data symbols included in the input data, a channel comprising a plurality of data lines and a data encoding unit configured to generate encoded data by performing DBI (data bus inversion) encoding on the data based on the auxiliary signal and to transmit the generated encoded data to a data reception unit via the channel.

Abstract: In an approach for detecting and processing multiple audio signals simultaneously, an audiometric receiver system comprises a transmitter, wherein the transmitter comprises a digital signal processor, and wherein the digital signal processor comprises a quality check component, an amplifier or attenuator component, mixer component, a modulator component, and an encrypter component; and a receiver, wherein the receiver comprises a decrypter component, a demodulator component, a splitter component, and a second amplifier or attenuator component.

Abstract: Techniques for transmitting data include one or more processors of a computing device included in a network device identifying data to be transmitted; and while a data session window is open: transmitting, using a transmitter of the network device, the data to a transceiver that is included in the network device and is separate from the one or more processors, wherein the transceiver is configured to transmit the data outside of the network device; and in response to determining that there is no additional data to be transmitted, (a) delaying for a period of time, and (b) after the period of time, instructing the transceiver to end the data session window early and transition to a lower power state.

Abstract: A charging apparatus having a backup function includes a first connecting interface, a second connecting interface, a processing unit, a memory unit, and an authorizing unit. The first connecting interface is adapted to receive a power source. When the processing unit authorizes the first electronic device, the processing unit activates the backup function to back up data stored on a first electronic device connected to the second connecting interface into the memory unit. Hence, a user can use the charging apparatus to charge the first electronic device, and to back up the data stored on the first electronic device into the memory unit or to restore the data stored on the memory unit into the first electronic. The user of the first electronic device can effortlessly enjoy the data backup and restore functionality.

Abstract: An apparatus comprising a first and second terminal configured to couple the apparatus to a first and second bus wire of a communication bus; a transceiver arrangement for communicating with one or more network nodes via the communication bus, the transceiver arrangement configured to provide and receive differential signalling according to a communication scheme to/from the communication bus, wherein the communication scheme defines at least a voltage to be used to provide said differential signalling; the apparatus configured to: based on a fault detection signal indicative of the occurrence of a fault in at least the communication bus, transmit a reconfiguration signal for the network nodes and wherein at least part of the reconfiguration signal has a high-voltage-level comprising a voltage higher than that defined in the communication scheme for said differential signalling; and wherein said reconfiguration signal is configured to cause the network nodes to switch single-ended signalling.

Abstract: The present invention discloses a communication method having both defined and undefined bus communication mechanism used in an electronic that includes steps outlined below. A connection between an application program and the peripheral electronic equipment is established through a built-in driver. A proxy library and a proxy driver respectively corresponding to a user mode and a kernel mode are activated by the application program. A connection between a combination of the proxy library and the proxy driver and the peripheral electronic equipment are established by the application program. Defined commands defined by the built-in driver are transmitted to and received from the peripheral electronic equipment through a bus by the application program by using the built-in driver. Non-defined commands not defined by the built-in driver are transmitted to and received from the peripheral electronic equipment through the bus by the application program by using the proxy library and the proxy driver.

Abstract: Provided herein are techniques for AP coordinated P2P communications in a Wi-Fi network. Embodiments describe an apparatus for an AP including processing circuitry to: encode a first trigger frame, to be transmitted to a plurality of STAs associated with the AP, to query a buffer status of each STA; receive one or more response frames from one or more of the plurality of STAs, each having data to be transmitted to a target receiver STA in the plurality of STAs; allocate one or more RUs for each of a group of STAs selected from the one or more STAs, based on the one or more response frames, and using OFDMA; and encode a second trigger frame, to be transmitted to the selected group of STAs and the target receiver STA for each of the group of STAs, to indicate the allocation of RUs.

Abstract: The present invention makes it possible to reduce threats to the security of a control unit. This controller system is provided with: a control unit that performs a control calculation for controlling a controlled object; and a security unit that is responsible for security. The control unit comprises: a first interface that brokers data exchange with an external device; a communication controller that is responsible for communication with the security unit; and a restriction means that restricts data from being exchanged with the external device via the first interface if a connection between the control unit and the security unit is detected via the communication controller.

Abstract: A processor may include a plurality of columns of vector processing units arranged in a two-dimensional column array with a plurality of column stacks placed side-by-side in a first direction and each column stack having two columns stacked in a second direction. The processor may further include a memory unit divided into two portions placed on two opposite sides of the column array in the second direction. Each portion may contain two memory blocks placed side-by-side in the first direction. Each memory block may contain two cache blocks placed along a first edge abutting an adjacent memory block and a plurality banks of memory cells placed to space from the first edge in the first direction by the two cache blocks and from a second edge abutting the column array in the second direction by routing channels.

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

Abstract: In a method for data communication between a control unit and a drive system, the control unit and the drive system are connected to one another, preferably via a bus, in such a manner that data is transmitted by a telegram. The telegram includes an instruction which can be configured for recording and includes an identifier. At least one actual value, preferably a plurality of actual values, and/or of an actual value sequence, preferably a plurality of actual value sequences, of the drive system, are recorded through the instruction for recording, and at least one defined actual value from a plurality of actual values and/or recording at least one defined actual value sequence from a plurality of actual value sequences can be recorded through the identifier.

Abstract: An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

Abstract: According to an aspect, a data inversion circuit configured to perform DBI-AC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal, a channel comprising N data lines, a first auxiliary signal generation unit configured to generate a first auxiliary signal that determines whether to perform a first encoding on the input data based on the number of each of a plurality of data symbols included in the input data, a first data encoding unit configured to generate intermediate data by performing the first encoding on the input data based on the first auxiliary signal, a second auxiliary signal generation unit configured to generate a second auxiliary signal that determines whether to perform a third encoding on the intermediate data by analyzing the relationship between a plurality of data symbols at a current time point and a plurality of data symbols at a previous time point included in the intermediate data and a second data encoding unit c

Abstract: Techniques are provided for combining data block and checksum block I/O into a single I/O operation. Many storage systems utilize checksums to verify the integrity of data blocks stored within storage devices managed by a storage stack. However, when a storage system reads a data block from a storage device, a corresponding checksum must also be read to verify integrity of the data in the data block. This results in increased latency because two read operations are being processed through the storage stack and are being executed upon the storage device. To reduce this latency and improve I/O operations per second, a single combined I/O operation corresponding to a contiguous range of blocks including the data block and the checksum block is processed through the storage stack instead of two separate I/O operations. Additionally, I/O operation may be combined into a single request that is executed upon the storage device.

Abstract: A method of managing communication between a host device and a USB device via a non-USB extension medium is provided. A downstream facing port device (DFP device) receives a data request packet that includes a first buffer count from an upstream facing port device (UFP device) via the non-USB extension medium. The DFP device determines a number of data packets to request from the USB device based on a free buffer count tracked by the DFP device that represents an amount of buffer space available on the UFP device. The DFP device generates a synthetic data request packet that includes a second buffer count based on the determined number of data packets to request from the USB device. The DFP device receives a set of data packets from the USB device responsive to the synthetic data request packet, and transmits the set of data packets to the UFP device.

Abstract: A controller acquires communication destination information including at least a first external apparatus connected via a first communication interface or a second external apparatus connected via a second communication interface. The controller performs initialization of the first communication interface and the second communication interface. The initialization includes: in response to determining that an external apparatus indicated by the communication destination information is the first external apparatus, after completing initialization of the first communication interface, shifting to a communication waiting state in which transmission and reception of data is acceptable; and in response to determining that the external apparatus indicated by the communication destination information is the second external apparatus, shifting to the communication waiting state after completing initialization of the second communication interface.

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Abstract: According to various embodiments, an electronic device may include an application processor including a first embedded universal serial bus (eUSB) device for performing an eUSB function, and a processor for controlling the first eUSB device. The electronic device may further include a repeater configured to be electrically connectable between the first eUSB device and an external device. The processor is configured to monitor to detect a connection of the external device to the electronic device. The processor is further configured to identify a mode related to an operation speed of the external device. The processor is further configured to control a signal to be transmitted or received in a high speed (HS) mode between the first eUSB device and the repeater, based on the identification that the mode is a full speed (FS) mode or a low speed (LS) mode. Various other embodiments may be provided.

Abstract: A semiconductor device includes a terminal group configured to receive a first signal and a second signal from a host, a first chip electrically connected to the terminal group, and a second chip electrically connected to the terminal group. The first chip is configured to, in response to reception of the first signal, transmit a third signal corresponding to the first signal to the second chip. The first chip is configured to, when the first chip has received the second signal before the first signal, refrain from transmitting the third signal to the second chip.

Abstract: An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

Abstract: A processor interface assembly includes: a first interface circuit including a plurality of sub-interface circuits and configured to couple with a plurality of peripheral devices, wherein the plurality of peripheral devices is configured to occupy a pre-determined address space, and the pre-determined address space includes multiple sub-address spaces; and a controller including a register and configured to set a sub-address space occupied by at least one type of peripheral devices among the plurality of peripheral devices based on at least a portion of data stored in the register.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: A device may include a lane group, a command queue, and a link manager. The lane group may include a first lane and at least one or more second lanes to form a link for communicating with a host. The command queue may store commands for at least one direct memory access (DMA) device, the commands generated based on a request of the host. The link manager may, in response to detecting an event that an amount of the commands stored in the command queue being less than or equal to a reference value, change an operation mode from a first power mode to a second power mode in which power consumption is less than that of the first power mode, deactivate the at least one or more second lanes, and provide a second operation clock lower than a first operation clock to the at least one DMA device.

Abstract: A communication system includes a master unit; and a plurality of slave units including a slave unit to which a termination resistance is set, the plurality of slave units connected to the master unit via a communication line. In the communication system, the master unit includes a master communication control unit that normally sets a communication rate of communication performed with the plurality of slave units to a high baud rate, switches the high baud rate to a low baud rate after detecting that communication with the slave unit to which the termination resistance is set is disabled, transmits an instruction for switching the low baud rate to the high baud rate to the plurality of slave units after detecting that the communication with the slave unit to which the termination resistance is set is restored, and switches setting of the master unit itself to the high baud rate.

Abstract: A low-power radio-frequency (RF) receiver is characterized by a decreased current consumption over prior art RF receivers, such that the RF receiver may be used in control devices, such as battery-powered motorized window treatments and two-wire dimmer switches. The RF receiver uses an RF sub-sampling technique to check for the RF signals and then put the RF receiver to sleep for a sleep time that is longer than a packet length of a transmitted packet to thus conserve battery power and lengthen the lifetime of the batteries. The RF receiver compares detected RF energy to a detect threshold that may be increased to decrease the sensitivity of the RF receiver and increase the lifetime of the batteries. After detecting that an RF signal is being transmitted, the RF receiver is put to sleep for a snooze time period that is longer than the sleep time and just slightly shorter than the time between two consecutive transmitted packets to further conserve battery power.