Bus Interface Architecture Patents (Class 710/305)
  • Patent number: 10776288
    Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple type
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 15, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Cheng-Yu Chen, Chih-Ching Chien
  • Patent number: 10754401
    Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 25, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Srirama Chandra, Robert Bartel
  • Patent number: 10734012
    Abstract: Data bus systems and methods include a device controller coupled to a first interface for digital audio data communications in accordance with a first communications protocol, the device controller including a master bus controller for controlling a multi-drop bus in accordance with a second communications protocol; and a first slave device coupled to the multi-drop bus and configured to transmit and receive digital audio data communications with the device controller in accordance with the second communications protocol. Each transmission line end is terminated using the device attached at one end of the transmission line and by another device attached at the other end and reflections due to mismatches in impedance by inclusion of intermediate signaling nodes are controlled to allow multi-drop device support and high speed signaling. The second communications protocol supports multiple audio data rates using a fixed frame format.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 4, 2020
    Assignee: SYNAPTICS INCORPORATED
    Inventor: Jens Kristian Poulsen
  • Patent number: 10733500
    Abstract: In one embodiment, a system includes one or more electronic neurons and one or more electronic axons. Each neuron is connected to at least one electronic axon via an electronic synapse, and at least one of the one or more electronic neurons is configured to store information in a membrane potential thereof and/or at least one of the one or more electronic axons is configured to store information in an axon delay buffer thereof to act as a memory. In another embodiment, a computer-implemented method includes storing information to a memory comprising electronic neurons and electronic axons. Information is stored in either a membrane potential of at least one of the electronic neurons or in an axon delay buffer of at least one of the electronic axons. Also, each neuron is connected to at least one electronic axon via an electronic synapse.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Andreopoulos, Andrew S. Cassidy
  • Patent number: 10721310
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a thin client. The thin client establishes a remote session with a remote machine. The thin client detects a connection of a device at a first connection port. The thin client determines a category of the device. The thin client establishes a redirection channel in the remote session with the remote machine based on the category. The thin client redirects access of the device to the remote machine.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 21, 2020
    Assignee: AMZETTA TECHNOLOGIES, LLC
    Inventors: Derek Huang, Tommy Hu, Yugender P. Subramanian, Indira Valmiki
  • Patent number: 10713203
    Abstract: This disclosure relates to methods and systems for dynamically partitioning of PCIe disk arrays based on software configuration/policy distribution. In one embodiment, at least one PCIe switch has an input port operatively connected to a respective CPU and at least one output port. A multiplexer is connected between the output port(s) of the at least one PCIe switch and a PCIe disk array, for example an NVMe SSD, and is configured to connect the PCIe disk array in a first configuration to a single PCIe switch in either one-x4 port or two x2 port mode, or in a second configuration to two PCIe switches in x2 port mode. The multiplexer can dynamically switch between the first configuration and the second configuration on the fly. Switching can occur, for example, in response to a hot-swap of an NVMe SSD or a policy change.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 14, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Yun Bai, Mengshi Li, Yang Sun, Min Wang, Yepeng Chen
  • Patent number: 10714878
    Abstract: A connector system having a plurality of high-speed connector modules, an anti-decoupling connector shell, and a multi axis backshell is provided. The high-speed module provides a low signal degradation electrically conductive signal path for terminated wires of twisted pairs of wires. The high-speed module additionally provides for dense placement of the terminated wires within the connector shell. The connector shell provides an anti-decoupling mechanism to prevent decoupling of the connector shell from a socket type connector shell resulting from typical forces applied to the connector shell. The multi-axis backshell provides mechanisms to toollessly adjust the angle of the various components making up the backshell which in turn provides a specifically angled path for cables contained within the backshell.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 14, 2020
    Assignee: PIC Wire & Cable, Inc.
    Inventors: Phong Dang, Phong Thao
  • Patent number: 10707988
    Abstract: Various solutions for transport block size (TBS) determination with respect to user equipment and network apparatus in mobile communications are described. An apparatus may determine an intermediate number of information bits. The apparatus may quantize the intermediate number of information bits. The apparatus may determine a TBS according to the quantized intermediate number of information bits. The apparatus may transmit the information bits according to the TBS.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 7, 2020
    Assignee: MediaTek Singapore Pte. Ltd
    Inventors: Abdellatif Salah, Abdelkader Medles
  • Patent number: 10704973
    Abstract: A method of timing data sampling includes, in a data acquisition device, generating sampling intervals from a system clock of the data acquisition device, sampling data at the generated sampling intervals, and receiving start of frame (SOF) signals from a port, such as a USB port. For a selected number of SOF signals received, an actual number of system clock cycles is determined for a time interval corresponding to the selected number of SOF signals. The actual number of system clock cycles is compared to a nominal number of system clock cycles and a sampling interval is adjusted based on the comparison. The actual number of system clock cycles may be determined using a count-and-capture counter. The nominal number of system clock cycles may be calculated based on a nominal system clock rate and on a known SOF interval. Generating sampling intervals may include using a divide-by-N counter.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 7, 2020
    Assignee: Advanced Mechanical Technology, Inc.
    Inventors: Albert C. Drueding, Gary M. Glass
  • Patent number: 10699013
    Abstract: A device for securing USB or Firewire port interconnections includes a microcontroller comprising a processor; a first connector/lead in communication with the microcontroller and configured to be coupled with a USB or Firewire external device; and a second connector/lead in communication with the microcontroller and configured to be coupled with a protected host. An optional user interface communicates with the microcontroller. When the microcontroller detects that the external device is coupled to the first connector/lead, the processor is configured to display a prompt on the user interface for a user to initiate inputs prior to the external device being allowed to connect with the protected host; or is configured to automatically prevent the external device from being connected with the protected host if the external device is on a blacklist of devices known to have device handlers in the protected host at a BIOS level, without modifying the protected host.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: June 30, 2020
    Assignee: Honeywell International Inc.
    Inventors: Matthew Warpinski, James Christopher Kirk, Brian Adams
  • Patent number: 10692410
    Abstract: A display panel driving apparatus includes an interface, a timing controller, a gate driver, and data driver. The interface includes a data determiner to determine whether or not input image data has a communication error and to process a packet of a data stream of the input image data, even though the input image data has the communication error. The timing controller receives the processed input image data from the interface and generates a data signal, a gate control signal, and a data control signal. The gate driver generates a gate signal based on the gate control signal. The data driver generates a data voltage based on the data control signal and the data signal.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 23, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Ho-Seok Han
  • Patent number: 10664403
    Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 26, 2020
    Assignee: ATI Technologies ULC
    Inventors: Leon King Nok Lai, Qian Ma, Jimshed B. Mirza
  • Patent number: 10652045
    Abstract: A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed ring data bus apparatus with a plurality of nodes, and associated application apparatus in data communication with at least one of the nodes. A synchronous ring protocol is used to transfer data packets or frames around the ring data bus, so as to avoid data collisions. The packets or frames include both payload and control data, and may be addressed to higher layer processes of the application apparatus. In one variant, differentially signaled optical or electrical bus segments are utilized to interface with the nodes, and data is serialized before transmission on the ring data bus. In another variant, a common clock signal is transmitted around the ring with the data packets or frames.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 12, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Zvi Regev, Alon Regev
  • Patent number: 10642678
    Abstract: Identifying and selecting a specific component of a computing system, typically by accessing its PCI and PCI Express (PCIe) configuration address space, an apparatus and method discover actual control or configuration addresses and characterize each as documented, partially documented, reserved, partially reserved, documented reserved test, partially documented reserved test, or undocumented. A filtered subset is tested by accessing each address contained in the subset, and verifying either continuity or failure of operation of the tested component or the system in response to that access. Attempting to read from or write to (or both) subset addresses proves the component and system to be compliant or non-compliant with the specification.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 5, 2020
    Inventor: Phillip M. Adams
  • Patent number: 10634796
    Abstract: The present invention relates to a high-precision real-time satellite positioning apparatus and a method thereof. The present invention has technical features as follows: the apparatus includes a polygonal receiver array formed by a plurality of single-point satellite positioning receivers; an antenna phase center of each single point satellite positioning receiver is disposed at each vertex and center point of the polygonal receiver array; each single-point satellite positioning receiver includes an MCU and a receiver connected with the MCU; and all MCUs are connected in parallel and jointly connected to a processor module.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 28, 2020
    Assignee: BROADGNSS TECHNOLOGIES CO., LTD.
    Inventors: Yan Shen, Yuanbo Li
  • Patent number: 10635618
    Abstract: In some examples, an electronic device includes a hub configurator to obtain, from a port hub that expands a number of ports for the electronic device, information of topological elements of the port hub, and modify a configuration of the port hub.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 28, 2020
    Assignee: 2236008 Ontario Inc.
    Inventors: Yuchen Luo, Gervais Kafwe Mulongoy
  • Patent number: 10606788
    Abstract: The USB chipset including a data processing unit, a transmitting unit, a first pin set and a second pin set is provided. The data processing unit generates a plurality of transmission information according to first information provided by a first device. The transmitting unit processes the transmission information to generate an output signal. The first pin set is configured to transmit the output signal to a second device. The second pin set is configured to transmit the output signal to the second device. When the first pin set transmits the output signal to the second device, the second pin set does not transmit the output signal to the second device. When the second pin set transmits the output signal to the second device, the first pin set does not transmit the output signal to the second device.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 31, 2020
    Assignee: VIA LABS, INC.
    Inventors: Wei-Yu Wang, Yu-Chung Wei, Yinglien Cheng
  • Patent number: 10592285
    Abstract: An information handling system includes a processor complex with a root complex that provides N serial data lanes, where N is an integer. The information handling system also includes boot process logic that determines that a device is coupled to X of the serial data lanes, where X is an integer less than N, determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N?X, and allocates a portion of bus resources of the root complex to the device, the portion being greater (X+Y)/N.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 17, 2020
    Assignee: Dell Products, LP
    Inventors: John C. Beckett, Robert W. Hormuth
  • Patent number: 10592189
    Abstract: A non-transitory computer-readable recording medium stores an information processing program that causes a computer that constitutes an information processing apparatus including a built-in first display device, to execute a process. The process includes detecting, from outside the information processing apparatus, a state where a second display device is connected, the second display device being different from the first display device; setting both the first display device and the second display device as display destinations, when switching the display destination from the first display device to the second display device; switching the display destination to the second display device after setting both the first display device and the second display device as display destinations; and controlling a display image according to a screen specification of the second display device.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 17, 2020
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshinaga Kato
  • Patent number: 10594607
    Abstract: The present invention discloses a switching apparatus, a switching apparatus group, a data transmission method, and a computer system, and pertains to the field of computer technologies. The switching apparatus includes: a selection circuit module, a SERDES module, and a scheduling module. The selection circuit module establishes at least (n?1) static links with each of n modes, and any two static links that are connected to the selection circuit module and that belong to different nodes are connected to each other. The SERDES module is disposed on a static link connected to the selection circuit module. The scheduling module establishes connections to the selection circuit module and each of the n nodes. The selection circuit module further establishes at least one dynamic link with each of the n nodes.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: March 17, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Donghao Yu, Chenghong He, Ting Yang
  • Patent number: 10586039
    Abstract: An information processing apparatus includes a memory and a processor. The memory stores a first string of error detection codes each corresponding to a used partial area of a stack area allocated to a program. The processor generates, when execution of the program is interrupted, a differential string of error detection codes each corresponding to a used partial area of a difference between used partial areas at the time of generating the first string and used partial areas at the interruption. The processor obtains a second string of error detection codes by reflecting the differential string to the first string. The processor generates, when the execution of the program is resumed, a third string of error detection codes each corresponding to a used partial area of the stack area at the resumption. The processor detects stack destruction based on collation between the second string and the third string.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: March 10, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Yoshihisa Morizumi
  • Patent number: 10576913
    Abstract: According to embodiments, a vehicle wire harness includes one end to be electrically connected to a control unit mounted on a vehicle and the other end to be electrically connected to one or more light sources. The vehicle wire harness further includes a driver operation portion configured to receive a control signal designating a lighting form for the one or more light sources from the control unit and to output a drive pattern for driving the one or more light sources. The driver operation portion is subordinate to the control unit.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 3, 2020
    Assignee: YAZAKI CORPORATION
    Inventor: Terumitsu Sugimoto
  • Patent number: 10582636
    Abstract: An apparatus includes a computer server having a chipset and a baseboard management controller, wherein the chipset includes a first serial bus controller, and wherein the baseboard management controller includes a second serial bus controller. The apparatus further includes a serial bus port disposed along an external panel of a server enclosure that houses the computer server, wherein the serial bus port is accessible for connection with a connector of a serial communication cable. Still further, the apparatus includes a switch that selectively connects the serial bus port to either the first serial bus controller or the second serial bus controller, wherein the switch is controlled by an output signal from the baseboard management controller.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: March 3, 2020
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Antonio Abbondanzio, Edward Klodnicki
  • Patent number: 10558388
    Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Craig Hanson, Sun Young Lim, Indong Kim
  • Patent number: 10547535
    Abstract: A relay device is connected to two networks of a plurality of layered networks and connected to a first communication device directly under a first lower layer network that is on a lower level of the two networks. The relay device includes a storage unit that stores connection information including model identification information associated with each of a second communication device and the first communication device and information on the number of connected second communication devices or on a memory area assigned to each of the first communication device and the second communication device, the second communication device being connected to a lower side through a second lower layer network that is situated lower than the first lower layer network, the connection information being arranged in a format capable of specifying a layer of a network to which each communication device is connected.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Isamu Yamada
  • Patent number: 10536398
    Abstract: In an example, there is disclosed an example of a system and method for plug and play in a controller based network. Aspects of the embodiments are directed to a network switch of a fabric network, the network switch configured to detect a connection of a device to the network switch, the device compliant with a remote integrated services engine (RISE) protocol; receive, from the device, a programming instruction for switching compliant with the RISE protocol; and distribute the programming instruction to one or more other network switches of the fabric network.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: January 14, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Samar Sharma, Venkatabalakrishnan Krishnamurthy, Ravinder Reddy Amanaganti
  • Patent number: 10536527
    Abstract: Methods and systems for controlling the collection and storage of data are described. In general, the system includes a human-machine interface (HMI), and the HMI includes an interface that is configured to receive and connect with an external device. Generally, the methods and systems involve the use of an external storage device that can store, for example, collected data and/or analyzed data.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 14, 2020
    Assignee: Thermo King Corporation
    Inventors: Luis Ramon Ocejo, Miguel A. Ferrer, Kirk Spencer
  • Patent number: 10534460
    Abstract: An information processing apparatus that controls a display disposed on a casing of the information processing apparatus to display an image; outputs, by a communication interface of the information processing apparatus, the image displayed on the display; detects an orientation of the casing; and generates different images as the image displayed on the display and the image output by the communication interface when a predetermined change of orientation of the casing is detected.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: January 14, 2020
    Assignee: SONY CORPORATION
    Inventor: Takamoto Tsuda
  • Patent number: 10530325
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A receiver includes multiple series inductors moved from a signal path to sampling circuitry to a termination path used for impedance matching. The removed direct current (DC) resistances of the inductors in the signal path reduces signal attenuation. The termination path has alternating current (AC) reactances of the inductors, which provide a frequency-dependent termination impedance. This termination impedance provides a positive reflection coefficient for high operating frequencies, which boosts the input signal being received by the sampling circuitry.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 7, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Dean E. Gonzales, Xuan Chen, Jeffrey Cooper, Milam Paraschou
  • Patent number: 10515044
    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. An apparatus includes a serial bus, and an originating device and destination device coupled to the serial bus. The originating device may be configured to generate a first virtual GPIO packet that carries a payload representative of signaling state of physical GPIO in the originating device, generate a second virtual GPIO packet that carries a payload representative of an event generated by a processor in the originating device, and transmit the first and second virtual GPIO packets on the serial bus. The destination device may be configured to receive the second virtual GPIO packet from the serial bus, and communicate the event to a processor of the destination device or modify signaling state of physical GPIO in the destination device in accordance with the payload of the second virtual GPIO packet.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Dominic Wietfeldt, Radu Pitigoi-Aron, Lalan Jee Mishra
  • Patent number: 10503239
    Abstract: An electronic device is connectable with a host via a serial interface including a link configured with a plurality of lanes, each of which includes a differential signal wire pair for transmission and a differential signal wire pair for reception. The electronic device includes a plurality of transmitter circuits that respectively transmit data via the differential signal wire pair for transmission of each of the corresponding lanes, a plurality of receiver circuits that respectively receive data via the differential signal wire pair for reception of each of the corresponding lanes, and a control circuit. The control circuit causes a state of the electronic device to transition from a normal operation state to a state in which the plurality of transmitter circuits are maintained in an active state and the plurality of receiver circuits are in an inactive state except for one receiver circuit corresponding to one of the lanes.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akinori Bito
  • Patent number: 10474361
    Abstract: Apparatus and method for managing data. A host device is coupled to multiple hybrid data storage devices each having a primary non-volatile memory (NVM), a secondary NVM, a top level controller and a secondary controller. During a normal I/O processing mode, host access commands are serviced by the top level controllers to direct transfers with the respective primary and secondary NVMs. During a front end I/O processing mode, the host device forms a consolidated, distributed memory space in which data are separately stored to the secondary NVMs by the host device. The primary NVM may be rotatable recording media and the secondary NVM may be flash memory. The secondary NVM may be in the form of removable SSD cards that plug into the storage devices to support replacement and performance upgrades, as well as allowing transitions between cold and hot data storage modes in a single system.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 12, 2019
    Assignee: Seagate Technology LLC
    Inventor: Christopher Nicholas Allo
  • Patent number: 10451664
    Abstract: An interconnect device is disclosed for detecting whether an vehicle on-board diagnostics (OBD) data port includes a blocking diode or equivalent, that prevents back feeding of power through the OBD data port. If a diode is detected, the interconnect device alerts the user that the power cannot be back fed through the OBD II port connector. In such a condition, an alternate means is used to preserve the data mentioned above. If a diode is not detected by the interconnect device, the interconnect device displays this fact to the user. The interconnect device includes circuitry for detecting and displaying whether a diode is connected in series with a power pin of the OBD II port connector.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 22, 2019
    Assignee: Schumacher Electric Corporation
    Inventors: Patrick J. Clarke, John S. Whiting, John B. Borke, Matthew Adam Heins, Samuel I. Weisbard
  • Patent number: 10452544
    Abstract: Embodiments are described for a multi-node file system, such as a clustered or distributed file system, with a file system buffer cache and an additional host-side tier non-volatile storage cache such as 3DXP storage. Cache coherency can be maintained by one of three models: (i) host-side tier management, (ii) file system management, or (iii) storage array management. performing a storage tier-specific file system action in a file system that comprises a namespace that spans multiple tiers of storage.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 22, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Stephen Smaldone, Ian Wigmore, Arieh Don
  • Patent number: 10445256
    Abstract: The disclosure relates to a function connection unit for connecting at least one parameterizable functional module, including at least one functional module connection configured to connect to the at least one parameterizable functional module; a communication interface that is configured to receive first parameter data records, the first parameter data records including parameter data for parameterizing the at least one parameterizable functional module and first parameter indices that index a memory area for the parameter data; and a processor configured to convert the first parameter indices into second parameter indices to obtain second parameter data records, the second parameter indices indexing a predetermined memory area of the at least one parameterizable functional module for storing the parameter data in the at least one parameterizable functional module.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 15, 2019
    Assignee: Phoenix Contact GmbH & Co. KG
    Inventor: Özkan Öztürk
  • Patent number: 10437760
    Abstract: A method to intercept an universal serial bus (USB) related request and to respond the intercepted request in a virtualized environment includes connecting a virtual USB peripheral controller in a virtualization software in the virtualized environment to a virtual machine in the virtualized environment. An USB data access request generated by the virtual machine may be intercept by the virtual USB peripheral controller so that the USB data access request does not reach a kernel space of the virtualization software and physical hardware resources supporting the virtualized environment. The method further includes generating a response according to the USB data access request and a process called by a firmware framework module of the virtual USB peripheral controller and transmitting generated response towards the virtual machine.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 8, 2019
    Assignee: VMware, Inc.
    Inventors: Nan An, Jianbin Sun, Yan Zhao, Zhao Gao
  • Patent number: 10430225
    Abstract: Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a bus manager circuit. The bus manager circuit comprises a first bus interface configured to be coupled with a first hardware device of the server, and a second bus interface configured to be coupled with a second hardware device of the sever. The bus manager further includes a control module. Under a first mode of operation, the control module is configured to receive an access request from the first hardware device to access the second hardware device, and responsive to determining not to grant the access request based on a pre-determined access policy, and block at least some of data bits corresponding to the access request from the second bus interface. The control module may also process the access request in a different manner under other modes of operations.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason Alexander Harland, Nathan Pritchard, Michael Joseph Kentley
  • Patent number: 10432730
    Abstract: An apparatus for inhibiting data on a bi-directional bus includes a first portion having a first analog port and a digital output. A second portion has a second analog port and a digital input, and the digital output is operably coupled to the first digital input. The digital output of the first portion is configured to produce a digital representation of an analog input signal presented to the first analog port. Likewise, the second analog port of the second portion is configured to produce an analog output representation of a digital signal presented to the digital input. The first and second portion cooperate to inhibit the propagation of data presented to the second analog port as an input.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 1, 2019
    Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
    Inventor: David C Prentice
  • Patent number: 10417165
    Abstract: Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from another electronic device. The other electronic device is configured to provide a protocol indicator that indicates a particular communication protocol with which the other electronic device is configured to communicate through an electrical connector of the electronic device. A method includes receiving a protocol indicator from another electronic device through an electrical connector. The protocol indicator indicates a communication protocol. The method also includes communicating with the other electronic device through the electrical connector using the indicated communication protocol.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 10417148
    Abstract: A bus traffic control apparatus includes a sizing block, a traffic request controller and a bus master engine. The sizing block is configured to determine a data transmitting size of a bus master based on bus traffic information. The traffic request controller is configured to control transmission of data from the bus master based on the data, a destination of the data, the data transmitting size. The bus master engine is configured to transmit the data to the destination in the data transmitting size based on the data, the destination of the data, the data transmitting size and a request received from the traffic request controller.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Chul Song, Yong Kim, Seong-Wook Cho
  • Patent number: 10417155
    Abstract: A system includes at least two ports (22, 24, 26) connected to particular electronic products. The system is able to intelligently detect the master/slave status of the electronic device and establish connecting routes among the ports (22, 24, 26) and the system accordingly. Each of the connecting route transfers at least electric power and optionally data. The system alleviates users' concern whether the electronic product to be connected to the system acts as a master or a slave. As such, electronic products can be connected to any port (22, 24, 26) available in the system.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: September 17, 2019
    Assignee: MODUWARE PTY LTD
    Inventors: Frank Thomas Filser, Hubertus Friedrich Wasmer, Lech Alexander Murawski
  • Patent number: 10416705
    Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Hyeong Soo Jeong
  • Patent number: 10409268
    Abstract: A field device management system include a plurality of field devices equipped in a plant, one or more host devices equipped at a place distant from the plant and configured to connect to the field devices via a first network, and a terminal apparatus configured to connect to the field devices via a second network and to connect to the host devices via a third network. The terminal apparatus includes a first communication interface module configured to perform field communication with the field devices via the second network, a second communication interface module configured to perform near field communication with the host devices via the third network, and a controller that, when updating data of any one of the field devices, performs communication with the host devices through the second communication interface module, and receives update permission information from the host device through the second communication interface module.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 10, 2019
    Assignee: Yokogawa Electric Corporation
    Inventor: Satoru Ochiai
  • Patent number: 10402330
    Abstract: Examples include a processor including a coherency mode indicating one of a directory-based cache coherence protocol and a snoop-based cache coherency protocol, and a caching agent to monitor a bandwidth of reading from and/or writing data to a memory coupled to the processor, to set the coherency mode to the snoop-based cache coherency protocol when the bandwidth exceeds a threshold, and to set the coherency mode to the directory-based cache coherency protocol when the bandwidth does not exceed the threshold.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Mustafa Hajeer, Thomas Willhalm, Francesc Guim Bernat, Benjamin Graniello
  • Patent number: 10397057
    Abstract: The present disclosure relates to communication networks. Some embodiments may include a communication network with two or more network nodes each comprising: a receiver discerning the signal quality of received signals; a transmitter sending signals at different data rates; and a controllable terminating impedance. A network node transmits the discerned signal quality to one or more additional network nodes, a network node records the signal qualities and corresponding values of the terminating impedances of the respective network nodes. A network node prescribes for additional network nodes a new respective value to set as a terminating impedance. A network node determines new terminating impedance values to optimize the data rate between the various network nodes and the signal quality at each of the network nodes.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 27, 2019
    Assignee: SIEMENS SCHWEIZ AG
    Inventors: Bernhard Blattmann, Oskar Camenzind, Juerg Eggerschwiler, Roland Kueng
  • Patent number: 10395037
    Abstract: An information handling system may include a non-volatile memory and a processor system coupled to the non-volatile memory to access the non-volatile memory. The processor system may include a processor core and a corresponding platform security processor (PSP) having PSP memory. A BIOS of the processor system running on the processor core may store data at locations in the non-volatile memory and provide these memory locations to the PSP. The PSP stores these non-volatile memory locations in PSP memory and maintains the data in the non-volatile memory at the locations during an event affecting the processor system.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 27, 2019
    Assignee: Dell Products, LP
    Inventors: Anh Luong, Vijay Bharat Nijhawan
  • Patent number: 10387072
    Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Sarathy Jayakumar, Mohan J. Kumar, Ashok Raj, Hemalatha Gurumoorthy, Ronald N. Story
  • Patent number: 10372646
    Abstract: A method and system for adapting communication between a low-speed interface and a high-speed interface is disclosed. The method includes retrieving configuration instructions in response to a power-up of a microcontroller, where the configuration instructions associated with a low-speed communication protocol. The method includes sending the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method includes retrieving, by the microcontroller, mapping instructions associated with a high-speed communication protocol.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 6, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: James V. Henson
  • Patent number: 10372645
    Abstract: A universal serial bus (USB) type C transmission line includes a host-to-host bridge, a first multiplexer, and a second multiplexer. When a first device and a second device are coupled to the first multiplexer and the second multiplexer respectively, the first multiplexer determines whether the first device is a host or a slave device and the second multiplexer determines whether the second device is another host or another slave device, and the first device optionally communicates with the second device through the host-to-host bridge, the first multiplexer, and the second multiplexer, or through the first multiplexer and the second multiplexer according to determination results of the first multiplexer and the second multiplexer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 6, 2019
    Assignee: eEver Technology, Inc.
    Inventors: Shih-Min Hsu, Shao-Hung Chen, Chien-Cheng Kuo
  • Patent number: 10365624
    Abstract: In order to reduce the labor required in order for a user to manually input and register the identification information of a device scheduled to be connected to a slave device, a device communication management unit (10) generates configuration settings information that includes the identification information of a device (20) scheduled to be connected to a device communication port (110), on the basis of the identification information of the device (20) connected to the device communication port (110).
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: July 30, 2019
    Assignee: OMRON Corporation
    Inventors: Toshiyuki Ozaki, Yasuhiro Kitamura