Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: A device may include a lane group, a command queue, and a link manager. The lane group may include a first lane and at least one or more second lanes to form a link for communicating with a host. The command queue may store commands for at least one direct memory access (DMA) device, the commands generated based on a request of the host. The link manager may, in response to detecting an event that an amount of the commands stored in the command queue being less than or equal to a reference value, change an operation mode from a first power mode to a second power mode in which power consumption is less than that of the first power mode, deactivate the at least one or more second lanes, and provide a second operation clock lower than a first operation clock to the at least one DMA device.

Abstract: A communication system includes a master unit; and a plurality of slave units including a slave unit to which a termination resistance is set, the plurality of slave units connected to the master unit via a communication line. In the communication system, the master unit includes a master communication control unit that normally sets a communication rate of communication performed with the plurality of slave units to a high baud rate, switches the high baud rate to a low baud rate after detecting that communication with the slave unit to which the termination resistance is set is disabled, transmits an instruction for switching the low baud rate to the high baud rate to the plurality of slave units after detecting that the communication with the slave unit to which the termination resistance is set is restored, and switches setting of the master unit itself to the high baud rate.

Abstract: A low-power radio-frequency (RF) receiver is characterized by a decreased current consumption over prior art RF receivers, such that the RF receiver may be used in control devices, such as battery-powered motorized window treatments and two-wire dimmer switches. The RF receiver uses an RF sub-sampling technique to check for the RF signals and then put the RF receiver to sleep for a sleep time that is longer than a packet length of a transmitted packet to thus conserve battery power and lengthen the lifetime of the batteries. The RF receiver compares detected RF energy to a detect threshold that may be increased to decrease the sensitivity of the RF receiver and increase the lifetime of the batteries. After detecting that an RF signal is being transmitted, the RF receiver is put to sleep for a snooze time period that is longer than the sleep time and just slightly shorter than the time between two consecutive transmitted packets to further conserve battery power.

Abstract: An apparatus, system, and method are provided for context-based protocol data unit (PDU) identifier provisioning. A PDU service module determines, based on a first PDU identifier and using a LUT associated with servicing a PDU, a signal identifier associated with a set of signals to include in the PDU. The PDU service module generates the PDU based on the LUT associated with servicing the PDU. The PDU service module transmits the PDU and the first PDU identifier to the router module. The router module determines, based on the first PDU identifier and using a LUT associated with routing the PDU, a communication bus and an interface module associated with the communication bus. The router module determines, based on the first PDU identifier and using a LUT associated with the interface module, a second PDU identifier. The router module transmits the PDU and the second PDU identifier to the interface module.

Abstract: Data may be communicated from a sender device to a receiver device over enabled or selected byte positions or other data bit groups of a data bus. The sender device may determine data values to be sent over the data bus and may determine which byte positions are enabled or selected and which are not selected. The sender device may also determine a code. The code may be a value that is not included in the data values to be sent over the data bus. The sender device may then send the selected data values in selected byte positions of the data bus and send the code in non-selected byte positions of the data bus. The sender device may also send the code to the receiver device separately from the data bit lanes of the data bus.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

Abstract: A method for transmitting, by a host, a notification to a subscriber may include: setting a plurality of subscription conditions based on a cross resource; detecting each event that satisfies each of the plurality of subscription conditions; and, when all the plurality of subscription conditions are satisfied, transmitting a notification for the cross resource to the subscriber. The plurality of subscription conditions may have a priority order.

Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.

Abstract: A GENZ port structure includes a body, a plurality of high-speed input pins, a plurality of high-speed output pins, a plurality of ground pins, a power supply pin, a plurality of differential clock pins, and a plurality of parameter setting pins. The main body includes a first side and a second side. The plurality of high-speed input pins are arranged on the first side. The plurality of high-speed output pins are arranged on the second side. The plurality of ground pins are interspersed between the plurality of high-speed input pins and the plurality of output pins. The power supply pins, the plurality of differential clock pins and the plurality of parameter setting pins are respectively arranged on one of the first side or the second side. The plurality of parameter setting pins are used to adjust an internal parameter setting of the GENZ port structure.

Abstract: Methods and apparatuses directed to more efficient data transfers within die architectures. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic can receive an initial data transfer request over the first communication bus, and determine a final address of the initial data transfer request. Further, the controller logic can assert a chip select signal of the second communication bus to initiate a data exchange. While asserting the chip select signal, the controller logic can receive an additional data transfer request over the first communication bus, and determine an initial address of the additional data transfer request. Based on the determined initial and final addresses, the controller logic can initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.

Abstract: Various data bus monitoring, analysis, and logging systems, devices, and methods are described herein. In one example, an apparatus includes a first circuit configured to monitor first packets among traffic carried by one or more first directional lanes of a communication link established between a host and one or more endpoint devices and determine header information for the first packets. The apparatus includes a second circuit configured to detect second packets among traffic carried by one or more second directional lanes of the communication link based at least in part on the header information determined for the first packets. The apparatus includes an analysis element configured to establish transaction metadata comprising properties of transactions on the communication link based at least on correlations among the first packets and the second packets.

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

Abstract: A user station for a serial bus system and a method for transferring data with manipulation protection in a serial bus system. The user station includes a communication control device for creating messages which are to be transmitted serially via a bus line to at least one other user station of the bus system, and/or for reading the messages which have been received serially from the bus line. The communication control device is designed to use a predetermined communication rule for creating and/or reading messages, and the communication control device, for creating and/or reading messages, is designed to use at least one rule for creating and/or reading the messages, which is different from the predetermined communication rule, when a predetermined trigger occurs.

Abstract: A plasma processing method includes performing a first plasma processing in a processing chamber in a first period, and performing a second plasma processing in the processing chamber during a second period continuously after the first period. In the first period and the second period, a first radio-frequency power for bias is continuously supplied to a lower electrode. A second radio-frequency power for plasma generation may be supplied as a pulsed radio-frequency power in a first partial period in each cycle of the first radio-frequency power in the first period. The second radio-frequency power may be supplied as a pulsed radio-frequency power in a second partial period in each cycle of the first radio-frequency power in the second period.

Abstract: A device includes a memory, a plurality of registers, a multiplexer/demultiplexer circuit, and a controller circuit. The memory stores a plurality of pages of pointers and a table of commands. The plurality of registers store information about a plurality of target devices. The multiplexer/demultiplexer circuit selects (i) information from a register of the plurality of registers based on a request received from a target device of the plurality of target devices, (ii) a page from the plurality of pages based on the selected information, and (iii) a pointer from the selected page based on the selected information. The controller circuit executes a command from the table of commands based on the selected pointer.

Abstract: A method, computer program product, and computing system for allocating a first number of tokens from a plurality of tokens for processing read IO requests from a read IO queue, thus defining a number of allocated read tokens. A second number of tokens may be allocated from the plurality of tokens for processing write IO requests from a write IO queue, thus defining a number of allocated write tokens. It may be determined that the processing of the write IO requests is throttled. In response to determining that the processing of the write IO requests from the write IO queue is throttled, a maximum allowable number of write tokens may be defined. Additional tokens may be allocated for processing the read IO requests from the read IO queue based upon, at least in part, the maximum allowable number of write tokens and the number of allocated write tokens.

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

Abstract: Techniques for transmitting data include identifying data to be transmitted; and in response to a data session window being open: transmitting the data to a transceiver via a transmitter; determining whether there is additional data to be transmitted and determining whether the transmitter has transmitted the data to the transceiver; and in response, instructing the transceiver to end the data session window early and transition to a lower power state.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit includes: a data determination module that determines whether to flip the current input data according to the previous depending on the number of changed data bits between the previous input data and the current input data of the semiconductor memory so as to generate a flip flag data and an intermediate data; a data buffer module that is used to determine an initial state of a global bus according to an enable signal and the intermediate data; and a data receiving module that receives the global bus data on the global bus, and receives the flip flag data through the flip flag signal line, and that is used to decode the global bus data according to the flip flag data, and write the decoded data into a memory block of the semiconductor.

Abstract: A processing system includes a controller of a transmitting module for transmitting data to a receiving module across an interconnect compliant with a processor interconnect protocol. The controller indicates the beginning and end of a variable-length data burst using data primitives that are N symbols (bytes) in length, rather than using data primitives that are M symbols in length, as specified by the processor interconnect protocol, where N<M. The controller of the transmitting module signals the beginning of a data burst by sending a short primitive indicating either the beginning of a data burst or signaling the receiving module to reset error detection logic so that error detection information based on the data burst can be calculated. The controller automatically inserts another short primitive indicating the end of a data burst when there is no data to transmit, thus accommodating data bursts of variable lengths.

Abstract: A system includes multiple memory-compute nodes coupled to one another over a scale fabric, where each memory-compute node includes a hybrid threading processor; a memory controller; a fabric interface; and a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller, wherein the fabric interface supports a first virtual channel (VC0), and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to the scale fabric.

Abstract: Disclosed herein are methods, systems, and devices for providing galvanic isolation and low power wakeup of circuitry. According to one embodiment, an apparatus includes first isolation circuitry, second isolation circuitry, and first control circuitry. The first isolation circuitry includes a first primary interface and a first secondary interface. The first primary interface is galvanically isolated from the first secondary interface. The second isolation circuitry includes a second primary interface and a second secondary interface. The second primary interface is galvanically isolated from the second secondary interface. The first control circuitry is electrically coupled with the first secondary interface and the second secondary interface.

Abstract: Disclosed is a graphics processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first graphics processing unit (GPU) dividing to-be-processed data into a first input part and a second input part, and processing the first output part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit and outputting the second output data to the main SoC via the external circuit; and a second GPU receiving the second input part from the second transceiver circuit and processing this part to provide the second output data for the second transceiver.

Abstract: Systems and methods of identifying infinite call loops using custom tracking headers are provided. In one exemplary embodiment, a method is performed by a first instance of a microservice operated by a first network node in a distributed microservice system having instances of one or more microservices operated by network nodes with each instance having a data cache operable to share data between instances of that microservice. The method includes receiving an indication that includes a message to access data that may be available in a data cache of an instance of the microservice, the indication also including one or more tracking identifiers with each tracking identifier corresponding to an instance of the microservice that successively sends or receives the message so as to determine that the message corresponds to a same message previously sent or received by the same instance of the microservice.

Abstract: A data storage device including a first printed circuit board (PCB) and a second PCB. The first PCB includes a controller, an interface configured to interface with a host device, and a first connector. The second PCB includes a non-volatile memory and a second connector. The second connector is configured to couple to the first connector to establish a communication connection between the controller and the non-volatile memory.

Abstract: Methods, systems, and devices for power management of a memory device are described. An apparatus may include a substrate and an input/output (I/O) interface and memory device coupled with the substrate. The I/O interface may communicate with a host device and the memory device may store data associated with the host device. The apparatus may include a power management component for providing one or more supply voltages to the memory device. The power management component may receive input voltages associated with the substrate and provide the supply voltages to the memory device based on the input voltages. The power management component may include a first portion integrated with the memory device and a second portion coupled with the substrate. The first portion may include control circuitry for the power management component and the second portion may include passive components for the power management component.

Abstract: The disclosure relates to a transceiver device, an electronic control unit and an associated method. The transceiver device is suitable for communicating between one or more network protocol controllers and a network bus and comprises: first interface circuitry configured to communicate with the one or more network protocol controllers; second interface circuitry configured to communicate with the one or more network protocol controllers; and selector circuitry configured to switch communication with the one or more network protocol controllers from the first interface circuitry to the second interface circuitry in response to a communication error in data carried on the first interface circuitry.

Abstract: In a system and method of operating a system that includes a controller and a first bus participant and a successor, the bus participant and successor each has a circuit arrangement arranged between an output and an input, a first resistor is arranged between the output and the supply voltage terminal, a second resistor is arranged between the input and a ground terminal, a third resistor can be arranged between the input and the supply voltage terminal by a first controllable semiconductor switch, and a fourth resistor can be arranged between the output and the supply voltage terminal by a second controllable semiconductor switch.

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

Abstract: A link interface is provided of a communication protocol using idle flow control digits (flits) to maintain link continuity. The link interface includes: a physical layer of the communication protocol configured to transmit and receive flits via a link, wherein the communication protocol provides for idle flits of first and second sizes for maintaining link continuity, the first size being smaller than the second size; and a data link layer configured to transmit and receive flits to/from the physical layer. The data link layer is configured to remove idle flits of the first size received from the physical layer and to report cyclic redundancy check errors of filtered first sized idle flits in a correct order in relation to other flits.

Abstract: A memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and operate any one of different control schemes for each of the first memory blocks based on a number of first not-open (N/O) strings included in each of the first memory blocks, respectively.

Abstract: A method includes generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplex data rate (XDR) of the first signal pin and the second signal pin. The channel configuration includes an association of the XDR to a channel. The method also includes determining a signal pin channel assignment based on the channel configuration, updating the channel configuration based on the signal pin channel assignment and a wirelength representative of a total distance between the first signal pin, the second signal pin, and physical ports of the channel, and performing socket instantiation based on the updated channel configuration and the signal pin channel assignment.

Abstract: An image reading apparatus includes a first communication device provided communicatively with a first information processing apparatus, a second communication device provided communicatively with a second information processing apparatus, and a processor to receive a setting for a transmission destination of an input image, prohibit transmission of the input image via the second communication device when the first information processing apparatus that can communicate via the first communication device is set as the transmission destination of the input image, determine whether the first communication device is in a state physically communicable with a network. The processor permits transmission of the input image via the second communication device when the first information processing apparatus is set as the transmission destination of the input image and it is determined that the first communication device is not in a state physically communicable with the network.

Abstract: A system and method for scaling resources of a secondary network for disaster recovery uses a disaster recovery notification from a primary resource manager of a primary network to a secondary resource manager of the secondary network to generate a scale-up recommendation for additional resources to the secondary network. The additional resources are based on latest resource demands of workloads on the primary network included in the disaster recovery notification. A scale-up operation for the additional resources is then executed based on the scale-up recommendation from the secondary resource manager to operate the secondary network with the additional resources to run the workloads on the secondary network.

Abstract: There is provided a semiconductor apparatus including a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, in which at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: In an approach to protecting against out-of-bounds buffer references, an apparatus comprises one or more processor cores and a bounds-checking functional unit in each processor core configured to manage bounds information for one or more memory buffers. When a buffer is allocated, an address range of the buffer is stored. When a pointer is assigned an address within the address range of the buffer, the address range of the buffer is associated with the pointer. When the pointer is used to compute an address for an operation, whether the address for the operation is within the address range associated with the pointer is determined. If the address is not within the address range associated with the pointer, signaling that an error has occurred.

Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Abstract: Methods and apparatus for dynamically provisioning virtualized functions in a Universal Serial Bus (USB) device by means of a virtual USB hub. The virtual USB hub includes a USB upstream port configured to be connected to a host system and at least one external bus or external interface to which devices including non-USB devices or computing devices in which non-USB devices are embedded may be connected. The virtual USB hub is configured to detect the non-USB devices and/or functions performed by the non-USB devices and generate corresponding virtual USB configuration information under which virtual USB devices and/or functions are connected to downstream virtual ports in the virtual USB hub. The virtual USB configuration is presented to the host computer to enable the host computer to communicate with the non-USB devices and/or their functions.

Abstract: Embodiments of systems and methods for high-speed Out-of-Band (OOB) management links for inter-Baseboard Management Controller (BMC) communications in High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include: a system BMC; and an accelerator tray comprising: (a) one or more managed subsystems, (b) a tray BMC coupled to the one or more managed subsystems, and (c) a Field-Programmable Gate Array (FPGA) coupled to the tray BMC and to the system BMC.

Abstract: A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.

Abstract: An apparatus, such as an image forming apparatus, includes a Universal Serial Bus (USB) host interface configured to connect to a USB device, a direct current to direct current (DC-DC) converter configured to supply power to the USB device connected to the USB host interface, and a control unit configured to switch the DC-DC converter from a pulse width modulation (PWM) mode to a pulse frequency modulation (PFM) mode based on a type of the USB device connected to the USB host interface.

Abstract: In one or more embodiments, an information handling system (IHS) manufacturer is configured to: manufacture multiple motherboards configured to be installed in multiple IHS product lines; respectively install multiple non-volatile memory media on the multiple motherboards; store first product line firmware, associated with a first product line of the IHS manufacturer, via the multiple non-volatile memory media; provide a first portion of the multiple motherboards to a first division; and provide a second portion of the multiple motherboards to a second division; the first division is configured to: permanently store a first IHS identity type on the first portion of the multiple motherboards; and the second division is configured to: permanently store a second IHS identity type on the second portion of the multiple motherboards; and store second product line firmware via non-volatile memory media of the second portion of the multiple motherboards.

Abstract: Systems and methods relate generally to contextual features for a printing device. In an example method thereof, features of a printing device configuration are queried by a firmware service. The features obtained by a first dynamic scheduling service associated with the printing device are packaged. The features packaged are retrieved to provide a features list thereof by a second dynamic scheduling service for a driver associated with the printing device. Dynamic scheduling data is generated by an artificial intelligence service including deactivating one or more of the features responsive to a policy. The generating of the dynamic scheduling data includes filtering the features using the policy by the artificial intelligence service. A dynamic user interface is created by the second dynamic scheduling service responsive to the dynamic scheduling data.

Abstract: In a network in which devices are classified into a plurality of layers, a physical first line is connected to an outdoor unit and a first indoor unit, which are first-layer devices, and a physical second line is connected to a second indoor unit, which is a second-layer device. A first intermediary unit, which is a first intermediary device, includes a first filter always connected to the first line and the second line. The first intermediary unit communicates with the outdoor unit and the second indoor unit via a first signal. The first filter is installed so as not to attenuate a high-frequency first signal used for communication among the outdoor unit, the first indoor unit, the first intermediary unit, and the second indoor unit and so as to attenuate a low-frequency second signal used for communication between the first intermediary unit and the second indoor unit.

Abstract: A bus coupler for a network, in particular for an optical ring network, includes: a bus participant interface for data connection to at least one bus participant device; a bus receiving interface for receiving bus input data via a bus line; a bus transmitting interface for transmitting bus output data via the bus line; and a control unit for generating bus output data based on participant input data received via the bus participant interface, the bus transmission data including bus control data, and to transfer the bus output data to a further bus coupler by the bus transmitting interface. The control unit specifies a control signal based on the bus input data received by the bus receiving interface and performs a relaying of the bus input data to the further bus coupler based on the specified control signal.

Abstract: Systems and methods of identifying infinite call loops using custom tracking headers are provided. In one exemplary embodiment, a method is performed by a first instance of a microservice operated by a first network node in a distributed microservice system having instances of one or more microservices operated by network nodes with each instance having a data cache operable to share data between instances of that microservice. The method includes receiving an indication that includes a message to access data that may be available in a data cache of an instance of the microservice, the indication also including one or more tracking identifiers with each tracking identifier corresponding to an instance of the microservice that successively sends or receives the message so as to determine that the message corresponds to a same message previously sent or received by the same instance of the microservice.

Abstract: A method for monitoring control-flow integrity in a low-level execution environment, the method comprising receiving, at a monitor, a message from the execution environment indicating that the execution environment has entered a controlled mode of operation, receiving, at the monitor, a data packet representing execution of a selected portion of a control-flow process at the execution environment, identifying, using the data packet, a pathway corresponding to the selected portion of the control-flow process from a set of permissible control-flow pathways and determining whether the identified pathway corresponds to an expected control-flow behaviour.

Abstract: Provided are an adapter, a terminal device and an adapter system. The adapter includes: a universal serial bus type-C (USB-C) plug cooperatively connected to a USB-C interface of the terminal device, a USB socket cooperatively connected to a charging plug, and a headset socket cooperatively connected to a headset plug, where a first communication pin of the USB-C plug is connected to a first communication pin of the USB socket, a second communication pin of the USB-C plug is connected to a second communication pin of the USB socket, a first sound channel pin and a second sound channel pin of the USB-C plug are connected to a right sound channel signal pin and a left sound channel signal pin of the headset socket in one-to-one correspondence.