Bus Interface Architecture Patents (Class 710/305)
  • Patent number: 11513799
    Abstract: Embodiments of the present disclosure relate to chained buffers in a neural processor circuit. The neural processor circuit includes multiple neural engines, a planar engine, a buffer memory, and a flow control circuit. At least one neural engine operates as a first producer of first data or a first consumer of second data. The planar engine operates as a second consumer receiving the first data from the first producer or a second producer sending the second data to the first consumer. Data flow between the at least one neural engine and the planar engine is controlled using at least a subset of buffers in the buffer memory operating as at least one chained buffer that chains flow of the first data and the second data between the at least one neural engine and the planar engine.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 29, 2022
    Assignee: Apple Inc.
    Inventor: Christopher L. Mills
  • Patent number: 11507526
    Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive first data from a first device via a first two-wire interface (TWI) bus; provide the first data to a second device via a second TWI bus; receive a first arbitration request via an out of band arbitration process from a third device; provide first control information via an in band arbitration process to the first device via the first TWI bus; receive second data from an isolation device via a third TWI bus; provide the second data to the second device via the second TWI bus; receive a second arbitration request via the in band arbitration process from the first device via the first TWI bus; and provide second control information via the out of band arbitration process to the third device.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Brian Daniel Kennedy, Nicholas Anthony Esposito, Maxwell Brooks Rapier
  • Patent number: 11507450
    Abstract: A computing device including: more than two Universal Serial Bus (USB) ports configured to be connected respectively to more than two mobile devices simultaneously; at least one processor coupled to the USB ports; and a memory storing instructions configured to instruct the at least one processor to reprogram, through the more than two USB ports, the more than two mobile devices simultaneously.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 22, 2022
    Assignee: Future Dial, Inc.
    Inventor: George Huang
  • Patent number: 11507414
    Abstract: A circuit for fast interrupt handling is disclosed. An apparatus includes a processor circuit having an execution pipeline and a table configured to store a plurality of pointers that correspond to interrupt routines stored in a memory circuit. The apparatus further includes an interrupt redirect circuit configured to receive a plurality of interrupt requests. The interrupt redirect circuit may select a first interrupt request among a plurality of interrupt requests of a first type. The interrupt redirect circuit retrieves a pointer from the table using information associated with the request. Using the pointer, the execution pipeline retrieves first program instruction from the memory circuit to execute a particular interrupt routine.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 22, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert T. Golla, Thomas Martin Wicki, Jama Ismail Barreh
  • Patent number: 11507323
    Abstract: Embodiments of the present disclosure relate to a memory device and an operating method thereof. According to the embodiments of the present disclosure, when a read failure for a first read command among a plurality of read commands inputted from a memory controller occurs, the memory device may execute in an overlapping manner, a read retry operation for the first read command and a read operation for a second read command among the plurality of read commands.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Chan Young Oh, Na Ra Shin
  • Patent number: 11496418
    Abstract: An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: November 8, 2022
    Assignee: Xilinx, Inc.
    Inventors: Zachary Blair, Pongstorn Maidee, Alireza S. Kaviani
  • Patent number: 11486729
    Abstract: The present invention relates to a data concentration unit and an operating method thereof. To this end, the data concentration unit of the present invention includes: a substrate; and a data communication unit for collecting meter reading data of a plurality of customers through communications with power metering communication modems respectively connected to watt-hour meters provided for the plurality of customers, wherein the data communication unit includes at least one wired communication module for performing wired communication with power metering wired communication modems, and at least one wireless communication module for performing wireless communication with power metering wireless communication modems, and the wired communication module and the wireless communication module are inserted and provided into the substrate.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 1, 2022
    Assignee: KOREA ELECTRIC POWER CORPORATION
    Inventors: Kang-Se Lee, Hyeong-Ju Lee, Jae-Wan Kim
  • Patent number: 11487469
    Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 1, 2022
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Yi Li, Gang Shan, Howard Chonghe Yang
  • Patent number: 11481343
    Abstract: A system includes multiple memory-compute nodes coupled to one another over a scale fabric, where each memory-compute node includes a hybrid threading processor; a memory controller; a fabric interface; and a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller, wherein the fabric interface supports a first virtual channel (VC0), and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to the scale fabric.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 11481350
    Abstract: Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer (“SerDes”) block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 25, 2022
    Assignee: Innovium, Inc.
    Inventors: Srinivas Gangam, Ajit Kumar Jain, Anurag Kumar Jain, Avinash Gyanendra Mani, Mohammad Kamel Issa
  • Patent number: 11483198
    Abstract: A meter communication interface device includes a radio frequency (RF) communication unit, multiple different types of communication ports, and a controller. The RF communication unit receives, via RF signaling, at least one of first commands, instructions or data destined for a first meter encoder, meter, or meter interface unit (MIU). The controller selects a first communication port from the multiple different types of communication ports, and sends, via the selected first communication port using a first communication mechanism, the at least one of first commands, instructions or data to the first meter encoder, meter, or MIU.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 25, 2022
    Assignee: Neptune Technology Group Inc.
    Inventor: Brandon Segrest
  • Patent number: 11474959
    Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: October 18, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Craig E. Hampel
  • Patent number: 11461106
    Abstract: A method includes executing software code comprising a plurality of execute packets; responsive to an execute packet of the software code being executed by a data processor core, advancing a value of a test counter register; and responsive to the value of the test counter register being equal to a terminal value, triggering an event to be handled by the software code.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: October 4, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Timothy D. Anderson
  • Patent number: 11461868
    Abstract: An image processing device includes a main SoC, an performance-enhancing SoC, and an external circuit set outside any of the two SoCs. The main SoC includes: a data splitter dividing input image data into a first input part and a second input part; a first image processing circuit processing the first input part to generate a first output part; and a transmitter outputting the second input part to the performance-enhancing SoC via the external circuit. The performance-enhancing SoC includes: a receiver receiving the second input part via the external circuit; and a second image processing circuit processing the second input part to generate a second output part. The combination of the two output parts jointly determines a data amount per unit of time which exceeds the processing capability of any of the two image processing circuits. Each of the two SoCs includes a CPU, and the two CPUs cooperate, too.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: October 4, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hsu-Jung Tung
  • Patent number: 11444829
    Abstract: In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 11444939
    Abstract: An authentication control device includes: an acquisition unit configured to acquire predetermined identification information regarding an on-vehicle device to be newly added to an on-vehicle network; and a determination unit configured to determine which of a plurality of types of authentication procedures is to be applied as an authentication process for the on-vehicle device, on the basis of the identification information acquired by the acquisition unit.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 13, 2022
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Akihiro Ogawa, Hirofumi Urayama, Takeshi Hagihara, Yasuhiro Yabuuchi
  • Patent number: 11436104
    Abstract: A set of restore jobs are created to restore a backup. The backup may be maintained across a set of storage devices connected to a backup server. The set of storage devices have different levels of performance and each restore job is responsible for restoring from a respective storage device. Information describing arrangements of processors and memory units is reviewed to create a set of heterogeneous domains, each domain including a processor and memory unit. Performance characteristics, including latency and bandwidth measurements, of the heterogeneous domains are examined. The heterogeneous domains are ranked based on their performance characteristics. The restore jobs are assigned to the heterogeneous domains by successively matching a restore job associated with a storage device having a lowest level of performance relative to other unmatched storage devices with a heterogeneous domain having a highest level of performance relative to other unmatched heterogeneous domains.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Parmeshwr Prasad, Rahul Vishwakarma, Bing Liu
  • Patent number: 11416370
    Abstract: An apparatus to collect firmware measurement data at a computing system is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent, verification logic to generate measurement data by verifying the integrity of the firmware and a register to store the measurement data, and a processor to execute an instruction to collect firmware measurement data from each of the plurality of agents.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Prashant Dewan, Uttam Sengupta, Aditya Katragada
  • Patent number: 11416422
    Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Samuel E. Bradshaw, Shivam Swami, Sean S. Eilert, Justin M. Eno, Ameen D. Akel
  • Patent number: 11403068
    Abstract: Apparatus and associated methods relate to determining a natural exponent from a digital word input by splitting the digital word, and retrieving a precalculated and predetermined value from a data store at an address defined by the first word. In an illustrative example, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by the second word. The hyperbolic sum may be scaled, and summed with the multiplication result to generate a scaled exponential value. The scaled exponential value may be scaled to produce an exponential value representing eX. In various examples, the digital word input may be in a fixed point or a floating point format, or converted therebetween. In various embodiments, the data store may be a lookup table. Various examples may provide a compact and versatile architecture for determining a natural exponent with minimized hardware resources.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 2, 2022
    Assignee: XILINX, INC.
    Inventor: Stefano Cappello
  • Patent number: 11397693
    Abstract: The invention relates to a peripheral device for communicating with a host and for controlling a controlled device, to a system including such peripheral device and at least the controlled device and to a corresponding method including a communication and a controlling. In order to allow for a possibility for upgrading controlled devices with further functionality during their service life at low initial costs or efforts on the side of the controlled devices, it is provided for an interconnection between a portion of the system using a complex standard and another portion of the system not using such standard by means of the peripheral device having a dual purpose, as a peripheral device to the standard compliant host and as a controlling device to the controlled device. In both cases, however, power is provided to the peripheral device from either the host or from the controlled device.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 26, 2022
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Matthias Wendt, Johan-Paul Marie Gerard Linnartz, Wolfgang Otto Budde, Anteneh Alemu Abbo, Georg Sauerlander, Reinhold Elferich
  • Patent number: 11386520
    Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: July 12, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Mantor, Jeffrey T. Brady, Angel E. Socarras
  • Patent number: 11374788
    Abstract: A network system includes: a first master device configured to carry out, in every cycle, (i) a process of receiving data from a first slave device, (ii) a process of carrying out, in accordance with pre-allocation, a part of a first process with respect to the data, (iii) a process of transmitting data corresponding to a remainder of the first process to an outside entity in accordance with the pre-allocation and receiving a result corresponding the remainder of the first process, and (iv) a process of transmitting, to the first slave device, a result corresponding to the first process; and at least one second master device configured to transmit, to the first master device before a period allocated to the first process within the cycle ends, the result corresponding to the remainder of the first process with respect to the data received from the first master device.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: June 28, 2022
    Assignee: OMRON CORPORATION
    Inventor: Yutaka Tahara
  • Patent number: 11366446
    Abstract: A plurality of sequentially consecutive sections of a linear drive are each controlled case by a respective control device that is assigned to a respective section of the plurality of sequentially consecutive sections, where converters that are controlled by the respective control device each individually apply current to a subsection of the respective section, and collectively to the respective section, control devices each specify new desired values to the converters they control, the respective control device controls each respective convertor of a plurality of converters, and where the control devices communicate, via respective peer-to-peer interfaces having real-time capability, with a number of other control devices that control sections.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 21, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventors: Juergen Hessenauer, Michael Jaentsch, Carsten Spindler
  • Patent number: 11354263
    Abstract: A bus system comprises a master, a first slave, a second slave, and a bus. The master is configured to be able to issue a second request to the second slave after issuing a first request to the first slave and before receiving a response to the first request. The bus comprises: a determination unit configured to, upon receiving the second request, determine whether to permit a transfer of the second request to the second slave; and a suspending unit configured to suspend the transfer of the second request to the second slave while it is determined by the determination unit that the transfer is not permitted. The determination unit determines whether or not the transfer is permitted based on a notification from the first slave regarding processing of the first request.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 7, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Daisuke Shiraishi, Wataru Ochiai
  • Patent number: 11347671
    Abstract: A method for protecting a system from a malicious USB device. The method includes one or more computer processors interrupting a universal serial bus (USB) enumeration process corresponding to a first USB device operatively couple to a system. The method further includes determining whether the first USB device is a human interface device (HID) based on a set of descriptor values corresponding to the first USB device. The method further includes responding to determining that that first USB device is a HID by generating a validation challenge. The method further includes presenting the validation challenge to a user of the system. The method further includes responding to determining that the user fulfils one or more actions of the validation challenge by resuming the USB enumeration process corresponding to the first USB device.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: May 31, 2022
    Assignee: KYNDRYL, INC.
    Inventors: Franz Friedrich Liebinger Portela, Cesar Augusto Rodriguez Bravo, Kevin Jimenez Mendez
  • Patent number: 11347672
    Abstract: A storage apparatus in which a controller reads out a port status of a switch in a short period of time is disclosed. The storage apparatus includes a switch and a plurality of storage controllers configured to communicate with each other through the switch. The switch includes a switch processor, a plurality of data ports, a switch integrated circuit, a memory, and a management interface. One of the plurality of data ports and a management port of the management interface are connected to each other. The switch processor stores a status of the plurality of data ports acquired from the switch integrated circuit into the memory. The plurality of storage controllers access the management interface through the plurality of data ports and the management port and receive the statuses of the plurality of data ports stored in the memory from the management interface.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 31, 2022
    Assignee: HITACHI, LTD.
    Inventors: Katsuya Tanaka, Hirotoshi Akaike
  • Patent number: 11341603
    Abstract: An image processing electronic device includes a pipeline configured to process frames of image data; an internal memory coupled to the pipeline, wherein a set of descriptors arranged according to an order is stored in the internal memory, each descriptor of the set of descriptors is associated with a corresponding function to be activated by the pipeline on at least one frame of image data; a controller configured to read each descriptor of the set of descriptors sequentially and cyclically according to the order at a rate of at least one descriptor per one frame of image data and store information corresponding to each read descriptor, wherein the pipeline is configured to activate on each frame of image data, the function associated with each read descriptor based on the stored information.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 24, 2022
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christophe Pinatel, Serge Mazer, Olivier Ferrand
  • Patent number: 11334514
    Abstract: A circuit for a bus system is provided. The circuit includes: an ascertainment circuit, which is configured to ascertain a first state in which an absolute difference of a voltage between two bus-side terminals is above a threshold value, to ascertain a second state in which the absolute value of the voltage between the two bus-side terminals is below the threshold value, to ascertain a bit boundary as a function of a number of state transitions between the first and second state, and to ascertain at least one time window, the start of which is situated before the bit boundary and the end of which is situated after the bit boundary; and a suppression circuit, which is configured to be activated when a state transition from the first state into the second state occurs within the ascertained time window.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 17, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Arthur Mutter, Steffen Walker
  • Patent number: 11327913
    Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 10, 2022
    Assignee: Astera Labs, Inc.
    Inventors: Casey Morrison, Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Vivek Trivedi
  • Patent number: 11326958
    Abstract: An electric machine includes a protective isolation module which is accommodated in a machine housing. The protective isolation module includes an input interface which is electrically connected to a temperature sensor to receive an electrical sensor signal generated by the temperature sensor as a measure of a machine temperature of the electric machine, an output interface which is galvanically isolated from the input interface to realize a secure electrical protective isolation of the output interface from a voltage flashover of a machine winding in the sensor power circuit, and a supply interface, via which the protective isolation module can be supplied with electrical energy from a power supply for the electric machine. An electronic control system receives an output signal that replicates the sensor signal via the output interface for evaluation in the electronic control system.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 10, 2022
    Assignee: WEISS SPINDELTECHNOLOGIE GMBH
    Inventors: Norbert Medla, Felix Butz, Michael Wöhning
  • Patent number: 11321266
    Abstract: The present invention discloses a dual-mode USB device, which includes a USB2.0 controller, a dual-mode USB2.0 interface module and a USB interface. The dual-mode USB device alternatively works in a USB2.0 standard mode or a USB2.0 extended mode. In the USB2.0 standard mode, DP and DM signals of the USB2.0 interface are connected to a remote USB interface by DC coupling, and is compatible with remote devices using USB2.0 standard signals and protocols; in the USB2.0 extended mode, DP and DM signals of the USB2.0 interface are connected to the remote USB interface by AC coupling, which is compatible with remote devices supporting the USB2.0 extended mode.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 3, 2022
    Assignee: NOREL SYSTEMS LIMITED
    Inventors: Yuanlong Wang, Miao Chen
  • Patent number: 11323519
    Abstract: An Internet of Things (IoT) system may include a publisher computer connected to IoT devices. The publisher computer may execute operations to provide data for the IoT devices to a remote computer which may be included in a cloud infrastructure. The publisher computer can receive data from the IoT devices, convert the data to a publisher-subscriber format that conforms to a predetermined specification, and transmit the data to the cloud infrastructure or other remote computers.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 3, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Gary Sherman, Hans Gschoßmann, Erich Barnstedt, Martin Regen, Marc Schier, Daniele Colonna
  • Patent number: 11314301
    Abstract: Methods, systems, and devices for power management of a memory device are described. An apparatus may include a substrate and an input/output (I/O) interface and memory device coupled with the substrate. The I/O interface may communicate with a host device and the memory device may store data associated with the host device. The apparatus may include a power management component for providing one or more supply voltages to the memory device. The power management component may receive input voltages associated with the substrate and provide the supply voltages to the memory device based on the input voltages. The power management component may include a first portion integrated with the memory device and a second portion coupled with the substrate. The first portion may include control circuitry for the power management component and the second portion may include passive components for the power management component.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technolgoy, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11284340
    Abstract: An electronic device and related control method are provided. The electronic device includes a first connection interface, configured to be electrically connected to a first host system through a first cable, and a second connection interface, configured to be electrically connected to a second host system through a second cable. The electronic device further includes a transmission control device having a first communication channel and a second communication channel, wherein the transmission control device provides operation functions for at least one of the first host system and the second host system according to a connection state. The electronic device further includes a data access device configured to receive data transmitted by the at least one host system, and a channel-detecting device, detecting the impedance information between one or both of the first connection interface and the second connection interface and the at least one host system.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 22, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Liang-Hsuan Lu
  • Patent number: 11271771
    Abstract: A controller area network bus based security communications system includes a gateway electronic control unit (ECU) and at least one control area network (CAN) bus ECU. The gateway ECU generates a random number, and sends the random number to the at least one CAN bus ECU. A first CAN bus ECU obtains the random number sent by the gateway ECU, and generates a first information authentication code based on a key of a first CAN identifier, the random number sent by the gateway ECU, a count value of the first CAN identifier, and data of a first CAN packet.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 8, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hsiao-Ying Lin, Zhuo Wei, Qingdi Sha, Kang Tang
  • Patent number: 11263158
    Abstract: Methods and apparatuses for a programmable IO device interface are provided. The apparatus may comprise: a first memory unit having a plurality of programs stored thereon, the plurality of programs are associated with a plurality of actions comprising updating memory based data structure, inserting a DMA command or initiating an event; a second memory unit for receiving and storing a table result, and the table result is provided by a table engine configured to perform packet match operations on (i) a packet header vector contained in a header portion and (ii) data stored in a programmable match table; and circuitry for executing a program selected from the plurality of programs in response to the table result and an address received by the apparatus, and the program is executed until completion and the program is associated with the programmable match table.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 1, 2022
    Assignee: PENSANDO SYSTEMS INC.
    Inventors: Michael Brian Galles, J. Bradley Smith, Hemant Vinchure
  • Patent number: 11249732
    Abstract: A GUI controller design support device can support the programming of a controller device that is capable of changing control and/or graphic representation flexibly and in real time. The GUI controller design support device supports the designing of a GUI controller that is displayed on a touch-sensitive panel display of an input device and that receives an operation input for operating a target device. The GUI controller design support device is provided with: a GUI controller editing unit for editing a controller set, the controller set being configured by a plurality of controller parts and defining the GUI controller; and a user program editing unit for editing a user program, the user program defining control of the target device in response to the operation input to the GUI controller.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 15, 2022
    Assignee: LC-STUDIO CORPORATION
    Inventor: Kunihito Ishisako
  • Patent number: 11237789
    Abstract: Methods and apparatuses are provided for displaying a screen in an electronic device. A message application is executed. An execution screen of the message application and a keyboard are displayed through a touch screen display of the electronic device while the message application is executed. A layer of the execution screen is overlaid with a layer of the keyboard. Based on a touch input on an object related to the keyboard, data related to the keyboard is transmitted to an external electronic device through a communication interface of the electronic device such that the external electronic device, based on the data related to the keyboard, displays the keyboard through a display of the second external electronic device. The execution screen is displayed through the touch screen display. The keyboard which has been displayed disappears from the touch screen display.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 1, 2022
    Inventors: Yong-Soo Jeong, Jin Park, Min-Ji Kim
  • Patent number: 11226215
    Abstract: A modular field device kit with interchangeable components allowing for customization and a method of assembly of a field device using such kit.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 18, 2022
    Assignee: VEGA GRIESHABER KG
    Inventors: Volker Allgaier, Christian Sum
  • Patent number: 11216402
    Abstract: The storage comprises a first bridge, a second bridge that can be connected to the first bridge, a first storage device that can be connected to the first bridge, and second and third storage devices that can be connected to the second bridge. If a command that has been received from a main controller is a command not corresponding to the first storage device and an access destination of the main controller is the second bridge, a controller transmits a command corresponding to the received command to the second bridge. In contrast, if the command that has been received from the main controller is a command corresponding to the first storage device, the controller transmits the command corresponding to the received command to the second bridge or the first storage device.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 4, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Masahiro Takizawa
  • Patent number: 11210216
    Abstract: Techniques to facilitate a hardware based table look of a table maintained in or more types of memories or memory domains include examples of receiving a search request forwarded from a queue management device. Examples also include implementing table lookups to obtain a result and sending the result to an output queue of the queue management device for the queue management device to forward the result to a requestor of the search request.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Alexander Bachmutsky, Raghu Kondapalli, Francesc Guim Bernat
  • Patent number: 11202378
    Abstract: A computing and storage system includes a housing having power and cooling facility and a plurality of slots, each slot having interface connection. An interconnecting board is coupled to the interface connection of the plurality of slots. A plurality of baseboards are inserted, each in one of the slots wherein a board interface mates with the interface connection. All of the baseboards have the same form factor and the same board interface and each of the baseboards has a plurality of electronic devices, such that all of the electronic devices mounted onto one of the baseboards are the same. Using the interconnecting board, the various baseboards can be interconnected to form a computing and/or storage machine of different operational characteristics as required by a given task. In addition, the inter connection board is managed to adjust the networking resource allocations for different traffic characteristics and workload requirements.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 14, 2021
    Assignee: BAIDU USA LLC
    Inventor: Tianyi Gao
  • Patent number: 11184190
    Abstract: An IC communication device according to an embodiment of the present invention includes: a plurality of sensing ICs including a first sensing IC to an N-th sensing IC arranged to be adjacent (N is an integer equal to or greater than 2); and a controller connected to the first sensing IC, wherein when the controller in a sleep mode receives a wakeup signal and transmits the wakeup signal to the first sensing IC, the wakeup signal is transmitted in two directions to two sensing ICs, from the first sensing IC to the N-th sensing IC, arranged to be adjacent.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 23, 2021
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventors: Yeong-Geun Yeo, Seulkirom Kim, Jae-Min Park, Jae-Seong Park, Sang-Ho Lee, Jong-Won Choi
  • Patent number: 11163444
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Charles W. Gainey, Jr., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • Patent number: 11150842
    Abstract: A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sesibhushana Rao Bommana, Mukesh Panda
  • Patent number: 11137995
    Abstract: Embodiments of the invention provide a computer-implemented method for updating firmware of a Universal Serial Bus (USB) device. The USB device is configured to execute one or more applications of the USB device in a normal mode of operation of the USB device. The USB device includes a device descriptor indicative of one or more configuration descriptors, wherein a configuration descriptor is indicative of endpoints for data and command exchange. The device descriptor can be modified by adding a predefined bootloader configuration descriptor to the configurations descriptors for updating the firmware.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Andreas Christian Doering
  • Patent number: 11106611
    Abstract: Systems, methods, and devices are provided for migrating field device data signals from a first control system to a second control system using an interface card. An interface card can be configured to couple to a first and second terminal block cable assembly, respectively associated with a first and second control system. The interface card and system herein can maintain a field device data channel assignment configuration when migrating control and data I/O of the field device from the first control system to the second control system.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Baker Hughes Oilfield Operations LLC
    Inventor: Chad Michael Shryock
  • Patent number: 11100035
    Abstract: A hot-pluggable barrel jack connection system includes a male barrel jack connector including a tip connector at a distal end of the male barrel jack connector and configured to conduct a ground reference voltage, a first ring connector electrically isolated from the tip connector by a first insulator, and configured to conduct a first data signal, and a sleeve connector adjacent to a base of the male barrel jack connector electrically isolated from the first ring connector, and configured to conduct a power signal.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 24, 2021
    Assignee: ERP POWER, LLC
    Inventor: James H. Mohan
  • Patent number: 11073881
    Abstract: To make is possible to use a peripheral device that consumes a current exceeding the rated current allocated to each port in a simpler system configuration in an electronic apparatus having a plurality of external interfaces.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: July 27, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Motoki Koshigaya