Abstract: A method for networking a first time-sensitive field bus with a second time-sensitive field bus, the first time-sensitive field bus comprising a first subscriber device and having a first dedicated time domain, and the second time-sensitive field bus comprising a second subscriber device and having a second dedicated time domain. The first time domain and the second time domain being frequency-synchronized. The first and second field buses being connected to each other via a gateway. The method includes: storing a first subscriber device identifier in the memory of the gateway; storing a second subscriber device identifier in the memory of the gateway; determining a first cycle duration of the first field bus and a second cycle duration of the second field bus by the gateway at a reference time; and determining a time offset between the first and second time domain by the gateway at the reference time.

Abstract: This document describes systems and techniques for modulating credit allocations in memory subsystems. The described systems and techniques can provide a feedback mechanism to a credit controller to improve the bandwidth at a memory interface. The memory controller monitors statistics associated with transaction requests served to one or more random access memories (RAMs) of the memory subsystem. The memory controller can then provide suggestions to the credit controller or to the one or more clients to modulate the number of credits allocated to one or more clients. In this way, the described systems and techniques can improve the efficiency of the memory controller in managing the transaction requests and the bandwidth at the memory interface.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes a D2D interface of a first type for coupling to a host IC chip via multiple lanes. The D2D interface includes multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes. A memory port includes a memory physical interface of a first memory type for accessing memory storage of the first memory type. The memory physical interface of the first memory type includes a second set of signal path resources corresponding to multiple memory channels of the first memory type. Mapping circuitry maps the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the first signal path resources for an integer number of the multiple unit interface modules.

Abstract: A semiconductor device includes terminals connectable to a host, first and second bridge chips connected to the terminals, first chips connected to the first bridge chip, and second chips connected to the second bridge chip. The terminals includes a first terminal through which a first signal designating a bridge chip is transmitted. The first bridge chip is configured to enable signal transmission to at least one of the first chips when the first signal designates the first bridge chip, and disable the signal transmission to the first chips when the first signal does not designate the first bridge chip. The second bridge chip is configured to enable signal transmission to at least one of the second chips when the first signal designates the second bridge chip, and disable the signal transmission to the second chips when the first signal does not designate the second bridge chip.

Abstract: A method for operating a memory device includes receiving an input that includes a command signal, an address signal, and a data signal, transmitting the command signal or the address signal to a low speed buffer, and transmitting the data signal to a high speed buffer.

Abstract: Detailed herein are embodiments which allow for integrity protected access control to provide defense against deterministic software attacks. Software attacks such as rowhammer attacks which target the TD bit itself are defended against using cryptographic integrity which the data itself is protected by the TD-bit alone. As such, software is reduced to performing only non-deterministic attacks (e.g., random corruption), but all the deterministic attacks are defended against. Additionally, integrity-protected access control bits are protected against simple hardware attacks where the adversary with physical access to the machine can flip TD bits to get ciphertext access in software which can break confidentiality.

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

Abstract: A signal switching method applicable to a first electronic device includes: receiving a voltage of a second electronic device through a power supply contact pin of the first electronic device; comparing the voltage with a threshold; when the voltage is greater than the threshold, connecting a first bus of the first electronic device to at least one signal contact pin, and disconnecting a second bus of the first electronic device from the at least one signal contact pin; and when the voltage is not greater than the threshold, connecting the second bus to the at least one signal pin, and disconnecting the first bus from the at least one signal contact pin.

Abstract: An information recording method, apparatus, and device, and a readable storage medium are provided. The method includes: when a server is started, determining a ring buffer in a Double Data Rate (DDR) of a Field-Programmable Gate Array (FPGA) acceleration card based on an OpenPower platform; determining a start address and an end address of the ring buffer and configuring the start address and the end address to the FPGA acceleration card; and during a running process of the server, recording preset debugging information to the ring buffer in real time, so as to perform fault location according to data in the ring buffer after a fault occurs in the server. According to the present application, during a running process of a server, preset debugging information is recorded using a DDR of an FPGA acceleration card.

Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

Abstract: An I/O module comprising an input interface, designed for connection to at least one sensor for input of an input signal, and/or an output interface, designed for connection to at least one actuator for output of an output signal, with a data interface for connection to a sub-bus for the transmission of an input datum and/or output datum, and with a control unit connected to the data interface and connected to the input interface and/or the output interface, wherein the control unit is set up to process the input datum and/or output datum and exchange it via the data interface, wherein the control unit is further set up to store a predetermined input value and/or output value which replaces the input datum and/or output datum.

Abstract: An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).

Abstract: An apparatus for generating FPD-link IV signals in automobiles. The apparatus includes a USB to I2C converter allowing USB interfaced commands and Ethernet interfaced commands to configure and update a single board computer, an FPD-link IV Serializer and the single board computer that produce a video signal to FPD-link IV outputs. The single board computer stores video timing parameters (EDID) for the Device Under Test as well.

Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.

Abstract: Asset tracking systems and methods include one or more tracking devices that pair with one or more hub devices to transmit sensor data from a tracking device only to a paired hub device with a hub device state quality rating, and from the paired hub device to a network server, thereby reducing redundant communications and communication network usage.

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

Abstract: [Problem] Learning of object operation skills robust against variation of conditions is implemented. [Solution] A behavior estimation apparatus 100 includes a collection unit 200 configured to collect skill data obtained when a slave robot is operated under a plurality of different conditions by using a bilateral system capable of operating the slave robot via a master robot through bidirectional control between the master robot and the slave robot. The behavior estimation apparatus 100 further includes a behavior estimation device 300 configured to estimate a command value for causing the slave robot 520 to automatically behave, based on the skill data collected by the collection unit 200 and a response output from the slave robot 520.

Abstract: A method for transmitting data between a peripheral device and a data acquisition unit, the data acquisition unit having a configurable communication interface via which the data are transmitted according to one of a number of defined communication protocols, includes: carrying out a communication protocol analysis by the peripheral device upon connection to a power supply; and carrying out an adaptation of the configurable communication interface of the peripheral device after detection of a communication protocol, providing a detected communication protocol, used by the data acquisition unit in order to carry out data exchange according to the detected communication protocol.

Abstract: An integrated circuit (IC) with reconstituted die interposer for improved connectivity has at least one device or component mounted on an exterior upper surface that couples to a die in an interposer layer within the package. The interposer layer may have interconnect structures, where a first interconnect structure has vias of a first pitch and a second interconnect structure has vias of a second pitch greater than the first pitch. In this manner, the interposer layer acts as a device that can allow conductive coupling for other devices with those pitches to support interconnections between those devices and other devices within the interposer layer.

Abstract: A method includes assessing an input in a buffer against a rule in a first node of a rule tree to determine that an action should be performed and updating the buffer with results of performing the action. The method also includes inserting an indication of the input, the rule, and the results of performing the action into a tracker log and passing the updated buffer to a second node in the rule tree in response to determining that the first node points to the second node.

Abstract: Systems and methods for arbitrating access of a shared resource are disclosed. Data is received from various sources and stored in various queues. A first data structure is generated based on the stored data. The first data structure may be associated with two dimensions (e.g. a first dimension associated with sources and a second dimension associated with destinations). A second data structure is generated based on the first data structure. The second data structure may be associated with one dimension. The one dimension may include the second dimension. A first arbitration is performed based on the second data structure for selecting a destination. A second arbitration is performed based on the first data structure and the selected destination for selecting a source. Data stored in one of the queues associated with the selected source and the selected destination is retrieved, and the retrieved data is provided to the shared resource.

Abstract: A docking station includes a network interface controller (NIC), a dock-side controller and a dock-side connector interface. The NIC is configured to transmit one or more management component transport protocol (MCTP) packets via a system management bus (SMbus). The dock-side controller is electrically coupled to the SMbus, and configured to encode the one or more MCTP packets to one or more vendor specific protocol (VSP) packets. The dock-side connector interface is electrically coupled to the dock-side controller, and configured to transmit the one or more VSP packets to an electrical device to control a basic input output system (BIOS) of the electrical device on the condition that the electrical device is connected to the docking station via the dock-side connector interface.

Abstract: Disclosed herein are devices and systems that embed a physical layer (e.g., an M-PHY) on a configurable integrated circuit (e.g., an FPGA) and include glue hardware that provides AC coupling between a high-speed serial communication device (e.g., a MIPI device) and the configurable integrated circuit. The glue hardware provides AC coupling using only resistors, capacitors, and inductors. The configurable integrated circuit includes a logic block that manages the operation to provide the desired PHY connectivity. Because the disclosed devices and systems use AC coupling, the signaling drive and receive paths are controlled based on the received signal frequency and not based on the mode (e.g., LS mode or HS mode). Specifically, the line state of the MIPI device is inferred from observation of signal transitions as opposed to direct detection of DC signal levels.

Abstract: An exemplary computer console can generate one or more video streams having image data relating to an image or a series of images, also referred to as video, to be presented by an electronic display device. The exemplary computer console can provide the one or more video streams to the electronic display device over one or more transport streams. The exemplary computer console can effectively throttle a video stream bitrate of the one or more video streams to be less than of the standard defined transport stream bitrate of the one or more transport streams to allow the transport of the one or more video streams over the one or more transport streams.

Abstract: Embodiments include a device comprising an interface module for interfacing with proprietary legacy systems. The interface module comprises a data interface for interfacing with a processing component of the legacy system, where the processing component uses a proprietary protocol for processing data of the legacy system. The interface module includes a protocol module that comprises a protocol corresponding to the proprietary protocol of the legacy system, and the interface module uses the protocol to exchange data with the processing component. The interface module includes a communication device that communicates with a remote system via a wireless channel. The interface module controls communications that include passing commands from the remote system to the legacy system, and passing event data of the legacy system to the remote system.

Abstract: A system for controlling data communications, comprising an enclosure management processor configured to generate a peripheral component interconnect express reset command and a chip reset command. A re-timer configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command. The communications port configured to reset in response to a control signal from the re-timer.

Abstract: The disclosure relates to a method for transmitting at least one control command to at least one actuator, comprising the following steps: a) monitoring a communication bus; b) detecting an event, for example bus inactivity, that lasts longer than a predefined time interval; c) dividing the communication bus into a first bus segment and a second bus segment, wherein the actuator is part of the second bus segment; d) transmitting the at least one control command to the at least one actuator on the second bus segment.

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

Abstract: An interface for an I3C slave. The interface allows I3C slaves to also be connected to a conventional I2C bus that includes an I2C master. For this purpose, an additional adaptation device is provided that adapts the signals of the I2C bus for an I3C slave.

Abstract: The approach relates to a modular computer architecture of a cockpit and infotainment system for a vehicle that includes an I/O module with an I/O computing node (2.0) with at least one data memory, the I/O computing node being designed for processing audio data and as a host computer for performing host functions with ASIL safety requirements. The I/O module also includes a tuner with associated antenna interface, and at least one interface of a vehicle bus system. The modular computer architecture further includes at least one computing module with a computing node with at least one data memory for performing cockpit and infotainment functions, and at least one display interface.

Abstract: Techniques for disk failure control involve determining the number of failed disks in a Redundant Array of Independent Disks (RAID). The techniques further involve comparing the number of failed disks with a predetermined threshold; and in accordance with a determination that the number of failed disks exceeds the predetermined threshold, setting at least one non-failing disk in the RAID into a protection mode to prevent the at least one non-failing disk from being disconnected. Such techniques facilitate prevention of the user data loss in the RAID.

Abstract: A transaction controller orders transactions between a master device and a slave device, where the transactions may be received out-of-order. First and second transactions have respective first and second sets of data packets. The transaction controller includes a transaction table, a first ordering counter, and a first sequence counter having first and second values when the first and second transactions are initiated. The first and second values are stored in the transaction table based on first and second transaction identifiers (TIDs) that are associated with the first and second transactions. The transaction controller determines, based on the second value, the second TID, and a current value of the first ordering counter, whether the first and second sets of data packets were received out-of-order. Based on the determination, the second set of data packets is transmitted to the master device after the first set of data packets.

Abstract: A host-to-host chip includes: first and second ports coupled to first and second hosts respectively; and a host-to-host control circuit coupled to the first port and the second port. When the host-to-host chip is coupled to the second host, the host-to-host control circuit identifies whether the second host is an i-Phone or an Android smartphone. If the host-to-host control circuit identifies that the second host is an i-Phone smartphone, in response to a command from the host-to-host control circuit, the second host switches to host role from device role, and the host-to-host control circuit controls whether data is transmitted between the first host and the second host via a DMA path. If the host-to-host control circuit identifies that the second host is an Android smartphone, the host-to-host control circuit determines that data is transmitted between the first host and the second host in a pass-through mode.

Abstract: A storage device includes a storage and a controller. The controller can control data write to the storage and data read from the storage. The controller includes a first processor, a second processor, a first bus, a memory access control device, and a second bus. The memory access control device can manage a memory access control information table. The memory access control information table stores access control information indicating a range of each of areas of the memory and an identifier associated with each area. The memory access control device can compare the identifier output to the first bus with the identifier in the memory access control information table, and determine whether to allow the access to the memory requested by the second processor.

Abstract: A system on a chip (SoC) can be configured to operate in one of a plurality of modes. In a first mode, the SoC can be operated as a network compute subsystem to provide networking services only. In a second mode, the SoC can be operated as a server compute subsystem to provide compute services only. In a third mode, the SoC can be operated as a network compute subsystem and the server compute subsystem to provide both networking and compute services concurrently.

Abstract: A controller suitable for controlling a semiconductor memory device includes a pattern determination circuit configured to determine a pattern information of data corresponding to a command received from a host. The controller includes a map cache management circuit configured to determine a target map table entry among map table entries of a map table based on the pattern information, and store, when the target map table entry does not exist in a map cache which stores some among the map table entries, the target map table entry in the map cache. The controller includes an entry eviction circuit configured to evict some among map table entries stored in the map cache, when storing the target map table entry in the map cache.

Abstract: A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.

Abstract: A CPU of an MFP receives battery information from a first external device via a first interface, determines whether a total amount of electric power supplied to a plurality of interfaces from a power supply is maintained, and reduces an amount of the electric power supplied to the first external device via the first interface in a case where determining that the first external device has no battery based on the battery information in response to determining that the total amount of the electric power supplied to the plurality of the interfaces from the power supply is not maintained.

Abstract: Protocols for transmitting a data flow transiting between a host computer and a remote client use the bandwidth of a computer network. The data includes at least display and sound data generated by a user session running on the host computer, and control data generated by at least one remote system I/O device. The transmission protocol includes a plurality of data flow reliability treatments to address transmission failures, the reliability treatments applying to the display, sound and control data respectively being different from each other.

Abstract: A rack-mountable data storage system includes: a chassis including one or more switchboards; a midplane interfacing with the one or more switchboards; and one or more data storage devices removably coupled to the midplane using a connector. At least one data storage device of the one or more data storage devices include a logic device to interface with the midplane. The logic device provides a device-specific interface of a corresponding data storage device with the midplane. The at least one data storage device is configured using the logic device according to a first protocol based on a signal on a pin of the connector, and the at least one data storage device is reconfigurable according to a second protocol based on a change of the signal on the pin of the connector using the logic device.

Abstract: A processor/endpoint communication coupling configuration system includes a plurality of processing subsystems coupled to a multi-endpoint adapter device by a plurality of communication couplings included on at least one hardware subsystem. A communication coupling configuration engine identifies each at least one hardware subsystem, determines at least one communication coupling configuration capability of the plurality of communication couplings, and determines at least one first multi-endpoint adapter device capability of the multi-endpoint adapter device.

Abstract: A signal transmission method and a circuit structure for heterogeneous platforms are provided. The method includes: adjusting signal transmission bandwidths between a first platform and a bridge circuit and between the bridge circuit and a second platform according to signal transmission speeds between the first platform and the bridge circuit and between the bridge circuit and the second platform; transmitting a command signal from the first platform to the bridge circuit and saving the command signal at a buffer of the bridge circuit; reading the command signal at the buffer of the bridge circuit by the second platform; transmitting data to the buffer of the bridge according to the command signal by the second platform; acquiring the data at the buffer of the bridge by the first platform.

Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: The storage interface includes a first programmable input/output unit configured to perform phase inversion on a clock signal that is output by the master controller, and output the phase-inverted clock signal to the storage device. The storage interface includes a second programmable input/output unit configured to delay a data signal that is output by the master controller, and output the delayed data signal to the storage device, where the delayed data signal is delayed by a time ?T relative to the clock signal that is output by the master controller, and TCLK/2??T?TISU and ?T?TIH, where TCLK represents a period of the clock signal, TISU represents a shortest input setup time required by the storage device in each of different data rate modes, and TIH represents a shortest input hold time employed by the storage device in each of different data rate modes.

Abstract: Generating a universal graphical desktop sharing protocol is disclosed. The universal graphical desktop sharing protocol is configured to communicate information (e.g., a sequence of one or more desktop sharing events) that has been translated from a first graphical desktop sharing protocol and is available to be translated into a final graphical desktop sharing protocol.

Abstract: A method for prefetching in a mass storage system, the method may include receiving or generating a request to fetch, to a cache memory of the mass storage system, a certain data unit that is currently not stored in the cache memory; wherein the certain data unit and additional data units form a certain cluster of data units; wherein the certain data unit and the additional data units have similar activity signatures; wherein at least two data units of the certain cluster differ from each other by at least one of (a) a file system, (b) a logical volume, and (c) an accessing unit; wherein for each data unit of the certain cluster, an activity signature related to the data unit provides a coarse estimation of activity related to the data unit during multiple time periods; fetching the certain data unit stored in a mass storage unit; and prefetching at least some of the additional data units that are not currently stored in the cache memory.

Abstract: In accordance with a first aspect of the present disclosure, a system is provided for verifying whether objects belong to a predefined set, the system comprising: a first radio frequency, RF, communication device comprised in or attached to a first object a second RF communication device comprised in or attached to a second object; an RF communication reader configured to perform a read operation; wherein a first portion of a valid response is provided in the first RF communication device and wherein a second portion of said valid response is provided in the second RF communication device; the system being configured to produce a positive verification result if the RF communication reader receives a sum of the first portion of the valid response and the second portion of the valid response. In accordance with a second aspect of the present disclosure, a corresponding method is conceived for verifying whether objects belong to a predefined set.

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.