Common Protocol (e.g., Pci To Pci) Patents (Class 710/314)
  • Patent number: 11226910
    Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 18, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Joseph Gerald McDonald, Garrett Michael Drapala, Eric Francis Robinson, Thomas Philip Speier, Kevin Neal Magill, Richard Gerard Hofmann
  • Patent number: 11216061
    Abstract: Aspects of the present disclosure relate to power bridge circuitry comprising a first interface configured to interface with a source power domain; a second interface configured to interface with a target power domain; transition circuitry to receive a transition indication that the power bridge circuitry is to transition to an idle state; communication circuitry to communicate messages between the interfaces; and message identification circuitry to identify messages communicated by the communication circuitry, the identification circuitry being configured to detect the communication of a given message directed to a target component connected to the second interface and indicating cessation of communication between the target component and a source component connected to the first interface.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 4, 2022
    Assignee: Arm Limited
    Inventors: Dominic William Brown, Christopher Vincent Severino
  • Patent number: 10936520
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 2, 2021
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, German Kazakov, Christopher R. Long, Jason Breakstone
  • Patent number: 10629285
    Abstract: Verifying a device under test (DUT) in which the DUT includes a bridge with a late write buffer includes storing write requests provided to the bridge in an initiator queue, and storing write requests provided to the target memory in a target queue. Upon both the initiator and target queues being non-empty, when entry addresses of top entries of the initiator and target queue match, data entries of the top entries of the initiator and target queue do not match, and the initiator queue has more than one entry, determining whether an entry address of a next entry in the initiator queue matches the entry address of the top entry in the initiator queue, and when the entry addresses of the next entry and the top entry in the initiator queue match, merging the top and next entry of the initiator queue and deleting the top entry of initiator queue.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventor: Prakashkumar Govindbhai Makwana
  • Patent number: 10628363
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data system is provided. The method includes initiating an isolation function in a communication fabric to form a peer arrangement between graphics processing units (GPUs) coupled to the communication fabric. The isolation function isolates a first address domain associated with the GPUs from at least a second address domain associated with the host by at least establishing synthetic devices representing the GPUs in the second address domain.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 21, 2020
    Assignee: Liqid Inc.
    Inventors: German Kazakov, Christopher R. Long, James Scott Cannata, Jason Breakstone
  • Patent number: 10585827
    Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a computing system is provided. The computing system includes a management processor configured to initiate a peer-to-peer arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device over a PCIe fabric comprising one or more PCIe switches. The peer-to-peer arrangement is established to detect data transfers from the first PCIe device directed to addresses corresponding to an address range established for the second PCIe device by a peer-to-peer management entity executed on a host processor, and redirect the data transfers over the PCIe fabric to the second PCIe device such that the data transfers are received by the second PCIe device without passing through the host processor.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 10, 2020
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Christopher R. Long, Sumit Puri, Bryan Schramm
  • Patent number: 10540185
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including one or more central processing units (CPUs), one or more storage modules and one or more PCIe switches to establish a first PCIe communication path between the management processor and a storage module of the one or more storage modules. The method also includes storing at least an operating system to the storage module using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the storage module. Moreover, the method includes instructing the PCIe fabric to establish a second PCIe communication path between a CPU of the one or more CPUs and the storage module comprising the operating system.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 21, 2020
    Assignee: Liqid Inc.
    Inventors: Henry Lee Harris, James Scott Cannata
  • Patent number: 10452499
    Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 22, 2019
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Jean Philippe Loison, Alexis Boutiller
  • Patent number: 10397113
    Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 27, 2019
    Assignee: Cavium, LLC
    Inventors: Vishal Anand, Tsahi Daniel, Gerald Schmidt, Premshanth Theivendran
  • Patent number: 10372648
    Abstract: A device management method and an apparatus. The device management method of the present disclosure includes receiving, by a switching device, diagnostic information sent by a managed device, where the diagnostic information is used to indicate at least one of a software version, a hardware version, or a running status of the managed device; and sending, by the switching device, the diagnostic information to a device management controller. The embodiments of the present disclosure resolve a problem of processing performance deterioration caused by device management performed by a central processing unit (CPU) of a server.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 6, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Xin Qiu
  • Patent number: 10248609
    Abstract: A modular interconnectivity assembly for interconnecting elements of a point of sale system, the modular interconnectivity assembly including at least one interconnectivity module including an Input/Output (I/O) hub having at least one upstream facing port and at least two downstream facing ports, at least one upstream connector connected to the at least one upstream facing port of the (I/O) hub and adapted for communication in accordance with a first communication protocol, at least one downstream connector connected to at least one of the at least two downstream facing ports and adapted for communication in accordance with the first communication protocol and at least one interface connected to another of the at least two downstream facing ports and adapted for communication in accordance with a second communication protocol, different from the first communication protocol.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 2, 2019
    Assignee: VERIFONE, INC.
    Inventors: Scott William McKibben, Ricardo Ernesto Espinoza-Ibarra, Dennis Carr, Paul Serotta
  • Patent number: 10180924
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes communicatively coupling graphics processing units (GPUs) over a Peripheral Component Interconnect Express (PCIe) fabric. The method also includes establishing a peer-to-peer arrangement between the GPUs over the PCIe fabric by at least providing an isolation function in the PCIe fabric configured to isolate a device PCIe address domain associated with the GPUs from at least a local PCIe address domain associated with a host processor that initiates the peer-to-peer arrangement between the GPUs.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 15, 2019
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, German Kazakov, Christopher R. Long, James Scott Cannata
  • Patent number: 9684607
    Abstract: The automated recovery of the warmth of cache of an application that has been subject to a running state change that degraded the warmth of the cache. To prepare for a loss in warmth, the state of a cache portion identifiers are captured. Such identifies the cache portions that are within the application cache at an instant in time. Thereafter, the application experiences a change in running state that diminishes the warmth of the application cache. For instance, the application might be stopped and restarted. After and despite this cache degradation, the application may continue to operate. However, in order to warm the application cache more quickly, while the application is operating, the application cache is automatically warmed. For instance, while the application is operating, cache portions identified by the captured cache portion identifiers are automatically accessed from a source that is external to the application cache.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: June 20, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nikhil Teletia, Jae Young Do, Kwanghyun Park, Jignesh M. Patel
  • Patent number: 9495723
    Abstract: A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 15, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Andrew Currid, Franck Diard, Chenghuan Jia, Parag Kulkarni
  • Patent number: 9424219
    Abstract: A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Eugene Saghi, Richard Solomon, Timothy E. Hoglund
  • Patent number: 9323706
    Abstract: Systems and methods for configuration snooping are provided. A bridge identifies an initialization message of a central processing unit (CPU) for a device that is downstream of a primary interface of the bridge. The bridge identifies a response to the initialization message. The bridge determines the address range for the device. The bridge stores the address range for the device in a list in the bridge.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: April 26, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9268732
    Abstract: A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 23, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Stephen D. Glaser
  • Patent number: 9244881
    Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: January 26, 2016
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Ben-Zion Friedman, Theodore L. Willke, Eliel Louzoun, Matthew R. Wilcox, Donald E. Wood, Steven B. McGowan, Robert O. Sharp
  • Patent number: 9100378
    Abstract: There is provided a file transfer device in which a determining unit determines, when a first file requested by a user terminal is not cached in a file buffering unit, a second file transferred to the user terminal based on a file cache status of the file buffering unit, a transfer protocol unit reads the second file from the file buffering unit while the file buffering unit reads the first file, a transmitting unit transmits the second file to the user terminal, wherein the instructing unit determines to transfer the first file, based on a progress status of reading the first file, the transfer protocol unit suspends reading the second file and reads the first file from the file buffering unit, the transmitting unit transmits the first file read by the transfer protocol unit to the user terminal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: August 4, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Goto, Nobuhiko Sugasawa, Yuta Kobayashi
  • Patent number: 9066039
    Abstract: A selective booting method and a broadcast receiving apparatus using the same are provided. The broadcast receiving apparatus including: a broadcast reception unit; a display which displays a broadcast received through the broadcast reception unit; a storage unit which stores a plurality of drivers of hardware provided on the broadcast receiving apparatus; and a controller which selectively loads a first driver, among the stored drivers, of first hardware for executing a first operation selected from among a plurality of operations, and then loads a second driver. Therefore, a user may execute foremost a desired operation.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seok Choi, Seung-kwon Park, Hee-soo Lee, Yong-jun Park
  • Patent number: 9043528
    Abstract: A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: May 26, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Shih-Min Hsu, Shao-Hung Chen
  • Patent number: 9032102
    Abstract: An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ilya Granovsky, Etai Adar
  • Publication number: 20150127875
    Abstract: PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
    Type: Application
    Filed: January 3, 2015
    Publication date: May 7, 2015
    Inventor: Mammen Thomas
  • Patent number: 8984205
    Abstract: A system includes an interface with a plurality of sub-addresses. The interface receives critical data and non-critical data. The critical data are received only at more specific sub-addresses of the interface. The interface transfers the critical data received at the sub-addresses to a critical processor, such that the critical data avoids being received by or being processed by a non-critical processor. The interface transfers the non-critical data from the interface to the non-critical processor. The configuration of the interface is hard-coded such that the configuration of the interface is fixed at power up of the interface and is non-changeable by the non-critical processor. The interface includes an external platform interface that is external to the critical processor, the non-critical processor, and a local controller. The external platform interface includes a limited ability to store the critical and non-critical data.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: March 17, 2015
    Assignee: Raytheon Company
    Inventors: David C. Robillard, Joseph D. Wagovich
  • Publication number: 20150052284
    Abstract: A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By configuring the non-transparent bridges appropriately, the network switch can facilitate a number of different communication mechanisms, including TCP/IP communication between servers, server clusters, and virtualized I/O device utilization. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. In another embodiment, the network switch is connected to an I/O device, and multiple servers are given access to that I/O device via virtualized connections.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 19, 2015
    Inventor: Jayanta Kumar Maitra
  • Publication number: 20150046627
    Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • Patent number: 8943256
    Abstract: An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gregory J. Landry, Edward L. Grivna
  • Publication number: 20150026385
    Abstract: Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.
    Type: Application
    Filed: June 25, 2014
    Publication date: January 22, 2015
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Norbert EGI, Robert LASATER, Thomas BOYLE, John PETERS, Guangyu SHI
  • Patent number: 8938568
    Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: January 20, 2015
    Assignee: Ineda Systems Pvt. Ltd
    Inventors: Balaji Kanigicherla, Siva Raghu Ram Voleti, Kirshna Mohan Tandaboina, Dhanumjai Pasumarthy
  • Publication number: 20150019788
    Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 15, 2015
    Inventors: Robert P. Adler, Eran Tamari, Mikal C. Hunsaker, Sridhar Lakshmanamurthy, Michael T. Klinglesmith, Blaise Fanning
  • Patent number: 8924621
    Abstract: An apparatus and method for a Universal Serial Bus (USB) isolating device. An USB isolating device includes a downstream facing circuit and a upstream facing circuit. The downstream facing circuit is coupled to a peripheral device via a first pair of signals and is configured for detecting a speed at which the peripheral device is operating based on a first voltage configuration on the first pair of signals. The upstream facing circuit is coupled to the downstream facing circuit and a host/hub via a second pair of signals and is configured for communicating with the downstream facing circuit on the speed of the peripheral device and adaptively creating a second voltage configuration on the second pair of signals to facilitate the host/hub to adapt to the speed of the peripheral device.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: December 30, 2014
    Assignee: Linear Technology Corporation
    Inventor: Brian Kirk Jadus
  • Patent number: 8918571
    Abstract: A method of selectively exposing expanders in a data storage fabric is disclosed. The method includes generating a phy permission table in a switch expander. The phy permission table is configured for access by an initiator and includes data as to which enclosure expanders are discoverable by the initiator. A zone group of phys from the enclosure expanders assigned to the initiator is created. The phy permission table is updated to identify each phy coupled to the enclosure expanders in the zone group.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 23, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael G. Myrah, Balaji Natrajan, Pruthviraj Herur Puttaiah
  • Publication number: 20140372659
    Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.
    Type: Application
    Filed: May 23, 2014
    Publication date: December 18, 2014
    Inventors: Gary Solomon, Robert A. Dunstan, Joe Schaefer, Brad Saunders
  • Publication number: 20140372658
    Abstract: Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
    Type: Application
    Filed: December 7, 2011
    Publication date: December 18, 2014
    Inventors: Robert J. Safranek, Robert G. Blankenship, Debendra Das Sharma
  • Patent number: 8909843
    Abstract: A peripheral component interconnect (PCI) express switch apparatus and a method of controlling a connection thereof are provided. In this apparatus, a first virtual bridge is connected to a computer system through a first PCI express port to perform data transmission and reception according to a PCI method with an external device, and a second virtual bridge is connected to an external device through the first virtual bridge and a second PCI express port and enables the external device to perform data transmission and reception with the computer system and according to the PCI method by cooperating with the first virtual bridge. A first cable matching device is connected to the first virtual bridge. Further, a second cable matching device is connected to the second virtual bridge and is connected to the first cable matching device through a PCI cable.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Yongseok Choi
  • Publication number: 20140351484
    Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
  • Patent number: 8868814
    Abstract: Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: October 21, 2014
    Assignee: NEC Corporation
    Inventors: Junichi Higuchi, Youichi Hidaka, Jun Suzuki, Takashi Yoshikawa
  • Patent number: 8862803
    Abstract: An apparatus for mediating communication between a universal serial bus (USB) device and a host computing device is described. In an example, the apparatus includes a USB host interface configured to be connected to a downstream USB device, and a USB device interface configured to be connected to an upstream host computing device. The apparatus also includes a mediation module positioned between the USB host interface and the USB device interface and configured to determine whether the USB device is authorized to communicate with the host computing device.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: October 14, 2014
    Assignee: Architecture Technology Corporation
    Inventors: Judson Powers, Matthew P. Donovan, Frank N. Adelstein, Michael Kentley, Stephen K. Brueckner
  • Patent number: 8856414
    Abstract: A method is included for loading a main loadable file and at least one optional loadable file during initialization of a computer system. The method includes loading a main loadable file which includes a resident portion and an input/output network interface software component. The resident portion is a utilization software component configured to use transmission protocols. The method also includes determining which optional loadable files are required to be loaded. The optional loadable files each include an optional portion. The method also includes loading the optional loadable files which contain optional portions corresponding to required protocols.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: October 7, 2014
    Assignee: LSI Corporation
    Inventor: James A. Lynn
  • Patent number: 8850098
    Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Rajesh Madukkarumukumana, James A. Sutton, II, Ioannis Schoinas, Richard Uhlig
  • Patent number: 8843686
    Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 23, 2014
    Assignee: Marvell International Ltd.
    Inventors: Ting Li Chan, Fredarico E. Dutton
  • Publication number: 20140237156
    Abstract: PCIe is a point-to-point protocol. A PCIe switch fabric has multi-path routing supported by adding an ID routing prefix to a packet entering the switch fabric. The routing is converted within the switch fabric from address routing to ID routing, where the ID is within a Global Space of the switch fabric. Rules are provided to select optimum routes for packets within the switch fabric, including rules for ordered traffic, unordered traffic, and for utilizing congestion feedback. In one implementation a destination lookup table is used to define the ID routing prefix for an incoming packet. The ID routing prefix may be removed at a destination host port of the switch fabric.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 21, 2014
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Jeffrey M. DODSON, Nagarajan SUBRAMANIYAN
  • Patent number: 8812760
    Abstract: An example method is provided and includes receiving a first signal transmitted to an address on a two-wire bus from a master device, where the two-wire bus couples the master device with a first slave and a second slave that share the address such that the first slave and the second slave receive the first signal. The method includes blocking a second signal from the second slave to the master device using digital isolation buffers. In particular embodiments, the digital isolation buffers are configured between the master device and the second slave. In addition, the two-wire bus may include a clock line and a data line. The digital isolation buffers may include a first digital isolation buffer located on the clock line between the master device and the second slave, and a second digital isolation buffer located on the data line between the master device and the second slave.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Harold E. Bamford, Ted R. Mila
  • Patent number: 8799550
    Abstract: A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: August 5, 2014
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Betty Luk, Gordon F. Caruk
  • Publication number: 20140215117
    Abstract: An electronic device includes a main board. The main board includes a number of PCI interfaces, an addressing unit, a determination unit, and a control unit. The addressing unit is configured for addressing addresses of each of the PCI interfaces of the main board from an address bus of the electronic device. The determination unit is configured for determining whether any PCI interfaces are not connected to corresponding PCI devices according to a value at the addressed addresses. The control unit is configured to turn off the PCI interfaces that are not connected to corresponding PCI devices. A method for controlling status of the PCI interfaces is also provided.
    Type: Application
    Filed: January 20, 2014
    Publication date: July 31, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (Shenzhen) CO., LTD.
    Inventors: MING-YI CHEN, HUAN DUAN
  • Patent number: 8788718
    Abstract: Methods and devices for manipulating HDMI-CEC messages transmitted over a network including at least two HDMI-CEC display devices with their associated at least two HDMI-CEC cluster trees that at least partially overlap, and enabling each of the HDMI-CEC display devices to communicate using HDMI-CEC with its associated HDMI-CEC cluster tree according to its current HDMI-CEC network view.
    Type: Grant
    Filed: August 17, 2008
    Date of Patent: July 22, 2014
    Assignee: Valens Semiconductor Ltd.
    Inventors: Eyran Lida, Nadav Banet
  • Patent number: 8788734
    Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: July 22, 2014
    Assignee: Icron Technologies Corporation
    Inventor: Terence C. Sosniak
  • Patent number: 8782318
    Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Chandra P. Joshi, Gurushankar Rajamani
  • Publication number: 20140195712
    Abstract: A processor module includes at least one storage device, at least one central processing unit (CPU) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the CPU.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 10, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Ha-uk RYU
  • Patent number: 8775691
    Abstract: An indication of a version of a firmware stored in an input/output adapter may be provided by a method that includes detecting whether a first pin is connected to an external circuit, detecting whether a second pin is unconnected to an external circuit, and causing the indication to be provided if the first pin is connected and the second pin is unconnected. The indication may be provided on the first pin. The first pin may include a power supply pin and the indication may be an average rate of power supplied to the input/output adapter.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cary L. Bates, Justin K. King, Lee Nee, Michelle A. Schlicht