Abstract: Protection circuits, USB interface integrated circuits, and methods for protecting host circuitry from USB port pin overvoltages, in which a switch is connected between a USB port pin and a middle node, and a detection circuit compares the middle node voltage with a reference voltage. A control circuit turns off the switch and turns on a clamp circuit to conduct pull down current from the middle node in response to the middle node voltage exceeding the reference voltage to mitigate overvoltage conditions on a host pin coupled to the middle node. When the middle node voltage falls below the reference voltage, the control circuit delays for a predetermined time and then turns off the clamp circuit and turns on the switch.

Abstract: Devices and methods for detecting the byte order (endianness) of a control device with which a peripheral device will exchange data. The control device initially transmits a special byte order determination data command to the peripheral device, which data command includes both a byte sequence having a byte order that can be read in any direction and still have the same value, and a specific data value that is known to both the control device and the peripheral device. Control device byte order is subsequently revealed by using the peripheral device to analyze the data value of the byte order determination data command in each of several possible byte orders to determine which byte order format results in a return of the expected specific value.

Abstract: A method and system are provided for transmitting SATA (serial advanced technology attachment) information. In an implementation, SATA commands are passed to an expander, rather than SCSI (Small Computer System Interface) commands. In an example implementation, SATA protocol elements are encapsulated into SAS (Serial Attached SCSI)-like frames and transmitted using the SSP (Serial SCSI protocol) and using SSP hardware.

Abstract: A data storage system provides asymmetric multi-path access to a storage device from a host computer using a storage protocol such as SCSI. Device state information is maintained indicating that one path of set of paths between the host computer and the storage device is a non-fully-functional path. In response to receiving device discovery commands from the host computer on the one path and the one path being indicated to be a non-fully-functional path, the data storage system returns respective good responses indicating that the storage device is accessible to the host computer via the non-fully-functional path. However, in response to receiving a test unit readiness command from the host computer on the one path and the one path being indicated to be a non-fully-functional path, an error response is returned which causes the host computer to select an alternative path of the set of paths for the data transfer.

Abstract: An internal voltage generation circuit includes a first control signal generation unit suitable for generating a first control signal activated to a level of a second external voltage when a first external voltage is activated, a second control signal generation unit suitable for generating a second control signal that equals the higher of the second external voltage and an internal voltage, and a voltage generation unit suitable for generating the internal voltage by performing a charge pumping operation based on the second external voltage and an oscillation signal while blocking a current flowing through a generation node from which the internal voltage is generated, based on the first and second control signals.

Abstract: A system includes a marshalling cabinet, a plurality of junction boxes, and an interface. The marshalling cabinet is configured to source a voltage in a plurality of cables through junction boxes to a plurality of field devices. Each of the junction boxes is configured to detect the voltage from the marshalling cabinet and transmit a detection message upon detecting the voltage. The interface is configured to receive the detection messages from the respective junction boxes that detect the voltage.

Abstract: An I2C router system includes an I2C router part, a first slave device and a second slave device. The I2C router part includes a first I2C router configured to output a first I2C signal via a first I2C bus, and a second I2C router configured to output a second I2C signal via a second I2C bus. The first slave device can be configured to receive the first I2C signal via the first I2C bus. The second slave device can be configured to receive the second I2C signal via the second I2C bus.

Abstract: Buffer rate control generally relates to outputting data at either a first rate or a second rate responsive to a fill level of the buffer. In an apparatus therefore, there is a buffer for receiving a data-signal input and for providing a data-signal output. A controller is coupled to receive fill-level information from the buffer and coupled to provide rate-control information to the buffer. The rate-control information is for controlling an output rate of the buffer for the data-signal output to be provided to a bus. The output rate is either a first rate or a second rate for providing the output rate of the data-signal output to the bus. The fill-level information is for selecting either the first rate or the second rate responsive to the buffer being either above or below a threshold fill level, respectively.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A method for enabling access to a data resource, which is held on a file server (25) on a first local area network (LAN) (21a), by a client (28) on a second LAN (21b). A proxy receiver (48) on the second LAN (21b) intercepts a request for the data resource submitted by the client (28) and transmits a message via a wide area network (WAN) (29) to a proxy transmitter (52) on the first LAN (21a), requesting the data resource. The proxy transmitter (52) retrieves a replica of the data resource from the file server (25) and conveys the replica of the data resource over the WAN (29) to the proxy receiver (48), which serves the replica of the data resource from the proxy receiver (48) to the client (28) over the second LAN (21b).

Abstract: Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in place of the physical link.

Abstract: Provided is a video and audio reproduction apparatus including a display unit; a speaker unit; a main board; and a power supply unit, and the main board includes a printed circuit board; a first connector area which is formed on a front side of the printed circuit board; a second connector area which is formed on the front side of the printed circuit board; and a main chip which is surface-mounted on a back side of the printed circuit board.

Abstract: A method and a system to automatically segment text based on header tokens is described. A relevance value and an irrelevance value are determined for each token in a description, assuming no tokens are left out of computations. The irrelevance value is based on occurrences of a token in a sample set of descriptions. The relevance value is an estimated probability of relevance based on the header of the description being segmented.

Abstract: A system on a chip includes a network, an interface and a bridge module. The network includes one or more devices. The network is configured to operate in a first domain. Communication in the first domain is based on a first set of read and write ordering rules. An interface is connected between the network and a second chip. Communication between the interface and the second chip is in a second domain. Communication in the second domain is based on a second set of read and write ordering rules. The second set of read and write ordering rules are different than the first set of read and write ordering rules. The bridge module is configured to map communication transactions between the first domain and the second domain.

Abstract: A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip.

Abstract: A method for monitoring the coordinated execution of sequenced tasks by an electronic card including at least one first processor (PP1) and a second processor (PP2) synchronized to the same clock of determined time period, includes: recording in memory means by the first processor (PP1) of a first identifier (ID1) characterizing the time period (T1) in the course of which the first sequenced task has been executed; recording in the memory means by the second processor (PP2) of a second identifier (ID2) characterizing the time period (T1) in the course of which the first accessory task (N1) has been executed; comparing by the first processor (PP1) the first identifier (ID1) and the second identifier (ID2); and signaling by the first processor (PP1) in the case of failure of the comparison so as to signal a defect of coordination of the processors (PP1, PP2).

Abstract: A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed.

Abstract: Techniques are provided for using an intermediate cache between the shared cache of an application and the non-volatile storage of a storage system. The application may be any type of application that uses a storage system to persistently store data. The intermediate cache may be local to the machine upon which the application is executing, or may be implemented within the storage system. In one embodiment where the application is a database server, the database system includes both a DB server-side intermediate cache, and a storage-side intermediate cache. The caching policies used to populate the intermediate cache are intelligent, taking into account factors that may include which object an item belongs to, the item type of the item, a characteristic of the item, or the type of operation in which the item is involved.

Abstract: Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the SD card form factor and is configured to receive a device. In use, a removable memory card is inserted into the receptacle and, using an SD compliant interrogation signal, the host interrogates a common area on the card so inserted. The common area includes information related to capability descriptors of the card. An SD compliant card will respond with information such as capability descriptors about the SD protocol capabilities, while a UFS compliant card will respond with an indication that the card is UFS compliant. The host may then restart the communication with the card using the UFS protocol.

Abstract: A method for optimized address pre-translation for a host channel adapter (HCA) static memory structure is disclosed. The method involves determining whether the HCA static memory structure spans a contiguous block of physical address space, when the HCA static memory structure spans the contiguous block of physical address space, requesting a translation from a guest physical address (GPA) to a machine physical address (MPA) of the HCA static memory structure, storing a received MPA corresponding to the HCA static memory structure in an address control and status register (CSR) associated with the HCA static memory structure, marking the received MPA stored in the address CSR as a pre-translated address, and using the pre-translated MPA stored in the address CSR when a request to access the static memory structure is received.

Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors and at least one of on-board memory and an external communication controller. The plurality of connectors is configured to fit with a form factor of a socket on a server board. The server board includes at least one processor and a circuit board having the socket and at least one processor socket. The processor(s) are coupled with the processor socket(s). The socket has the form factor configured for a module having a first functional set and the form factor. The at least one of the on-board memory and the external communication controller is coupled with at least some of the connectors. The external communication controller also has a second functional set different from the first functional set. The on-board memory is configured to be usable by the processor(s).

Abstract: A technique synchronizes de-registration of registered memory and incoming input/output (I/O) data received from an I/O device for storage in a memory of a computer system. Registration and de-registration of the memory with an I/O memory management unit (IOMMU) are illustratively performed by an I/O device driver of the computer system in anticipation of (or in response to) an I/O request to store the incoming I/O data in buffers of the memory. The synchronization technique ensures that storage of the I/O data in the buffers and de-registration of the buffers occur in a coordinated, reliable manner to obviate data corruption or other error conditions that may manifest in response to a race condition between such data storage and memory de-registration. Notably, I/O data which may be in-flight (i.e., inbound) from a sender to the I/O device may be received without error even when active buffers are deregistered.

Abstract: Embodiments of the invention relate to non-standard input/output (I/O) adapters in a standardized I/O architecture. An aspect of the invention includes implementing non-standard I/O adapters in a standardized I/O architecture. A request is received at an I/O adapter from a requester to perform an operation on one of the I/O adapters. It is determined that the request is in a format other than a format supported by an I/O bus and that the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus, and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus. The completion response is transmitted to the requester.

Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: Provided is a storage apparatus and a method for controlling the storage apparatus which are capable of achieving both enhancement of data transfer processing efficiency and enhancement of apparatus availability. A storage apparatus including a storage medium for providing an external apparatus with a data storage area has a processing unit including a plurality of processors and a shared memory for storing programs executed by the processors and is configured such that the processors receive data I/O requests and store the data I/O requests in the shared memory as storage medium control information for the storage medium. The storage medium controller executes data processing of writing or reading target data for the corresponding data I/O processing request to or from the storage medium on the basis of the storage medium control information transmitted from the external apparatus.

Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester.

Abstract: An apparatus, comprising a housing; a first connector coupled to the housing and having a first plurality of contacts; a second connector coupled to the housing and having a second plurality of contacts; and a circuit electrically connected to at least one of the first contacts and at least one of the second contacts. The circuit is encapsulated within the housing. The circuit is configured to generate an output signal in response to a resistance sensed at the at least one of the first contacts.

Abstract: A connective transmission device of the invention may include a first interface configured to connect to a first device; a second interface configured to connect to a second device; and a control module connected to the first interface and the second interface. When the first interface is connected to the first device and the second interface is connected to the second device, the control module is configured to connect the first device and the second device for data transmission or power transmission, or configured to receive a media message from the first device or the second device.

Abstract: A multimedia residential gateway device for providing video services to multiple televisions within a home. The device receives incoming video content from a DSL, DOCSIS, or Ethernet data stream and outputs selected content to individual televisions, with the content for each television being transmitted over an ATSC or NTSC channel associated with each television. This eliminates the need for multiple set top boxes in a high-definition offering. Radio frequency handheld remotes for each television are provided which communicate directly with the gateway device. The device may also be provided as a multi-television set top box, wherein the device receives Ethernet data streams from a customer's existing residential gateway.

Abstract: In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from AP.

Abstract: In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP.

Abstract: Embodiments disclosed herein include operating the M-PHY communications over peripheral component interconnect (PCI)-based interfaces. Related cables, connectors, systems, and methods are also disclosed. In particular, embodiments disclosed herein take the M-PHY standard compliant signals and direct them through a PCI compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having PCI connectors to communicate.

Abstract: Example apparatus and methods to communicatively couple field devices to controllers in a process control system are disclosed. An example method of changing a communication protocol of a first field device in a process control system includes decoupling from the first field device a first removable communication module configured to communicate using a first communication protocol. The example method also includes coupling to the first field device a second removable communication module configured to communicate using a second communication protocol. After coupling the second removable communication module, the first field device is configured to communicate using the second communication protocol.

Abstract: Initiating, by USB device adaptors, USB connections over a non-USB network, including the steps of: Connecting non-collocated USB hosts with respective non-collocated USB host adaptors (USBHs), according to USB specification timings. Connecting non-collocated USB devices with respective non-collocated USB device adaptors (USBDs). Enabling the USBDs and the USBHs to communicate over the non-USB network that enables each USBD to discover the presence and capabilities of each USBH. Receiving, by the USBDs, information about the USB hosts. And then, initiating by the USBDs USB-over-network connections between the USB devices and the USB hosts.

Abstract: Initiating, by USB host adaptors, USB connections over a non-USB network, including the steps of: Connecting non-collocated USB hosts with respective non-collocated USB host adaptors (USBHs), according to USB specification timings. Connecting non-collocated USB devices with respective non-collocated USB device adaptors (USBDs). Enabling the USBHs and the USBDs to communicate over the non-USB network that enables each USBD to discover the presence and capabilities of each USBH. Receiving, by the USBHs, information about the USB devices. And then initiating, by the USBHs, USB-over-network connections between the USB hosts and the USB devices.

Abstract: Methods and systems for memory interface systems are provided. A first command from control circuitry is received by bridge circuitry at a first clock rate. The control circuitry is configured to operate at the first clock rate. A second command is generated by the control circuitry on the received first command. The second command is transmitted to memory circuitry at a second clock rate. The memory circuitry is configured to operate at the second clock rate, and the second clock rate is greater than the first clock rate.

Abstract: Connecting USB devices with USB hosts over a network supporting distributed initiations of USB connections over the network, including the following steps: Connecting non-collocated USB hosts with respective non-collocated USB host adaptors (USBHs), according to USB specification timings. Connecting non-collocated USB devices with respective non-collocated USB device adaptors (USBDs). Enabling the USBDs and the USBHs to communicate over the network and to discover the presence and capabilities of one another. Initiating, by the USBDs or the USBHs, via the network control plane, USB-over-network-data-plane connections between the USB devices and the USB hosts. And operating at least two of the USB-over-network-data-plane connections essentially simultaneously and without any common network node.

Abstract: A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Abstract: A disclosed example apparatus includes a first interface to be communicatively coupled to one of a first field device or a second field device. The first interface communicates using a first fieldbus communication protocol when coupled to the first field device and communicates using a second fieldbus communication protocol when coupled to the second field device. The example apparatus includes a communication processor to encode first information received from the one of the first field device or the second field device for communication via a bus using a third communication protocol. The example apparatus includes a second interface communicatively coupled to the communication processor and the bus to communicate the first information to a controller in the process control system. The bus is to use the third communication protocol to communicate second information received from the other one of the first field device or the second field device.

Abstract: Safe bus devices use a safety protocol in order to transmit safe data encapsulated in an industrial Ethernet message via an Ethernet-based field bus. However, this restricts the safe bus device to a certain combination of safety protocol and industrial Ethernet protocol. In order to be able to use a safe bus device 12, 14, 151 more flexibly, it is provided that, to transmit the safety-oriented data, the industrial Ethernet protocol uses the session layer 5 and/or presentation layer 6 of the safety protocol, which is independent of the industrial Ethernet protocol, instead of the session layer 5 and/or presentation layer 6 which is implemented in the industrial Ethernet protocol, whereby such a bus device 12, 14, 151 becomes independent of the industrial Ethernet protocol.

Abstract: A communication converter for connecting automation devices having different operating voltages to a host computer, including an interface component and a transceiver component coupled to the interface component, the interface component being connected on the input side via a host connector to a host interface of the host computer and the transceiver component being connected via a device connector to a device interface of the automation device, and a voltage transformer, which on the input side is connected via the host interface to an operating voltage and on the output side to a voltage supply line of the device interface. So the communication converter can communicate with devices having different interface standards, the converter has a first current/voltage measuring unit, a second current/voltage measuring unit, and a switching device.

Abstract: Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol.

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract: A signal relaying circuit includes an input interface arranged for receiving an input signal; a DisplayPort (DP) output interface arranged for outputting a DP-like signal, where the input interface and the DP output interface correspond to different interface standards; and a relaying circuit coupled between the input interface and the DP output interface, arranged for relaying the input signal to the DP output interface according to the characteristics of channels, so as to generate the DP-like signal. A signal receiving circuit, signal relaying method and signal receiving method are also disclosed.

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: An image forming apparatus includes: an image forming unit; a power supply controller controls the image forming apparatus to operate in a power saving mode, in which supply of power to the image forming unit is cut off, and a normal mode; and a plurality of interfaces that receives a transition command for transitioning from the power saving mode to the normal mode. The power supply controller is configured to perform: an interface-power supply process of supplying power to at least one interface; a determining process of determining whether availability is high or low for an operating interface receiving power supply in the interface-power supply process; and a changing process of changing a power supply target from the operating interface to an idle interface when the availability of the operating interface is determined to be low.