Abstract: A system and method for providing a serial communication bus is disclosed. A serial communication bus connects multiple footprint devices, such as electronic sensors in a process control sample system. The footprint devices can utilize various footprint device specific communication protocols. Multiple tophat devices act as general I/O ports for connecting with the footprint devices. Each tophat device identifies the footprint device specific communication protocol of a connected footprint device, converts outputs signals transmitted from the connected footprint device from the footprint device specific communication protocol of the footprint device to a standard bus communication protocol, and converts input signals directed to the connected footprint device from the standard bus communication protocol to the footprint device specific communication protocol of the footprint device.

Abstract: Certified Wireless USB 1.0 defines two different types of association: cable association and numeric association. In order to implementation these two association methods, the CWUSB device needs to have either upstream USB connector (for cable association) or display capability (for numeric association). These extra requirements make the CWUSB device bulkier (one more USB connector) and/or more expensive (extra display components). For cheap and simple CWUSB devices, we need a simpler association method that is easy and cheap to implement. In a pre-packaged total solution, which includes a host and one or more device(s), we can use pre-association to smooth the user experience. The host and device(s) are pre-associated. When an end user starts to use this solution, they do not need to worry about the association at all.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: An interface for transmitting messages between two bus systems including a receiver device for receiving a message from the first bus system, a classification device for classifying the message received from the first receiver device according to one of several predetermined classes, a translation device for translating the message based on a predetermined rule for each class into a message for transmission on the second bus system, and a transmitter device for transmitting the translated message on the second bus system.

Abstract: A circuit interfaced between a first USB host and a second USB host for providing unidirectional transmission of data signals from the first USB host to the second USB host is provided. A first converter circuit is operable to receive data signals from the first USB host and convert them from a USB protocol to a second communications protocol. A second converter circuit is operable to receive the converted data signals from the first converter circuit and convert them from the second communications protocol to the USB protocol for transmission to the second USB host. The first and second converter circuits are electrically connected to each other in such a manner as to provide a transmission path from the first USB host to the second USB host and to disable a transmission path from the second USB host to the first USB host.

Abstract: The present invention may be related to a bridge for communications between a first computing device and a second computing device in a data communication system. The bridge may include a first interface, a second interface and a control module. The first interface may be adapted to couple with the first computing device. The second interface may be adapted to couple with the second computing device. The control module may be configured to process a file input/output (I/O) command from the first computing device so as to allow the first computing device to have access to at least one of data or resource of the second computing device via the first and second interfaces. Moreover, the control module may further include a parser, a decoder and a micro processor. The parser may be configured to identify whether the file I/O command includes an encoded controller command and retrieve the encoded controller command from the file I/O command if the file I/O command includes an encoded controller command.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SAS standard and causing communication between one or more hosts and a SATA/SAS device. The communication system includes a multi-port bridge device including two or more SAS ports through which the bridge device communicates to hosts. The multi-port bridge device further includes a SATA port through which the bridge device communicates to a SATA device, each said SAS ports having associated therewith addresses for identifying the ports, the bridge device operative to generate addresses unique to each SAS port and operative to communicate the port addresses, through a SAS frame, wherein identification of SAS ports is achievable even when the SATA device is inoperational.

Abstract: A flash storage chip including a single circuit board, a microcontroller, a flash memory, and a peripheral component interconnect express (PCI Express) connecting interface is provided. The microcontroller, the flash memory, and the PCI Express connecting interface are embedded on the single circuit board, and the microcontroller has a flash memory interface and a PCI Express interface. When a host writes a data into the flash storage chip, the microcontroller receives the data though the PCI Express interface and stores the data into the flash memory though the flash memory interface. When the host reads a data form the flash storage chip, the microcontroller reads the data from the flash memory though the flash memory interface and transmits the data to the host though the PCI Express interface and the PCI Express connecting interface.

Abstract: Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A cover that is hinged to the card to normally cover one set of contacts can be manually rotated out of the way when that set of contacts is being used.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connecting to a first memory, and a second memory controller connected to the switch for optionally connecting to a second memory. The IO processor may be connected to the external CPU, to the second memory, or be capable of connecting to external CPUs of different ranks, depending on the situation, so as to meet the cost considerations and the actual application requirements.

Abstract: A signal processing board including a resource board substrate, an external interface on the board substrate, adapted to receive signals for processing, at least one slot adapted to receive a plug-in module with at least one processor thereon and an interface unit adapted to at least participate in converting signals exchanged between the external interface and a processor on a module received by the slot, between a format of signals received by the external interface and a signal format of the processor. The interface unit is suitable to at least participate in the conversion for a plurality of types of processors that differ in the format in which they transmit or receive signals.

Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.

Abstract: Certain aspects of a method and system for interlocking data integrity for network adapters are disclosed. Aspects of one method may include executing a plurality of interlocking checks within a network adapter. Each interlocking check may comprise receiving a plurality of input check values associated with a plurality of input data packets corresponding to a first protocol. A plurality of check values may be generated which are associated with the plurality of input data packets and a plurality of output data packets corresponding to a second protocol. The data integrity of the plurality of input data packets and the plurality of output data packets may be validated based on one or more comparisons between one or more of the generated plurality of check values and one or more of the received plurality of input check values.

Abstract: The present invention provides a method and apparatus for controlling the operating condition of a peripheral device based on the mode of interconnection of the peripheral device of a host device. The apparatus includes a first connector for connecting the peripheral device, a second connector for connecting the host device and a coupling system operatively interconnecting contacts of the first connector and contacts of the second connector. The coupling system is further configured to provide a supply signal to the peripheral device via the first connector, wherein the supply signal is at least in part indicative of one or more characteristics of the power available to the peripheral device from the host device. The supply signal may provide a means for the peripheral device to control operation thereof in light of the characteristics of the power available.

Abstract: Methods and apparatus for translating messages in a computing system are disclosed. In particular, a disclosed method for converting messages in a computer system includes receiving a command message from a processing unit where the message is defined according to a transport protocol that utilizes command messages using an address to communicate commands to devices in the computer system. The command message is translated to an interface standard by mapping the address into an address field of a packet constructed according to the interface standard. Corresponding apparatus that perform the methods are also disclosed.

Abstract: A process for the transmission of data between a processor and a mass memory unit, initialization and/or control commands are transmitted via a PCMCIA interface to the mass memory unit, while user data, however, are transmitted via a memory interface. Accordingly, a device for the transmission of data between a processor and an (ATA) mass memory unit has a driver designed for switching over the transmission paths of initialization and/or control commands via a PCMCIA interface and of user data via a memory interface.

Abstract: A smart translator “SMARTX” box provides an aircraft outfitted with an analog AGM-65 (“Maverick”) interface with the same “look and feel” and capability to use a store outfitted with a digital MIL-STD-1760 interface as if the aircraft was fully 1760 compliant without any modifications to the electronics or software of either the aircraft or store.

Abstract: Methods and apparatus for adding an autonomous controller to an existing architecture such as by way of example, portable devices such as cell phones, MP3 players, and digital cameras. A circuit interposed between the memory card and the system controller of the device is controllable to couple the memory card to the system controller, or to couple the memory card to a high speed I/O controller on the circuit. When the memory card is coupled to the high speed I/O controller on the circuit, the circuit provides signals to the system controller indicative of a memory card removal event. In systems having an I/O connection such as a USB connection, the circuit also disconnects that connection from the system controller, provides signals to the system control indicative of a USB disconnect and connects the I/O connection to the memory card through a high speed data transfer unit to provide a higher speed I/O capability. Various features and capabilities are disclosed.

Abstract: A data diode comprises a USB input port coupled to a first USB to RS422 converter, which is coupled to a first serial port. A second serial port is coupled to a second USB to RS422 converter, which is coupled to a USB output port. The TX-pin of the first serial port is connected to the RX-pin of the second serial port and the TX+ pin of the first serial port is connected to the RX+ pin of the second serial port. The TX ports of the second serial port are not connected to the RX ports of the first serial port, thereby preventing reverse data flow.

Abstract: An apparatus connected to a first and second buses, the apparatus having a first controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a second controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a first distributing unit connected to the first and second controllers, the first distributing unit distributing first form data to the first and second controllers, respectively, a first selector that selects one of the second form data, and outputs the selected data, a second distributing unit connected to the first and the second controllers, the second distributing unit distributing second form data to the first and second controllers, respectively, and a second selector that selects one of the first form data, and outputs the selected data

Abstract: A data storage device comprises a data storage medium; an interface between the data storage medium and a host device configured to provide connectivity according to a plurality of storage interconnect standards. The data storage device also includes a interconnect detector configured to determine the presence of a physical connection to the host device and identify an interconnect standard of the host device, wherein the interconnect standard of the host device is one of the plurality of storage interconnect standards; and a controller configured to: receive an indication of the interconnect standard of the physical connection from the interconnect detector, receive data access commands in accordance with the interconnect standard from the host device via the connector; process the data access commands by accessing the data storage medium; and send a response to the data access commands in accordance with the interconnect standard to the host via the connector.

Abstract: An electronic flash memory external storage method and device for data processing system, includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores date by flash memory and access control circuit 2 with the cooperation of the firmware, driver and operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in statistic state and is driven by software. It is plug-and-play and adapted to data processing system.

Abstract: A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in problem state memory. The active package is switched to the child node, and the processor switches from running in privileged mode to running in problem mode. FCode of an FCode driver in the PCI device is probed. Data, properties and methods generated in response to the probe are created in problem state memory. After the probe is complete, the active package is switched to the parent node of the child node, and the processor switches back to running in privileged mode.

Abstract: There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmitted to the bus of the respective bus system in its own cycle. A predetermined or predeterminable number of data items is buffered from a data sequence that is to be transmitted from the original bus system to the target bus system, and a respective data item is determined on the basis of the cycle time TB of the target bus system from the data buffered on the basis of cycle time TA of the original bus system.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: The present invention provides methods and modules allowing for mapping of interface signals at for instance multi-line buses. A mapping of internal signal order schemes to external signal order schemes is enabled such that upon configuration any interface signals may carried on any lines of a multi-line bus. The configurability may obtained by the implementation of mapping logics and mapping algorithms, which associates external interface terminal to signal association to internal interface terminal to signal association in a configurable manner.

Abstract: First and second networks, for example Controller Area Networks (CANs), of different physical layers are interfaced by applying signals of the busses of the two networks to respective transceivers. A dominant state of one of the busses is sensed and data is transferred between the two transceivers in a direction from the dominant bus. The two busses are interfaced by a logic circuit interposed between the transceivers. A control circuit is coupled to the first and second logic units for mutually exclusively activating and deactivating the first and second logic units to control the direction of data transfer between the busses.

Abstract: A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.

Abstract: Embodiments of peripheral pointing devices and methods for manufacturing the same are generally described herein. In at least one embodiment, a peripheral device comprises a housing, one or more buttons at a first side of the housing, a displacement tracker at a second side of the housing, a keypad comprising keys at the second side of the housing; and a keypress restrictor coupled to the housing. Other examples, embodiments, and related methods are further described below.

Abstract: To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.

Abstract: A telecommunications system and constituent two-wire interface module. The two wire interface module includes a logic component configured to communicate over the same pair of wires using different two-wire interface protocols depending on an input signal presented on a configuration input. This configurability allows the two-wire interface module to use the same two wires to communicate with a variety of other two-wire interface modules, even if those two-wire interface modules communicate using different two-wire interface protocols.

Abstract: Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.

Abstract: A host device and an accessory exchange information (e.g., commands and data) via an intermediate device. The host device and accessory can each connect to the intermediate device. The host device can exchange commands and data with the intermediate device, while the accessory device can serially exchange data with the intermediate device. The host device and the accessory can also “tunnel” information to each other through the intermediate device, by packaging the tunneled information as a payload of a command recognizable by the intermediate device; the intermediate device can repackage and forward the payload. In some embodiments, the intermediate device can control serial communication parameters between the intermediate device and the accessory in response to commands received from the host.

Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.

Abstract: ASCII gateway to in-vehicle system provides bi-directional translation between multiplexed motor vehicle networks and industrial control and monitoring devices. Integrated hardware and software components provide data communications between motor vehicle electronic control module networks and RS-232 serial ASCII-text capable device, for industrial control and/or industrial automation application in manufacturing or assembly operations. Communications networks (CAN, SAE or ISO protocols) implemented inside motor vehicles pass data'between electronic control modules that control operation of important vehicle components like engine, transmission and brake systems, have their messages converted to RS-232 serial ASCII-text; and from RS-232 serial ASCII-text converted to motor vehicle communications network by the system. Messages to monitor and/or control vehicle networks are generated by a serial ASCII-test capable device. Multiple vehicle protocols are supported by the system.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: A bridge circuit that is located between a peripheral device and a USB connection to a host. The bridge stores data indicating the amount of power required to execute each particular command. When a command is received, the command is executed if this list indicates that a particular command can be executed with the available power. If the list indicates that the command can not be executed with the available power, the command is either rejected or delayed. The bridge may include a power storage device that accumulates and stores power. In this case the list of commands would indicate commands that can be delayed until the storage device has accumulated sufficient power.

Abstract: A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.

Abstract: An electronic device, operating as a USB host, has an embedded processor and a system memory, connected by a memory bus. A host controller integrated circuit does not need to master the system memory, but instead acts purely as a slave. The embedded processor is then adapted to write the data to the host controller integrated circuit in the form of transfer-based transactions.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.

Abstract: Systems and methods for booting a host device(s) from a peripheral device(s), via an interface, such as an MMC/SD interface, with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal. Power is provided to the power terminals, and the command terminal of the MMC/SD or analogous interface is set during power-up to low. The data bus is monitored for a start bit of data transmission.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

Abstract: This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.

Abstract: A hardware/software system and method that collectively enables virtualization of the host computer's native I/O system architecture via the Internet and LANs. The invention includes a solution to the problems of the relatively narrow focus of iSCSI, the direct connect limitation of PCI Express, and the inaccessibility of PCI Express for expansion in blade architectures.

Abstract: A method and integrated circuit for providing enclosure management services compatible with a multitude of physical interfaces and protocols for exchanging enclosure management data between an HBA and an enclosure management backplane is provided. According to one method, two or more interfaces utilized for exchanging enclosure management data may be monitored to determine whether one of the interfaces is actively being utilized by an HBA to transmit enclosure management data. If one of the interfaces is identified as being active, a determination is then made as to which of a plurality of protocols for transferring enclosure management data is being utilized on the active interface. In particular, a determination may be made as to whether a protocol defined by one HBA manufacturer is being utilized or whether another protocol defined by another HBA manufacturer is being utilized.

Abstract: A network (100) includes a hub device (110) and at least one unattached peripheral device (120). The unattached peripheral device (120) transmits an attach request to the hub device (110) with a selected address, receives a new address from the hub device to identify the unattached peripheral device (120), and communicates with the hub device (110) using the new address.

Abstract: An improved extended cardbus/PC card controller (20) incorporating proprietary Split-Bridge™ high speed serial communication technology for interconnecting a conventional parallel system bus via a high speed serial link with a remote peripheral device. The extend cardbus/PC card controller is adapted to interface the parallel system bus, which may be PCI, PCMCIA, integrated, or some other parallel I/O bus architecture, with peripheral devices via PC cards, and now optionally via a high speed serial link using the proprietary serial Split-Bridge™ technology. The serial Split-Bridge™ technology provides real time interconnection between the parallel system bus and the remote device which may also be based on a parallel system data bus architecture, over a serial link, which serial link appears to be transparent between the buses and thus facilitates high speed data transfer exceeding data rates of 1.0 GigaHertz.