Abstract: A traffic manager for a network switch port stores incoming cells in a cell memory and later forwards them out of the cell memory and the switch port. Each cell is assigned to one of several flow queues and each flow queue has an assigned minimum forwarding bandwidth with which cells of that flow queue must be forwarded from the cell memory and has an assigned maximum bandwidth with which cells of that flow queue may be forwarded. When any flow queue is active (i.e., when it has cells currently stored in the cell memory), the traffic manager allocates a sufficient amount of the switch port's available cell forwarding bandwidth to each active flow queue so that cells of that flow queue are forwarded with at least the flow queue's assigned minimum bandwidth.

Abstract: A switch matrix 10 is provided comprising a plurality of input modules X and a plurality of output modules P. Each input module 16 has a plurality of first input interconnections 14, a plurality of first interconnected switches 21, and a plurality of first output interconnections 20. Each output module 18 has a plurality of second input interconnections 23, a plurality of second interconnected switches 24, and a plurality of second output interconnections 20. The plurality of input modules X is electrically coupled to the plurality of output modules P, forming a plurality of signal paths 12 having a plurality of interconnected switches K per signal path 12. A method is also provided minimizing the total number of interconnected switches Z within the switch matrix 10 for a particular application. The method comprises determining switch matrix design requirements, calculating the values of X and P, and performing an integer partitioning process.

Abstract: A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of queue switch transistors, source to drain for data switched onto the bus, the queue switch transistors gated simultaneously by control lines from an on-board arbitrator controller following a preprogrammed arbitration scheme. Data is switched off the bus and hub by port adapter controllers connected to read amplifier receivers connected directly to the on-chip bus, the port adapter controllers enabled by the arbitrator controller following the same preprogrammed arbitration scheme. Ports may be serial or parallel, and may be adapted to special purposes, such as PCI and hub to hub connection for expansion.

Abstract: A system and method for transferring information at a fast rate between add-in cards in a rack mount system are described. In one embodiment, the invention allow all the add-in cards within the rack mount system to be interconnected. All the main cards within the rack mount system connect to a switch card using point-to-point differential copper pairs. All communication over these differential copper pairs use a messaging protocol that provides a messaging protocol destination address that is used to route the information to the intended destination main card. The messaging protocol may be the Ethernet protocol. In an alternative embodiment, data redundancy is provided by having two switch cards in the rack mount system. A particular main card transmits one set of information to the first switch card and a second set of information (that is identical to the first set of information) to the second switch card.

Abstract: A requester includes an output data register which retains a data piece to be output to a relay register of a crossbar, and two request registers which output a request corresponding to the data piece. The requester sets a next data piece in the output data register, and sets a corresponding request in the request register in response to a selection signal from the crossbar. The crossbar outputs a grant signal representing that output of a data piece output from the requester to an output port is permitted to the requester, and at the same time, switches selection between requests from the two request registers in accordance with a request selection register prepared in advance, and inputs the selected request to an arbiter.

Abstract: A method to determine the read capability and/or the write capability of one or more input/output devices and one or more information storage media disposed in a computer system whereby a device bit is set for each input/output device based upon the device's write capability, a media bit is set for each information storage medium based upon the writeability of that medium, each device bit and each medium bit is stored for future reference. A method to write information to a designated information storage medium using an allocated data storage device using a specified information recording format, whereby a previously-determined media bit for the designated information storage medium is examined, and a previously-determined device bit for the allocated data storage device is examined, and the write capability of the designated information storage medium using the specified information recording format is determined.

Abstract: A network and storage I/O device is described for use with a host computer system having a system bus coupled to a host processor and a main memory to provide a high bandwidth network server system. The network and storage I/O device includes a plurality of network controllers to communicate with client computers connected over a network, a plurality of storage controllers to transfer data to and from storage devices, at least one memory element to temporarily store data transferred between the network controllers and the storage controllers and a crossbar switch having a plurality of nodes to interconnect the plurality of network controllers, the plurality of storage controllers and the at least one memory element. The network and storage I/O device also includes a bridge coupled between one of the nodes and the system bus of the host computer.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: A method and system for switching signals over conductors is disclosed. The method and system comprises a plurality of encoders for receiving signals from a plurality of sources. The system further comprises a crosspoint switching matrix means for receiving encoded signals from the plurality of encoders and for providing encoded signals to a plurality of receivers. The crosspoint switching matrix means in a preferred embodiment includes a control system which is controlled by multiple remote receivers.

Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

Abstract: A memory system having a backplane with a plurality of receiving slots. Each one of the slots has electrical contacts for providing an indication of Such one of the slots. Each one of the slots has a different slot indication. A plurality of memory boards is provided. Each one of the memory boards is plugged into a corresponding one of the slots. Each one of such boards is coupled to the electrical contacts in the corresponding one of the slots to provide a slot signal indicative of the slot indication provided by the electrical contacts. Each one of such boards has: a memory array region; and a switching network for transferring information between a port of the switching network and a memory on such memory boards The transfer is initiated by a director coupled to such port. The director designates a selected one of the plurality of memory boards.

Abstract: A modified version of a switching/routing device commonly known as a crossbar switch which is optimized to switch and reroute very high speed synchronous data communication signals without interruptions and/or excessive transition time shifts.

Abstract: Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.

Abstract: An apparatus is described comprising: a switch for providing a plurality of communication channels between a plurality of nodes; and a crossbar switch communicatively coupled between the switch and the nodes for allocating one or more of a plurality of links to each of the nodes. Additionally, in a system including a switch for providing a plurality of communication channels between a plurality of nodes, a method is disclosed comprising the steps of: determining bandwidth requirements of each node in the system; and allocating links to the nodes based on the bandwidth requirements.

Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch.

Abstract: A processing system includes a processor, a main memory, a cache and a crossbar interface between the processor and the cache. In a multiprocessing system, a plurality of main memory address ranges can be mapped to a plurality of caches, and a plurality of caches can be mapped to a plurality of processors. Thus a significant degree of flexibility is provided in configuring a processing system.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors.

Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

Abstract: A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data input. A serial address and data enter the address input and the data input in parallel. A shift sequence is transmitted on the single shift input. The data flows before the shift sequence on the shift input is complete. The data is shifted through the crossbar switch using a clock that is generated on-chip using a clock recovery circuit. The decoder converts a binary address input into a serial address and includes an N-bit counter with a plurality of toggle flip-flops. The crossbar switch is implemented using superconductor digital electronics such as rapid single flux quantum (RSFQ) logic.

Abstract: A memory system and method of using same are provided. In one embodiment of the present invention, a novel memory operation protocol may be used to facilitate the execution of memory operations in the memory system. These memory operations may include atomic read-modify-write operations that may involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the prior art.

Abstract: A node controller (12) includes a processor interface unit (24) that receives an interrupt signal (50). The processor interface unit (24) includes a register (52) with a forward enable bit (54). In response to the forward enable bit (54) being set, the processor interface unit (24) generates a forward interrupt signal (56) for transfer to an input/output interface unit (26) of the node controller (12). The input/output interface unit (26) generates an interrupt request for transfer to a remote node controller. The input/output interface unit (26) includes an interrupt destination register (58) that includes an identity of a particular remote node controller and associated processor interface unit to which the interrupt request is to be transferred. The remote node controller having a processor attached thereto to handle the interrupt request.

Abstract: A system and method for dynamically configuring communication components in a computer system. The method may operate in a computer system including a plurality of buffers, a plurality of bus master engines and a bus interface unit. A plurality of communication medium interfaces may be coupled to the bus interface unit. Bus master engines, buffers and communication medium interfaces are dynamically configurable so that a set or subset of bus master engine(s), buffer(s) and communication medium interface(s) can be used in either a single or multiple peripheral bus function(s).

Abstract: A scalable crossbar switch is enabled by a single crossbar switch chip building block that incorporates input and output queuing circuits. The input and output queuing circuits can by selectively bypassed by voltages applied to configuration inputs. A circuit card used to construct a crossbar switch from the switch chips has the configuration inputs wired to the appropriate voltages so that when a switch chip is placed in a location the correct input or output queuing circuits are bypassed preserving the correct level of queuing and minimizing delays. The single crossbar switch chip building block also has line drivers after the output queuing circuits on all output lines and after the input queuing circuits on all input lines so off chip line driving is preserved on the appropriate lines whenever output queuing circuits are bypassed thus minimizing delays due to off chip loads.

Abstract: A parallel, point-to-point bus architecture for interconnecting two or more electronic components for data communication. The bus architecture includes a non-blocking crosspoint switch having a tap for interconnection to each component, a clock terminal for receiving a common clock signal and an interface for connecting each component to a tap of the crosspoint switch. Each interface includes parallel data terminals for coupling data signals between the crosspoint switch tap and the component, a clock terminal for coupling the common clock signal between the crosspoint switch tap and the component and a clock-to-data alignment system. The clock-to-data alignment system aligns the data signals coupled between the crosspoint switch tap and the component to the common clock signal. Simultaneous data communications at very high speeds can be achieved through use of the bus.

Abstract: A node controller (12) includes a processor interface unit (24), a crossbar unit (26), and a memory directory interface unit (22). Request and reply messages pass from the processor interface unit (24) to the crossbar unit (26) through a processor interface output queue (52). The processor interface unit (24) writes a request message into the processor interface output queue (52) using a processor interface clock to latch a write address from a write address latch (62) in a synchronizer (60). The write address is encoded by a Gray code counter (64) and latched by a first sync latch (66) and a second sync latch (18) using a core clock of the crossbar unit (30). The output of the second sync latch (68) provides one of the inputs to a read address latch (70) using the core clock of the crossbar unit (30).

Abstract: A memory alias adapter, coupled to a processor's memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus. As a result, it is transparent to the processor whether its memory access is to the local memory or to the shared memory.

Abstract: An apparatus and method for establishing construction information of an unmanaged Ethernet switch which is capable of readily replacing a memory according to a construction form of each option slot without opening or closing an outer casing. In the apparatus for establishing construction information of an unmanaged Ethernet switch, a first memory storing switch construction information, in the case where there is no option board mounted in an option slot, is positioned on a main board, and a second memory storing switch construction information, in the case where there is a option board in the option slot, is positioned on the option board, so that when there is no option board in the option slot, the first memory is automatically used, and when there is an option board in the option slot, the second memory is used.

Abstract: The invention provides a transmission apparatus, a recording apparatus, a transmission and reception apparatus, a transmission method, a recording method and a transmission and reception method by which data can be communicated between different apparatus over a single data bus in accordance with a first communication method wherein data can be transmitted and/or received periodically and a second communication method wherein data can be transmitted and/or received asynchronously.

Abstract: A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of que switch transistors, source to drain for data switched onto the bus, the queue switch transistors gated simultaneously by control lines from an on-board arbitrator controller following a preprogrammed arbitration scheme. Data is switched off the bus and hub by port adapter controllers connected to read amplifier receivers connected directly to the on-chip bus, the port adapter controllers enabled by the arbitrator controller following the same preprogrammed arbitration scheme. Ports may be serial or parallel, and may be adapted to special purposes, such as PCI and hub to hub connection for expansion.

Abstract: A method and apparatus for sharing memory in a multiprocessor computing system. More specifically, this invention provides a number of system buses with each bus being connected to a respective memory controller which controls a corresponding partition of the memory. Any one of the processors can use any one of the system buses to send real addresses to the connected memory controller which then converts the real addresses into physical addresses corresponding to the partition of memory that is controlled by the receiving memory controller. The processors can be dynamically assigned to different partitions of the memory by via a switching mechanism.

Abstract: A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel.

Abstract: A disk array controller is made up of multiple disk array control units for implementing the data read/write operation and each having channel IF units, disk IF units, cache memory units and shared memory units. The disk array controller further includes interconnections for interconnecting the shared memory units and interconnecting the cache memory units across the border of disk array control units. Thereby alleviating the deterioration of performance due to the data transfer between the disk array control units, when the multiple disk array control units are to be operated as a single disk array controller.

Abstract: Conventional routing switchers have employed a fixed architecture, i.e. the input and output connectors of the switching matrix are fixed in function. Prior art routing switchers use fixed matrix sizes. This invention uses a variable input/output architecture to enable multiple matrix sizes to be implemented in a single product. Switches are used to connect a subset of input and output connectors to either an input pin or an output pin. These switches allow users to select the number of input connectors and output connectors available for their particular application. The invention enables a single product to replace a range of routing switchers of different sizes. The user can also reconfigure the routing switcher size should application requirements change. This allows the user to configure the routing switcher matrix size to exactly meet the application requirements.

Abstract: A digital signal processing system has a control processor, a signal processor, and a plurality of memories. A signal processor carries out signal processing under control of the control processor. A connecting device connects each of the memories selectively to one of the control processor and the signal processor in response to an instruction from the control processor.

Abstract: A parallel, point-to-point bus architecture for interconnecting two or more electronic components for data communication. The bus architecture includes a non-blocking crosspoint switch having a tap for interconnection to each component, a clock terminal for receiving a common clock signal and an interface for connecting each component to a tap of the crosspoint switch. Each interface includes parallel data terminals for coupling data signals between the crosspoint switch tap and the component, a clock terminal for coupling the common clock signal between the crosspoint switch tap and the component and a clock-to-data alignment system. The clock-to-data alignment system aligns the data signals coupled between the crosspoint switch tap and the component to the common clock signal. Simultaneous data communications at very high speeds can be achieved through use of the bus.

Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

Abstract: A disk storage system containing a storage device having a record medium for holding the data, a plurality of storage sub-systems having a controller for controlling the storage device, a first interface node coupled to a computer using the data stored in the plurality of storage sub-systems, a plurality of second interface nodes connected to any or one of the storage sub-systems, a switching means connecting to a first interface node and a plurality of second interface nodes to perform frame transfer between a first interface node and a plurality of second interface nodes based on node address information added to the frame. The first interface node has a configuration table to store structural information for the memory storage system and in response to the frame sent from the computer, analyzes the applicable frame, converts information relating to the transfer destination of that frame based on structural information held in the configuration table, and transfers that frame to the switching means.

Abstract: A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus connections controlled by an integrated distributed switch (IDS) controller. The IDS controller is placed, during chip design, in the upper layer metals of the processor chip. When the data processing system is a multi-chip multiprocessor data processing system, the IDS controller operates to provide a pseudo switching effect whereby the processor is directly connected to each external component. The IDS controller permits the processor to have greater communication bandwidth and reduced latencies with the external components. It also allows for a connection to distributed external components such as memory and I/O, etc. with overall reduced system components.

Abstract: A method for communicating from a source port (i) to a destination port (j) is employed within a switching system that has m ports, each of the ports being coupled to a local area network via a Hub. The connectivity between the inputs and outputs of the m ports forms a matrix of cross points having m rows and m columns. Each port has a transmit line being coupled to a row of the matrix and a receive line being coupled to a column of the matrix. A transmission operation from the source port (i) to the destination port (j) involves a first control circuit for unilaterally connecting the port (i) to the port (j) and a second control circuit for unilaterally connecting the port (i) to the port (i). The method comprises a first step of sending address information from the port (i) to a third control circuit.

Abstract: A method of transferring data in a processing system comprising a shared memory for storing data blocks, a plurality of processors, at least one of the processors having a cache memory for the data blocks, a plurality of data buses to each one at least one processor is connected, cross-bar means for selectively connecting the data buses and the shared memory therebetween; the method comprises the steps of requesting the reading of a data block from the shared memory by a requesting processor, if the requested data block is present in modified form in the cache memory of an intervening processor, requesting an access to the corresponding data bus by the intervening processor, granting the access to the intervening processor, granting an access to any other data bus available to the cross-bar means, logically connecting the data bus corresponding to the intervening processor with the other data buses available, and sending the modified data block onto the data bus corresponding to the intervening processor and

Abstract: A distributed shared memory multi-processor system includes a System Control Unit (SCU) which is made up of a system control unit address section (SCUA) and system control unit data sections (SCUDs). The SCU is scalable by dividing the control and data flow functions of the SCU, and then parallelizing the data path. This allows the number of processors in the system to be increased or higher performance processors to be added by increasing the number of SCUDs and reprogramming crossbar switches incorporated in the SCUA and SCUDs. This results in the overall increase of the multi-processor system performance.

Abstract: A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.

Abstract: A switching system (1) connects with a host computer (6) via a GPIB bus (5). A controller (3) in a chassis (2) slot transmits control signals to up to twelve switch modules (4). A passive backplane (20) is used to address the modules (4) according to voltage levels sensed on pins (A15-A18) in the connectors. The controller (3) uses the backplane to provide a 16-bit data bus (21), a module address bus (22), a register address bus (23), a control bus (24), an auxiliary bus (24) and a power supply bus (25).

Abstract: A method and system for switching signals over conductors is disclosed. The method and system comprises a plurality of encoders for receiving signals from a plurality of sources. The system further comprises a crosspoint switching matrix means for receiving encoded signals from the plurality of encoders and for providing decoded signals to a plurality of receivers. The crosspoint switching matrix means in a preferred embodiment includes a control system for controlling multiple remote receivers.

Abstract: The present invention enables to obtain a data transfer at a high rate, at a reasonable cost, and with a high reliability.