Abstract: Consumer threads can assist in performing progressive chunking for a data queue. For example, a consumer thread can determine a current-chunk identifier indicating a current memory chunk of an unbounded queue, where the current memory chunk is associated with a producer thread that is different from the consumer thread. The consumer thread can determine a target-chunk identifier indicating a target memory chunk to which the producer thread is to write a data item. In response to determining that the target-chunk identifier is greater than the current-chunk identifier, the consumer thread can append a new memory chunk to the unbounded queue for use as the target memory chunk by the producer thread.

Abstract: A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.

Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals each having a first voltage range to the first line and the second line in a first mode, and signals each having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The receiver includes a low-power driver which receives signals through the first line and the second line in an operating state of the first mode, and stops an operation thereof in the second mode, and a high-speed driver which receives signals through the first line and the second line in the second mode, and stops an operation thereof in the first mode.

Abstract: Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for force provisioning virtual objects in degraded stretched clusters. A request to provision a virtual object by a stretched cluster according to a storage policy specified as part of the request can be received by a software defined data center (SDDC). The cluster can include a plurality of sites. An insufficiency of storage policy resources to satisfy the storage policy specified for the virtual object can be determined. The virtual object can be force provisioned responsive to determining storage policy resources sufficient to satisfy the storage policy at one of the plurality of sites.

Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.

Abstract: A universal serial bus (USB) hub with a multi-mode transmission physical layer and method thereof are provided. The hub includes a control unit and a hub controller. The hub controller is electrically connected to an upstream connection port, downstream port and the control unit for controlling a plurality of transmission modes of a differential signal to mitigate an issue of signal decay by the multi-mode transmission physical layer.

Abstract: A data storage chassis includes a plurality of data storage cartridges, and printed circuit board assembly (PCBA) electronics selectively connectable to one or more of the plurality of data storage cartridges. The data storage chassis also includes a wireless interface controller communicatively coupled to the PCBA electronics. The wireless interface controller facilitates wireless communication of data between the data storage chassis and a host using at least one frequency in a range of frequencies including fifth-generation (5G), millimeter, and sub-millimeter frequency ranges.

Abstract: An LCS networking device multi-host primary circuit board system includes a primary circuit board having a host processing system that provides an operating system for an LCS. A networking device connector on the circuit board is configured to connect to a networking device that performs networking operation(s) for the LCS, with the networking device connector also coupled via the circuit board to the host processing system to provide a first host coupling that is used by the networking device to access the host processing system. A first orchestrator device connector on the circuit board is configured to cable to an orchestrator device including an orchestrator processing system that performs orchestration operations for the LCS, with the first orchestrator device connector also coupled via the circuit board to the networking device connector to provide a second host coupling that is used by the networking device to access the orchestrator processing system.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

Abstract: Disclosed are various approaches for exposing peripheral component interconnect express (PCIe) configuration space implementations as Enhanced Configuration Access Mechanism (ECAM)-compatible. In some examples, a bridge device is identified on a segment corresponding to a root complex of a computing device. An endpoint device is connected to a bus downstream from the bridge device. A synthetic segment identifier is assigned to the bus once the endpoint device is identified as connected to the bus. Synthetic address data is generated for the endpoint device. The synthetic address data includes the synthetic segment identifier for the bus and sets a bus identifier of the bus to zero regardless of a hierarchical position of the bus in a standard peripheral component interconnect express (PCIe) bus hierarchy.

Abstract: A (controller area network) CAN filter combining method and a CNA controller are provided. The CAN filter includes a special filter and one or more common filters. The method includes: initializing a mask code and at least two filter codes of the special filter, acquiring a first total number of the filter codes in the special filter and a second total number of the common filters, acquiring mask codes and filter codes of the common filters, and adjusting the mask code and the filter codes of the special filter on the basis of the first total number, the second total number, and the mask codes and the filtering codes of all of the common filters. The method reduces the load of a processor, and prevents the CAN controller from processing a large amount of irrelevant data, thereby accelerating communications.

Abstract: The disclosure provides an approach for virtual computing instance (VCI) migration. Embodiments include scanning logical segments associated with a customer gateway to identify network addresses associated with the logical segments. Embodiments include determining one or more recommended supernets based on the network addresses associated with the logical segments. Embodiments include providing output to a user based on the one or more recommended supernets. Embodiments include based on the output, receiving input from the user configuring an aggregation supernet for the customer gateway. Embodiments include advertising the aggregation supernet to one or more endpoints separate from the customer gateway.

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Provided are systems, methods, and apparatuses for latency-aware edge computing to optimize network traffic. A method can include: determining network parameters associated with a network architecture, the network architecture comprising a data center and an edge data center; determining, using the network parameters, a first programmatically expected latency associated with the data center and a second programmatically expected latency associated with the edge data center; and determining, based at least in part on a difference between the first programmatically expected latency or the second programmatically expected latency, a distribution of a workload to be routed between the data center and the edge data center.

Abstract: An end-to-end telemetry system for a Remote Direct Memory Access (RDMA) communication network having multiple end-servers. The system includes an RDMA tracer for each end-server, one or more programmable data planes, and a telemetry collector. Each RDMA tracer extracts host-level telemetry information for one or more RDMA sessions associated with the corresponding end-server. Each programmable data plane extracts network-level telemetry information for one or more RDMA sessions associated with the programmable data plane. The telemetry collector (i) receives the host-level telemetry information from the RDMA tracers and the network-level telemetry information from the one or more programmable data planes and (ii) generates telemetry reports based on the host-level and network-level telemetry information. In some implementations, the system enables real-time monitoring of RDMA traffic at the RDMA protocol level granularity across all RDMA-enabled workloads for different use cases.

Abstract: An input system includes a first input device and a second input device. Each of the first input device and the second input device includes a main body, a first connecting port, at least two second connecting ports, a power switching circuit and a control unit. When the first connecting port of the first input device is connected with an external power source, the power switching circuit of the first input device receives a first voltage from the external power source. When one of the second connecting ports of the first input device is connected with one of the second connecting ports of the second input device, the first voltage is converted into a second voltage by the power switching circuit of the first input device and the second voltage is transmitted to the second input device.

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

Abstract: Systems and techniques for automated transfer of peripheral device operations are described herein. In an example, a system may adapted so that, while a first device of a first type and a second device of the first type are simultaneously connected to a client device, the first device, rather than the second device, is used as an active device of the first type for at least one application, the first and second devices being peripheral devices. The system may be further adapted so that, while both the first and second devices remain connected to the client device, a switch from the first device to the second device by a user is determined, and, based on the switch from the first device to the second device, the second device, rather than the first device, is used as the active device of the first type for the at least one application.

Abstract: A host can include a programmable network interface card (NIC) or “Smart NIC” which accesses host-local drives hidden from a host processor. One configuration can include a switch with a one logical partition including the NIC as a root complex (RC) and the local drives as end points (EPs), and with another logical partition including the host processor as an RC and the NIC as an EP. A second configuration can include the NIC and switch directly connected to the host processor with an access control component (ACC) configured on switch ports connected to the local drives. A third configuration can include the NIC and local drives directly connected to the host processor with the ACC configured on host processor ports connected to the local drives. The NIC can use a multi-layer driver to communicate with the ACC and local drives hidden behind the ACC.

Abstract: Disclosed are a method, a device and a system for data communication control. In the method for data communication control, data sent from a first communication device is received by a data forwarding device, where the data is transmitted through at least two types of physical interfaces in sequence. The data is then forwarded by the data forwarding device to a second communication device that is preconfigured. During the process of sending the data by the first communication device, the data is physically isolated by at least two types of physical interfaces, and then forwarded to the second communication device that is preconfigured. Even if the first communication device is illegally invaded by outsiders, the outsiders only know the IP address of the first communication device but fail to know the IP address of the destination of the physically isolated data.

Abstract: A communication control device for a subscriber station of a serial bus system. The communication control device has a communication control module for generating a transmitted signal for controlling a communication of the subscriber station with at least one other subscriber station of the bus system, in which bus system at least a first communication phase and a second communication phase are used for exchanging messages between subscriber stations of the bus system, a first terminal for transmitting, in an operating mode of the first communication phase, the transmitted signal to a transmitting/receiving device, a second terminal for receiving, in the operating mode of the first communication phase, a digital received signal from the transmitting/receiving device, and an operating mode switching module for switching the transmission direction of the first and the second terminal in the second communication phase to the same direction for differential signal transmission.

Abstract: A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

Abstract: A display system and a display device are provided. The display system includes a host device, a display device and an input device. The display device includes a display controller, a display panel and a USB hub. The display controller processes an image signal provided by the host device with a first processing mode and displays the processed image signal on the display panel. The USB hub is coupled to the host device. The input device is coupled to the USB hub. The input device forms a first signal input path with the host device via the USB hub and a second signal input path with the display controller via a signal line. The input device transmits the control signal via the signal line to cause the display controller to process the image signal with a second processing mode and display the processed image signal on the display panel.

Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

Abstract: An information handling system includes a secondary baseboard management controller that may transmit a first set of data via an external interface, and transmit a second set of data via an internal interface. A primary baseboard management controller includes a data traffic manager that may transmit a first signal for the current data to be transmitted if the current data is of the first set of data, or transmit a second signal if the current data is of the second set of data.

Abstract: In some embodiments, a system for communicating USB information via an extension medium is provided. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device is communicatively coupled to a host device via a USB-compliant connection. The DFP device is communicatively coupled to at least one USB device via a USB-compliant connection and communicatively coupled to the UFP device via a non-USB extension medium. The DFP device is configured to receive, from the UFP device, an incoming request packet addressed to a first USB endpoint provided by a USB device; and hold transmission of an outgoing request packet based on the incoming request packet to the USB device in response to determining that a ping response packet has not yet been received from the first USB endpoint.

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

Abstract: There is provided a communication apparatus comprising a connector that includes a plurality of signal lines and connects to an external recording device. The control unit performs control to determine whether a second signal has been input before a predetermined time period elapses since a first signal was output to the external recording device, the second signal indicating that the external recording device is compatible with a second transfer mode. In a case where it is determined that the second signal has been input, the control unit performs control to perform communication in the second transfer mode.

Abstract: System and method for supporting configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment. A mapping table in DRAM can be provided through the use of a software based SMA that implements the mapping table. With this mapping table, it is possible to provide a legacy compliant view of a bit map based P_Key table. Such a legacy compliant view can be called a virtual P_Key table, or a configurable legacy P_Key table abstraction.

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Abstract: According to examples, an apparatus may include a processor that may access an assignment of a component connected to a downstream USB port, from among a plurality of downstream USB ports that are downstream of a display device, to a first physical host device from among a plurality of physical host devices connected to the display device via respective upstream USB ports. The apparatus may bind, based on the assignment, the downstream USB port to a first upstream USB port that connects the first physical host device to the display device. The binding may cause the component to be coupled to the first physical host device. The apparatus facilitates assignment of individual components connected to downstream USB ports to one of a plurality of upstream USB ports.

Abstract: A method of managing inter-branch communication is a network, including generating an end-to-end path, wherein the end-to-end path starts in a first computing device in a first branch and ends at a second computing device in a second branch, wherein the end-to-end path is generated using a plurality of flow records and a plurality of path records and the end-to-end path includes a wide area network (WAN) segment, and issuing, based on the generating, a notification to a network administrator, wherein the notification specifies the end-to-end path and a latency associated with at least one segment in the end-to-end path.

Abstract: This invention provides a generalized electronic computer architecture with multiple cores, memory distributed amongst the cores (a core-local memory). This arrangement provides predictable, low-latency memory response time, as well as a flexible, code-supplied flow of memory from one specific operation to another (using an operation graph). In one instantiation, the operation graph consists of a set of math operations, each accompanied by an ordered list of one or more input addresses. Input addresses may be specific addresses in memory, references to other math operations in the graph, or references to the next item in a particular data stream, where data streams are iterators through a continuous block of memory. The arrangement can also be packaged as a PCIe daughter card, which can be selectively plugged into a host server/PC constructed/organized according to traditional von Neumann architecture.

Abstract: The present disclosure describes example service takeover methods, storage devices, and service takeover apparatuses. In one example method, when a communication fault occurs between two storage devices in a storage system, the two storage devices respectively obtain running statuses of the two storage devices. A running status can reflect current usage of one or more system resources of a particular storage device. Then, a delay duration is determined according to the running statuses, where the delay duration is a duration for which the storage device waits before sending an arbitration request to a quorum server. The two storage devices respectively send, after the delay duration, arbitration requests to the quorum server to request to take over a service. The quorum server then can select a storage device in a relatively better running status to take over a host service.

Abstract: A method includes monitoring, by a processing device, error characteristics of a particular memory component among a plurality of memory components of a memory sub-system and detecting, by the processing device and based on the monitored error characteristics, an error characteristic associated with the particular memory component that exhibits a value that is greater than or equal to a threshold error characteristic value. The method can further include causing, by the processing device, a counter coupled to the plurality of memory components to be updated in response to the detection that the particular memory component exhibits the value of the error characteristic that is greater than or equal to the threshold error characteristic value.

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

Abstract: A method may include receiving, by a privileged component executed by a processing device, bytecode of a packet processing component from an unprivileged component executed by the processing device, analyzing, by the privileged component, the bytecode of the packet processing component to identify whether the bytecode comprises a first command that returns a redirect, analyzing, by the privileged component, the bytecode of the packet processing component to identify whether the bytecode comprises a second command that returns a runtime computed value, and responsive to determining that the bytecode comprises the first command or the second command, setting a redirect flag maintained by the privileged component.

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

Abstract: Systems and methods for InfiniBand fabric optimizations to minimize SA access and startup failover times. A system can comprise one or more microprocessors, a first subnet, the first subnet comprising a plurality of switches, a plurality of host channel adapters, a plurality of hosts, and a subnet manager, the subnet manager running on one of the one or more switches and the plurality of host channel adapters. The subnet manager can be configured to determine that the plurality of hosts and the plurality of switches support a same set of capabilities. On such determination, the subnet manager can configure an SMA flag, the flag indicating that a condition can be set for each of the host channel adapter ports.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

Abstract: Systems and methods for payment processing on devices are provided. Such systems and methods enable payment processing to be completed with a peripheral device (such as a magnetic card reader) and a point of sales system, without the need for extensive developer integration. The system receives a payment charge amount from a point of sales system. The system also detects (or dynamically populates) peripheral devices that are used to capture account information. The peripheral device is a supported device type with an associated library, which includes data for properly interfacing with the peripheral device. The system provides the captured account data, a merchant ID and the amount of the charge to a payment management system. The system likewise receives a response (approve or decline) from the payment management system.

Abstract: A data processing method includes receiving, by an operating system of a device, a start instruction from an application in the device that includes an identifier of a socket connection, where the application is a latency-insensitive application, calling, by the operating system according to the start instruction, a monitoring system in the operating system to monitor buffering of data of the socket connection in a kernel buffer, where the data of the socket connection is from an underlying protocol stack, and generating, by the monitoring system, a data readable identifier when a time interval between a current moment and a start moment is greater than or equal to a timeout duration, where the start moment is when the operating system receives the start instruction, and the data readable identifier indicates that the data of the socket connection is readable by the application.

Abstract: A device can determine that a container is deployed in a front-end of a private network. The container can include a self-contained execution environment. The container can include an interface that is configured for directing network traffic between the front-end of the private network and one or more applications operating in a back-end of the private network. The device can configure an interface of the container for directing network traffic between an external network and the container. The device can configure a firewall of the front-end of the private network to permit routing of network traffic between the external network and the container. The device can advertise a route for directing network traffic between the external network and the container. The device can perform routing of network traffic between the one or more applications operating in the back-end of the private network and the external network using the container.

Abstract: A mechanism is provided to maximize utilization of internal memory for packet queuing in network devices, while providing an effective use of both internal and external memory to achieve high performance, high buffering scalability, and minimizing power utilization. Embodiments initially store packet data received by the network device in queues supported by an internal memory. If internal memory utilization crosses a predetermined threshold, a background task performs memory reclamation by determining those queued packets that should be targeted for transfer to an external memory. Those selected queued packets are transferred to external memory and the internal memory is freed. Once the internal memory consumption drops below a threshold, the reclamation task stops.

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.

Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.