Abstract: A data processing method, a data processing apparatus and a storage medium. The data processing method includes: receiving first data comprising at least one piece of second data (S101); transmitting the at least one piece of second data to at least one first data transmission channel (S102); sending, according to link cross information of a Printed Circuit Board (PCB), data of the at least one first data transmission channel to at least one corresponding data transmission link (S103); respectively receiving at least one piece of third data based on at least one port (S401); and sending, according to a channel identifier of request information, the at least one piece of third data to a corresponding data reconstitution link (S402).

Abstract: A first node obtains a transaction layer packet (TLP); and the first node sends the TLP to a second node. The TLP includes data, a type field, and an extension header, and the type field and the extension header are used to indicate a data type of the data and one or more first attribute parameters corresponding to the data type.

Abstract: Methods and apparatus for improved data movement operations through interconnect fabric. In one embodiment, Non-Transparent Bridge (NTB) technology used to perform data movement operations between a host and multiple peer devices using a DMA (direct memory access) engine and at least one descriptor ring having enhanced descriptor entries. In one implementation, descriptor ring entries include source and destination address information, address translation information, and fabric partition information. In one implementation, a DMA engine is configured directly access host memory and generate data packets using the descriptor entry information. In one embodiment, the descriptor ring is a virtual descriptor ring located on DMA hardware, host memory, or elsewhere in the NT fabric address space, and may be accessed by user processes.

Abstract: A method of managing inter-branch communication is a network, including generating an end-to-end path, wherein the end-to-end path starts in a first computing device in a first branch and ends at a second computing device in a second branch, wherein the end-to-end path is generated using a plurality of flow records and a plurality of path records and the end-to-end path includes a wide area network (WAN) segment, and issuing, based on the generating, a notification to a network administrator, wherein the notification specifies the end-to-end path and a latency associated with at least one segment in the end-to-end path.

Abstract: An electronic device may include at least one control unit and an interface or a group of peripheral devices. The group of peripheral devices may include a plurality of peripheral devices (e.g., an input module, a sound output module, a display module, an audio module, a haptic module, a sensor module, a camera module, a power management module, and a communication module). The electronic device includes a plurality of peripheral devices and at least one processor connected to the plurality of peripheral devices via a serial interface, wherein the at least one processor may be configured to control the electronic device to continuously transmit, via the serial interface, a single command frame including a single serial control command, and data frames to be delivered to at least two peripheral devices among the plurality of peripheral devices.

Abstract: A modular server chassis enclosure controller (EC) on-premises keyboard video and mouse module has an EC frame buffer memory and an EC virtual network computing (libvnc) client process. The libvnc fetches an EC frame buffer memory address, displays an on-screen display (OSD) screen to a user and accepts user selection of a blade server deployed in the modular server chassis from the OSD. The libvnc receives a virtual network computing (VNC) streaming session over transport layer security, from a VNC computing server process of the selected blade server. The libvnc determines whether the VNC server process has data to send and, if it does, reads graphics data from the virtual network computing server process and writes the graphics data from the VNC server to the EC frame buffer memory address. The graphics data is displayed on an on-premises monitor coupled to the modular server chassis from the EC frame buffer.

Abstract: A system and method for performing live firmware and configuration update. A method includes maintaining live operation of network nodes during an update, each of the network nodes including a disk that is divided into a plurality of partitions, a currently running application file is located in a first partition of the network node; and downloading an update file in a common partition of the disk of the network node to be updated. A method may include extracting the update file from the common partition to a second partition of the disc of the network nodes to be updated; and switching the live operation of the network nodes to operate from the currently running application file in the first partition to the update file in the second partition.

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

Abstract: A Peripheral Component Interconnect Express (PCIE) device, apparatus, and method with different PCIE bandwidths compatible in the same PCIE slot. The device includes a PCIE single board. A first core chip corresponding to a first PCIE XN device and a second core chip corresponding to a second PCIE XN device are arranged on the PCIE single board. An XN+XN gold finger is further arranged on a body of the PCIE single board. The XN+XN gold finger is formed by two XN gold fingers.

Abstract: A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to the allotted virtual queues and enables the return queue for arbitration. When the return queue is enabled for arbitration, the processor reads out the data written to the allocated virtual queues, processes the read out data, and provides the processed data to a processing pipeline.

Abstract: An electronic-device control system and an electronic-device control method are provided. The electronic-device control system includes an electronic device having multiple pogo pads acting as an interface and a control device performing at least one preset operation on the electronic device. The control device includes: a pogo-pin module, including multiple pogo pins corresponding to the pogo pads to form a one-to-one correspondence to be connected via contact or disconnected; and a signal transfer unit, receiving from an external computer a second specification signal converted from a first specification signal, and transmitting the second specification signal to the corresponding pogo pin among the multiple pogo pins. A special firmware communication interface is configured by adapting the electronic-device control system and the electronic-device control method to update or control the electronic device, protecting the electronic device from malicious updates.

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

Abstract: A data plane integrated circuit that includes interfacing units (IFUs), Datapath units (DPUs); and a network on chip (NoC). The DPUs are arranged in local sets of DPUs that are proximate to each other, each local set is configured to (a) store an instance of packet header processing control data structures and (b) independently perform local packet header processing and transmission scheduling.

Abstract: Provided is a modular multilevel converter and a method for synchronizing outputs of sub-modules of the converter. The modular multilevel converter includes sub-modules connected in parallel, and each sub-module generates an output. The modular multilevel converter also includes a controller that is communicatively coupled to the sub-modules. The controller controls a flow of one or more synchronizing signals between the plurality of sub-modules, such that each sub-module receives the synchronizing signals in opposite directions simultaneously, thereby controlling a synchronization of the outputs generated by the sub-modules.

Abstract: A storage engine has a pair of compute nodes, each compute node having a separate PCIe root complex and attached memory. The PCIe root complexes are interconnected by multiple Non-Transparent Bridge (NTB) links. The NTB resources are unequally shared, such that host IO devices are required to use a first subset of the NTB links to implement memory access operations on the memory of the peer compute node, whereas storage software memory access operations are able to be implemented on all of the NTB links. A NTB link arbitration system arbitrates usage of the first and second subsets of NTB links by the storage software, to distribute subsets of the storage software memory access operations on peer memory to the first and second subsets of NTB links, while causing all host IO device memory access operations on peer memory to be implemented on the first set of NTB links.

Abstract: Composable computing architectures with an interconnection fabric to provide high availability and fault tolerance are described. An interconnection fabric routes packets between compute resources, memory resources, and input/output (I/O) resources. A fabric manager is coupled with the interconnection fabric to receive an I/O or memory requirement for a compute workload for a host device, and to map individual I/O or memory resources from the plurality of I/O resources to individual compute resources from the plurality of compute resource and to dynamically map individual I/O resources from the plurality of I/O resources based on received resource requests.

Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes executable instructions for causing the one hardware device to be inhibited from functioning with the IHS when at least one of the hardware devices is powered on, and performing an authentication procedure with that hardware device. After that hardware device has been successfully authenticated, the instructions then enable the one hardware device to function with the IHS.

Abstract: A device configured to receive a set of bits for a first package from a previous device of a plurality of devices connected in a daisy chain configuration, the set of bits for the first package including a first priority value and if the device does not have a second package for output to a destination device of the plurality of devices, output the set of bits for the first package to a subsequent device of the plurality of devices. When the device has the second package for output to the destination device of the plurality of devices, the device is configured to determine whether the second priority value is higher than the first priority value and if the second priority value is higher than the first priority value output a set of bits for the second package to the subsequent device of the plurality of devices.

Abstract: An in-wall power adapter adapted to receive a control attachment is described. The in-wall power adapter may comprise a first plurality of contact elements adapted to receive wires of a junction box, the first plurality of contact elements comprising a first contact element adapted to receive a power signal, a second contact element adapted to receive a neutral signal, and a third contact element adapted to provide the power signal to a load; a recess adapted to receive a control attachment; and a switch comprising a switch element having a first terminal adapted to receive the power signal and a second terminal adapted to provide the power signal to a load, and an actuator element coupled to the switch element to control the switch element; wherein the in-wall power adapter is adapted to control an application of the power signal received at the first contact element to a load in response to an actuation of the switch actuator.

Abstract: In some examples, a method includes receiving a transaction at an inbound port, the transaction including a requester identification (ID), a traffic class, and a peripheral component interconnect express (PCIe) address. The method includes providing an attribute based at least in part on the traffic class. The method includes providing a context ID based on the attribute and the requester ID. The method includes accessing a region of memory responsive to the transaction, the region of memory corresponding to the context ID.

Abstract: Consumer threads can assist in performing progressive chunking for a data queue. For example, a consumer thread can determine a current-chunk identifier indicating a current memory chunk of an unbounded queue, where the current memory chunk is associated with a producer thread that is different from the consumer thread. The consumer thread can determine a target-chunk identifier indicating a target memory chunk to which the producer thread is to write a data item. In response to determining that the target-chunk identifier is greater than the current-chunk identifier, the consumer thread can append a new memory chunk to the unbounded queue for use as the target memory chunk by the producer thread.

Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals each having a first voltage range to the first line and the second line in a first mode, and signals each having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The receiver includes a low-power driver which receives signals through the first line and the second line in an operating state of the first mode, and stops an operation thereof in the second mode, and a high-speed driver which receives signals through the first line and the second line in the second mode, and stops an operation thereof in the first mode.

Abstract: A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.

Abstract: Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for force provisioning virtual objects in degraded stretched clusters. A request to provision a virtual object by a stretched cluster according to a storage policy specified as part of the request can be received by a software defined data center (SDDC). The cluster can include a plurality of sites. An insufficiency of storage policy resources to satisfy the storage policy specified for the virtual object can be determined. The virtual object can be force provisioned responsive to determining storage policy resources sufficient to satisfy the storage policy at one of the plurality of sites.

Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.

Abstract: A universal serial bus (USB) hub with a multi-mode transmission physical layer and method thereof are provided. The hub includes a control unit and a hub controller. The hub controller is electrically connected to an upstream connection port, downstream port and the control unit for controlling a plurality of transmission modes of a differential signal to mitigate an issue of signal decay by the multi-mode transmission physical layer.

Abstract: A data storage chassis includes a plurality of data storage cartridges, and printed circuit board assembly (PCBA) electronics selectively connectable to one or more of the plurality of data storage cartridges. The data storage chassis also includes a wireless interface controller communicatively coupled to the PCBA electronics. The wireless interface controller facilitates wireless communication of data between the data storage chassis and a host using at least one frequency in a range of frequencies including fifth-generation (5G), millimeter, and sub-millimeter frequency ranges.

Abstract: An LCS networking device multi-host primary circuit board system includes a primary circuit board having a host processing system that provides an operating system for an LCS. A networking device connector on the circuit board is configured to connect to a networking device that performs networking operation(s) for the LCS, with the networking device connector also coupled via the circuit board to the host processing system to provide a first host coupling that is used by the networking device to access the host processing system. A first orchestrator device connector on the circuit board is configured to cable to an orchestrator device including an orchestrator processing system that performs orchestration operations for the LCS, with the first orchestrator device connector also coupled via the circuit board to the networking device connector to provide a second host coupling that is used by the networking device to access the orchestrator processing system.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

Abstract: Disclosed are various approaches for exposing peripheral component interconnect express (PCIe) configuration space implementations as Enhanced Configuration Access Mechanism (ECAM)-compatible. In some examples, a bridge device is identified on a segment corresponding to a root complex of a computing device. An endpoint device is connected to a bus downstream from the bridge device. A synthetic segment identifier is assigned to the bus once the endpoint device is identified as connected to the bus. Synthetic address data is generated for the endpoint device. The synthetic address data includes the synthetic segment identifier for the bus and sets a bus identifier of the bus to zero regardless of a hierarchical position of the bus in a standard peripheral component interconnect express (PCIe) bus hierarchy.

Abstract: A (controller area network) CAN filter combining method and a CNA controller are provided. The CAN filter includes a special filter and one or more common filters. The method includes: initializing a mask code and at least two filter codes of the special filter, acquiring a first total number of the filter codes in the special filter and a second total number of the common filters, acquiring mask codes and filter codes of the common filters, and adjusting the mask code and the filter codes of the special filter on the basis of the first total number, the second total number, and the mask codes and the filtering codes of all of the common filters. The method reduces the load of a processor, and prevents the CAN controller from processing a large amount of irrelevant data, thereby accelerating communications.

Abstract: The disclosure provides an approach for virtual computing instance (VCI) migration. Embodiments include scanning logical segments associated with a customer gateway to identify network addresses associated with the logical segments. Embodiments include determining one or more recommended supernets based on the network addresses associated with the logical segments. Embodiments include providing output to a user based on the one or more recommended supernets. Embodiments include based on the output, receiving input from the user configuring an aggregation supernet for the customer gateway. Embodiments include advertising the aggregation supernet to one or more endpoints separate from the customer gateway.

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Provided are systems, methods, and apparatuses for latency-aware edge computing to optimize network traffic. A method can include: determining network parameters associated with a network architecture, the network architecture comprising a data center and an edge data center; determining, using the network parameters, a first programmatically expected latency associated with the data center and a second programmatically expected latency associated with the edge data center; and determining, based at least in part on a difference between the first programmatically expected latency or the second programmatically expected latency, a distribution of a workload to be routed between the data center and the edge data center.

Abstract: An end-to-end telemetry system for a Remote Direct Memory Access (RDMA) communication network having multiple end-servers. The system includes an RDMA tracer for each end-server, one or more programmable data planes, and a telemetry collector. Each RDMA tracer extracts host-level telemetry information for one or more RDMA sessions associated with the corresponding end-server. Each programmable data plane extracts network-level telemetry information for one or more RDMA sessions associated with the programmable data plane. The telemetry collector (i) receives the host-level telemetry information from the RDMA tracers and the network-level telemetry information from the one or more programmable data planes and (ii) generates telemetry reports based on the host-level and network-level telemetry information. In some implementations, the system enables real-time monitoring of RDMA traffic at the RDMA protocol level granularity across all RDMA-enabled workloads for different use cases.

Abstract: An input system includes a first input device and a second input device. Each of the first input device and the second input device includes a main body, a first connecting port, at least two second connecting ports, a power switching circuit and a control unit. When the first connecting port of the first input device is connected with an external power source, the power switching circuit of the first input device receives a first voltage from the external power source. When one of the second connecting ports of the first input device is connected with one of the second connecting ports of the second input device, the first voltage is converted into a second voltage by the power switching circuit of the first input device and the second voltage is transmitted to the second input device.

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

Abstract: Systems and techniques for automated transfer of peripheral device operations are described herein. In an example, a system may adapted so that, while a first device of a first type and a second device of the first type are simultaneously connected to a client device, the first device, rather than the second device, is used as an active device of the first type for at least one application, the first and second devices being peripheral devices. The system may be further adapted so that, while both the first and second devices remain connected to the client device, a switch from the first device to the second device by a user is determined, and, based on the switch from the first device to the second device, the second device, rather than the first device, is used as the active device of the first type for the at least one application.

Abstract: A host can include a programmable network interface card (NIC) or “Smart NIC” which accesses host-local drives hidden from a host processor. One configuration can include a switch with a one logical partition including the NIC as a root complex (RC) and the local drives as end points (EPs), and with another logical partition including the host processor as an RC and the NIC as an EP. A second configuration can include the NIC and switch directly connected to the host processor with an access control component (ACC) configured on switch ports connected to the local drives. A third configuration can include the NIC and local drives directly connected to the host processor with the ACC configured on host processor ports connected to the local drives. The NIC can use a multi-layer driver to communicate with the ACC and local drives hidden behind the ACC.

Abstract: Disclosed are a method, a device and a system for data communication control. In the method for data communication control, data sent from a first communication device is received by a data forwarding device, where the data is transmitted through at least two types of physical interfaces in sequence. The data is then forwarded by the data forwarding device to a second communication device that is preconfigured. During the process of sending the data by the first communication device, the data is physically isolated by at least two types of physical interfaces, and then forwarded to the second communication device that is preconfigured. Even if the first communication device is illegally invaded by outsiders, the outsiders only know the IP address of the first communication device but fail to know the IP address of the destination of the physically isolated data.

Abstract: A communication control device for a subscriber station of a serial bus system. The communication control device has a communication control module for generating a transmitted signal for controlling a communication of the subscriber station with at least one other subscriber station of the bus system, in which bus system at least a first communication phase and a second communication phase are used for exchanging messages between subscriber stations of the bus system, a first terminal for transmitting, in an operating mode of the first communication phase, the transmitted signal to a transmitting/receiving device, a second terminal for receiving, in the operating mode of the first communication phase, a digital received signal from the transmitting/receiving device, and an operating mode switching module for switching the transmission direction of the first and the second terminal in the second communication phase to the same direction for differential signal transmission.

Abstract: A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

Abstract: A display system and a display device are provided. The display system includes a host device, a display device and an input device. The display device includes a display controller, a display panel and a USB hub. The display controller processes an image signal provided by the host device with a first processing mode and displays the processed image signal on the display panel. The USB hub is coupled to the host device. The input device is coupled to the USB hub. The input device forms a first signal input path with the host device via the USB hub and a second signal input path with the display controller via a signal line. The input device transmits the control signal via the signal line to cause the display controller to process the image signal with a second processing mode and display the processed image signal on the display panel.

Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

Abstract: An information handling system includes a secondary baseboard management controller that may transmit a first set of data via an external interface, and transmit a second set of data via an internal interface. A primary baseboard management controller includes a data traffic manager that may transmit a first signal for the current data to be transmitted if the current data is of the first set of data, or transmit a second signal if the current data is of the second set of data.

Abstract: In some embodiments, a system for communicating USB information via an extension medium is provided. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device is communicatively coupled to a host device via a USB-compliant connection. The DFP device is communicatively coupled to at least one USB device via a USB-compliant connection and communicatively coupled to the UFP device via a non-USB extension medium. The DFP device is configured to receive, from the UFP device, an incoming request packet addressed to a first USB endpoint provided by a USB device; and hold transmission of an outgoing request packet based on the incoming request packet to the USB device in response to determining that a ping response packet has not yet been received from the first USB endpoint.

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

Abstract: There is provided a communication apparatus comprising a connector that includes a plurality of signal lines and connects to an external recording device. The control unit performs control to determine whether a second signal has been input before a predetermined time period elapses since a first signal was output to the external recording device, the second signal indicating that the external recording device is compatible with a second transfer mode. In a case where it is determined that the second signal has been input, the control unit performs control to perform communication in the second transfer mode.