Path Selecting Switch Patents (Class 710/316)
  • Patent number: 11328753
    Abstract: A semiconductor device includes a read/write control circuit, a core circuit, and a data conversion circuit. The read/write control circuit generates a read strobe signal and a read address from an internal address/command signal based on an internal read command during a self-write operation, generates a write strobe signal after the read strobe signal is generated, and generates a write address from the internal address/command signal. The core circuit is synchronized with the read strobe signal to output read data stored in a bank selected by the read address and is synchronized with the write strobe signal to store write data into the bank or another bank which is selected by the write address. The data conversion circuit changes a pattern of the read data to generate the write data.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventors: Min O Kim, Min Wook Oh, Yeong Han Jeong
  • Patent number: 11327796
    Abstract: A method for deploying a task includes deploying the task in the supercomputer; executing the task; at the end of the execution of the task, detecting at least one link which is not allocated to any task, and setting each detected link in an inactive state, wherein the link requires a power consumption less than the power consumption required by a link associated with at least one task.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 10, 2022
    Assignee: BULL SAS
    Inventor: Jean-Noël Quintin
  • Patent number: 11311800
    Abstract: A cloud gaming system includes a cloud storage system and a cloud compute system connected together through a PCIe switch and PCIe fabric. The PCIe switch is configured to map resources within the cloud storage system to a memory map of the cloud compute system. The PCIe switch is configured to map resources within the cloud compute system to a memory map of the cloud storage system. The PCIe fabric enables transfer of a data input/output command buffer generated by the cloud compute system to the cloud storage system by either a direct write or a direct read between the cloud compute system and the cloud storage system. The PCIe fabric enables transfer of data between the cloud storage system and the cloud compute system, as indicated by the command buffer, by either a direct write or a direct read between the cloud compute system and the cloud storage system.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 26, 2022
    Assignee: Sony Interactive Entertainment LLC
    Inventor: Roelof Roderick Colenbrander
  • Patent number: 11277335
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of input-output (IO) operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on the storage system. The processing device is further configured to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target, and to modify path selection in the host device to at least temporarily avoid selecting the one or more identified paths. The processing device illustratively comprises at least a portion of the host device.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinay G. Rao, Sanjib Mallick, Arieh Don
  • Patent number: 11270201
    Abstract: Embodiments described herein provide a system to configure distributed training of a neural network, the system comprising memory to store a library to facilitate data transmission during distributed training of the neural network; a network interface to enable transmission and receipt of configuration data associated with a set of worker nodes, the worker nodes configured to perform distributed training of the neural network; and a processor to execute instructions provided by the library, the instructions to cause the processor to create one or more groups of the worker nodes, the one or more groups of worker nodes to be created based on a communication pattern for messages to be transmitted between the worker nodes during distributed training of the neural network.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Srinivas Sridharan, Karthikeyan Vaidyanathan, Dipankar Das, Chandrasekaran Sakthivel, Mikhail E. Smorkalov
  • Patent number: 11190568
    Abstract: Various implementations include devices and approaches for managing multimedia communications. In one aspect, a computer-implemented method of controlling a device connection includes: receiving audio data and video data from an input device connected with a peripheral bus input port; converting the audio data for transmission over an audio over internet protocol (IP) connection or a balun connection and converting the video data for transmission over a video over internet protocol (IP) connection or the balun connection; and transmitting the converted audio data and the converted video data for decoding and output to at least one output device via a multimedia audiovisual interface output port, where the peripheral bus input port is configured to support bidirectional audio and bidirectional video exchange with the input device and bidirectional exchange of IP-based control signals or balun-based control signals with the input device.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: November 30, 2021
    Assignee: Bose Corporation
    Inventors: Marc Brandon Happes, Marco Maurizio Panzanella, Darryl John Bryans
  • Patent number: 11182309
    Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 23, 2021
    Assignee: NVIDIA Corporation
    Inventors: John Feehrer, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
  • Patent number: 11176071
    Abstract: A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 16, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: David G. Wright, Shopitham Ram
  • Patent number: 11163591
    Abstract: A power management method and device for a multi-operating system (OS) electronic apparatus can employ a host OS including first power attribute files, each including a power pack name and a power attribute name. A guest OS includes second power attribute files, each including a pack name code and an attribute name code corresponding respectively to a power pack name and a power attribute name in each first power attribute file. When any second power attribute file is called, a pack name code and an attribute name code corresponding thereto are decoded in the guest OS to obtain a called power pack name and a called power attribute name, which are then sent to the host OS. The host OS then provides the corresponding first power attribute file to the guest OS. The invalidity risk of any power attribute file in the multi-OS electronic apparatus can therefore be reduced.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 2, 2021
    Assignee: CLOUDMINDS (SHENZHEN) ROBOTICS SYSTEMS CO., LTD.
    Inventor: Yangang Li
  • Patent number: 11165962
    Abstract: A computer vision system includes a camera that captures a plurality of image frames in a target field. A user interface is coupled to the camera. The user interface is configured to perform accelerated parallel computations in real-time on the plurality of image frames acquired by the camera. The system provides an accountability measurement of impact of architecture and design work.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 2, 2021
    Assignee: RoundhouseOne Inc.
    Inventors: Mark Raymond Miller, Archana Ramachandran, Christopher C. Anderson
  • Patent number: 11159962
    Abstract: The present invention is directed to optimization and failure detection of a wireless base station network. Based on an RF link attenuation measurement, e.g., a Received Signal Strength Indication (RSSI) measurement, a server determines an optimal transmission sequence. For each base station of the optimal transmission sequence, a predecessor and a successor are designated. Each base station of the sequence generates a packet. The most distant base station (relative to the server) transmits its packet to its successor. Each base station of the sequence (in turn) receives the packet from its predecessor, combines the received packet with its own generated packet, transmits the combined packet to its successor, and so on until the combined packet is relayed to a super base station at the end of the sequence. The super base station transmits the packet to the server. Based on the packet size, the server can ascertain which base station (if any) failed.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: October 26, 2021
    Assignee: TRAKPOINT SOLUTIONS, INC.
    Inventors: Christopher Williams, Jon Siann
  • Patent number: 11144215
    Abstract: A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 12, 2021
    Assignee: Beijing Horizon Robotics Technology Research and Development Co., Ltd.
    Inventors: Honghe Tan, Liang Chen
  • Patent number: 11106607
    Abstract: A NUMA-aware storage system including a first processing subsystem coupled to a first memory subsystem, and a second processing subsystem coupled to a second memory subsystem. A first NTB subsystem connected to the first processing subsystem presents itself as a first storage device, identifies first data transfer operations directed to the first memory subsystem and, in response, claims those first data transfer operations and provides them directly to the first processing subsystem. A second NTB subsystem connected to the second processing subsystem presents itself as a second storage device, identifies second data transfer operations directed to the second memory subsystem and, in response, claims those second data transfer operations and provides them directly to the second processing subsystem. A storage controller system receives a command from either the first or second processing subsystem via the first or second NTB subsystem and, in response, transmits that command to a storage system.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 31, 2021
    Assignee: Dell Products L.P.
    Inventors: Gary Benedict Kotzur, William Emmett Lynn, Kevin Thomas Marks, Chandrashekar Nelogal, James Peter Giannoules, Austin Patrick Bolen
  • Patent number: 11108583
    Abstract: Methods and systems for collaborative learning and enabling skills among smart devices within a closed social network group are disclosed. A method includes: receiving, by a computing device from a first smart device, a request for steps to perform an activity; determining, by the computing device, the steps to perform the activity using a knowledge corpus; translating, by the computing device, the steps into a format that is compatible with the first smart device; and sending, by the computing device, the translated steps to the first smart device.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shubhadip Ray, Sarbajit K. Rakshit, Craig M. Trim, Garfield Vaughn
  • Patent number: 11100963
    Abstract: A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 24, 2021
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11093436
    Abstract: An arithmetic processing device includes arithmetic processing units configured to perform arithmetic processing; first routers connected to the plurality of arithmetic processing units, respectively; first buses connecting the plurality of first routers in a ring shape; and second buses connecting between one of the plurality of first routers and any one of the other first routers excluding the first routers directly connected through the first buses.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: August 17, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Ishibashi, Tadatoshi Shindo
  • Patent number: 11089615
    Abstract: An operation method of a transmitting apparatus in a wireless communication system includes transmitting, to a receiving apparatus, reverse mapping flag information indicating a direction of mapping data symbols to one or more subcarriers included in a resource block allocated to the receiving apparatus; mapping the data symbols to the one or more subcarriers of the resource block based on the reverse mapping flag information; and transmitting the resource block to the receiving apparatus. According to the embodiments of the present disclosure, the amount of subcarrier phase shift noises due to an SFO occurring in proportion to synchronization impairment and subcarrier index can be reduced in a multi-carrier communication system, thereby increasing data retransmission efficiency.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 10, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Seung Jae Bahng
  • Patent number: 11068428
    Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Yonghui Tang, Huanzhang Huang, Douglas Edward Wente
  • Patent number: 11070478
    Abstract: A method for managing traffic of a plurality of packets in a plurality of packet flows transmitted using a time-slotted interface. The packet flows traverse a plurality of switches of a transport network according to an assigned path from a source node to a destination node. The method comprises determining an end-to-end latency of a plurality of packets traversing a current switch in packet flows and assigning priority values to the packets traversing the current switch, wherein a priority value of a packet depends on the determined end-to-end latency of said packets. The method further comprises allocating a time slot in an output interface of the current switch to the packet having the highest priority value among the packets competing for said time slot.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: July 20, 2021
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Fabio Cavaliere, Giulio Bottari, Stefano Stracca
  • Patent number: 10997106
    Abstract: Described are programmable IO devices installed on a host device and configured to execute instructions that cause the programmable IO device to perform operations to establish a virtual link between another programmable IO device installed on the host device and provide a data plane using the virtual link. These operations comprise: establishing the virtual link with the other programmable IO device installed on the host device, wherein the virtual link provides a communication channel between the programmable IO devices; providing the data plane by establishing, with the other programmable IO device via the virtual link, a data path associated with the data plane; receiving a packet in the data plane destined for the other programmable IO device; and forwarding the packet to the other programmable IO device via the virtual link.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 4, 2021
    Assignee: PENSANDO SYTEMS INC.
    Inventors: Bharat Bandaru, Pirabhu Raman, J. Bradley Smith
  • Patent number: 10979138
    Abstract: The present disclosure provides a protection group superposition switching method, a control apparatus, and an optical communication device. Multiple protection state machines are implemented by using a field programmable gate array (FPGA). Each protection state machine independently performs an automatic protection switching (APS) protocol operation for at least one protection group that is pre-associated with the protection state machine. At least one protection status table for recording a status of each protection group is updated according to a result of the APS protocol operation, and a cross-connection table for traffic cross-connection between communication units is updated according to the protection status table; the updated cross-connection table is configured into a cross-connection chip, so that the cross-connection chip performs traffic cross-connection according to the updated cross-connection table.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 13, 2021
    Assignee: SINO-TELECOM TECHNOLOGY CO., INC.
    Inventors: Lei Hou, Zhiyuan Wu, Hu Xie, Lin Li
  • Patent number: 10949374
    Abstract: The present disclosure provides a Type-C interface controlling circuit, a controlling method, and a mobile terminal, wherein the Type-C interface controlling circuit includes: a Type-C interface, a first transmission module, a second transmission module, a switching module, and a detection module. The first end of the detection module is connected to the Type-C interface for detecting a connection state of the Type-C interface, and the second end of the detection module is connected to the switching module, and the detection module controls a connection relationship between the first end of the switching module and the second end of the switching module according to the connection state.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 16, 2021
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Quanxi Yin
  • Patent number: 10949365
    Abstract: The invention relates to a software defined device interface system 10, a software defined device interface, gateway and a method of defining an interface for a device which uses a specific communication protocol for communication purposes. The system 10 includes a microprocessor/processing unit 12.1, 12.2 with a plurality of communication pins and software/firmware. The software/firmware is configured, based on a specific communication protocol which is used by a particular device 30.1-30.4 for communication purposes, to, in runtime, assign/select one or more of the communication pins to form a virtual port to which the particular device 30.1-30.4 can be connected, upon receiving a configuration instruction from a user to implement the specific communication protocol. The software/firmware is further configured to implement the specific communication protocol through the virtual port, to thereby allow for communication between the microprocessor/processing unit 12.1, 12.2 and the device 30.1-30.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 16, 2021
    Assignee: IOT.nxt BV
    Inventors: Gysbert Johannes Jacobs, Rudi Deodat Du Toit
  • Patent number: 10943102
    Abstract: A computer vision system includes a camera that captures a plurality of image frames in a target field. A user interface is coupled to the camera. The user interface is configured to perform accelerated parallel computations in real-time on the plurality of image frames acquired by the camera. The system detects and tracks animal wellness and habitat/intervention design.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: March 9, 2021
    Assignee: RoundhouseOne Inc.
    Inventors: Mark Raymond Miller, Archana Ramachandran, Christopher C. Anderson, Aaron Spafford
  • Patent number: 10936404
    Abstract: Technologies for error recovery in compressed data streams include a compute device configured to compress uncompressed data of an input stream to generate compressed data, perform a compression error check on the compressed data to verify integrity of the compressed data, and determine, as a result of the performed compression error check, whether the compressed data included a compression error. The compute device is further configured to transfer, in response to a determination that the performed compression error check indicated that the compressed data included the compression error, the uncompressed data into a destination buffer, and store an indication with the uncompressed data into the destination buffer, wherein the indication is usable to identify that the uncompressed data has been transferred into the destination buffer. Other embodiments are described herein.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Laurent Coquerel, Paul Hough
  • Patent number: 10922160
    Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Xin Chen
  • Patent number: 10915381
    Abstract: A method of facilitating communication to an embedded computer in a computational storage device via a host includes receiving a message for transmission to an embedded process running at the embedded computer, determining that a destination address of the message corresponds to the embedded computer within the computational storage device, in response to the determination, forwarding the message to a host relay process associated with the embedded computer, and encapsulating the message to generate a proprietary command for transmission to the computational storage device.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: February 9, 2021
    Assignee: NGD Systems, Inc.
    Inventors: Hermes Costa, Vladimir Alves
  • Patent number: 10915263
    Abstract: The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jeremiah J. Willcock, David L. Pinney
  • Patent number: 10901823
    Abstract: A system and method to balance computational loads across multiple computing systems, such as servers in a server cluster, is disclosed. The system includes a load balancer. Upon receiving a new computing request corresponding to an expected throughout, the load balancer identifies a computing system that is most likely to fail and sends the new computing request to a different computing system. The load balancer uses a mutational algorithm to identify potentially problematic throughputs for a given computing system in a given state. The mutational algorithm is used to determine latency-throughput curves that are fit to a data population that includes many diverse data points with relatively high slopes in a 2D latency-throughput space.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 26, 2021
    Assignee: Accenture Global Solutions Limited
    Inventors: Yashaswi Poorlupadi, Veera Venkatasatyanagaganesh Metla, Chandrashekar Sadashivappa Gunjiganur, Dhireshwar Mishra, Sudhir Kudva
  • Patent number: 10901925
    Abstract: A method and system for configuring a USB3 input/output port in a camera are disclosed. The method comprises responsive to an indication that a peripheral device is a non-USB3 device, remapping pins of the USB3 input/output port to a first predefined port configuration associated with an I2C protocol by remapping a RX1? pin to communicate a first I2C signal and remapping a RX1+ pin to communicate a second I2C signal, and responsive to successful authentication between the camera and the peripheral device via the I2C protocol, enabling communication with the peripheral device and remapping the pins of the USB3 input/output port to a second predefined port configuration compatible with operation of the authenticated peripheral device by remapping a TX2+ pin to communicate a first general purpose input/output signal and remapping a TX2? pin to communicate a second general purpose input/output signal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 26, 2021
    Assignee: GoPro, Inc.
    Inventor: Yu Wang
  • Patent number: 10895899
    Abstract: A circuit includes a regulation circuit configured to intercept messages on a configuration channel of a universal serial bus (USB) cable between a USB source device and a USB sink device. The regulation circuit regulates a source capability message from the USB cable configuration channel based on a predetermined power capability of the USB cable.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Deric Wayne Waters
  • Patent number: 10895986
    Abstract: A control apparatus includes first and second regions that each store device information of a monitoring target device; an evacuating region; and a processor configured to execute a procedure including: controlling switching between first and second states at a predetermined timing, the first state including the first region being in updatable and unreferenceable states and the second region being in referenceable and unupdatable states, the second state including opposite states to the first state; evacuating, in a case where the second region is being referred at a timing when the first state is switched to the second state, unreferred information stored in the second region to the evacuating region; controlling, after completion of evacuation, switching the state of the second region from referenceable to updatable; and controlling, after completion of reference to the unreferred information in the evacuating region, switching the state of the first region from updatable to referenceable.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Yoshida, Tomohiko Muroyama
  • Patent number: 10887782
    Abstract: The present invention is directed to optimization and failure detection of a wireless base station network. Based on Received Signal Strength Indication (RSSI) measurements, a cloud server determines an optimal transmission sequence. For each base station of the optimal transmission sequence, a predecessor and a successor are designated. Each base station of the sequence generates a packet. The most distant base station (relative to the cloud server) transmits its packet to its successor. Each base station of the sequence (in turn) receives the packet from its predecessor, combines the received packet with its own generated packet, transmits the combined packet to its successor, and so on until the combined packet is relayed to a super base station at the end of the sequence. The super base station transmits the packet to the cloud server. Based on the packet size, the cloud server can ascertain which base station (if any) failed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: January 5, 2021
    Assignee: TRAKPOINT SOLUTIONS, INC.
    Inventors: Christopher Williams, Jon Siann
  • Patent number: 10840240
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10831176
    Abstract: Provided is a numerical controller in which a plurality of devices is allowed to be connected to a serial bus by a daisy chain, acquiring, from each of the devices, a connection number on the daisy chain and a device ID as connection information, determining presence or absence of a problem by comparing the connection information with a connection setting parameter obtained by associating the connection number with a logic axis number of the numerical controller, storing the connection information acquired by the connection information acquisition unit when there is no problem in the determination, and identifying a removed device by comparing the connection information acquired by the connection information acquisition unit with the connection information stored in the connection information storage unit when there is a problem in the determination, and excluding the removed device from the connection setting parameter, thereby creating connection setting data.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Fanuc Corporation
    Inventor: Takahiro Omori
  • Patent number: 10817205
    Abstract: Processing efficiency of a computer using a volume and processing efficiency of another computer using another volume corresponding to the volume can be maintained at high levels. In a computer system, a storage apparatus is able to provide a certain volume to a computer, and another storage apparatus provides data to the computer by causing a virtualization function to point to another volume from the certain volume and copying data from the other volume to the certain volume. An upper limit on the number of pages copiable from the other volume to the certain volume of the storage apparatus is set. A CPU of the other storage apparatus copies data in an amount equal to or smaller than the upper limit from a page among multiple pages of the other volume to a storage region corresponding to a page forming the certain volume of the storage apparatus.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 27, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Takaki Nakamura, Hideo Saito, Ken Nomura
  • Patent number: 10805240
    Abstract: A method and apparatus of a network element that processes control plane data in a network element is described. In an exemplary embodiment, the network element receives network data and determines a class of the network data. The network element additionally determines that this class of the network data is to be processed. The network element further marks the network data based on at least on an existence of an indication of whether the network element had previously processed other data in the same class as the class of the network data. Furthermore, the network element queues the network data.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 13, 2020
    Assignee: Arista Networks, Inc.
    Inventors: Francois Labonte, Hugh W. Holbrook
  • Patent number: 10777257
    Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 10762021
    Abstract: An information system connected to hosts and an information processing system manages a second ALU connected to the hosts via a second logical path, and second SLUs for receiving I/O requests from the hosts via the second logical path. A processor manages a first ALU connected to the hosts via a first logical path and first SLUs that receive I/O requests from the hosts via the first logical path, and builds up a first group including the first SLUs. A first SLU and a second SLU compose an HA pair, and the HA pair is provided to the hosts as one volume. The processor evaluates the state of the first logical path based on the pair state of the first SLU that composes the HA pair included in the first group so priorities with which the hosts issue I/Os to the first logical path can be determined.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: September 1, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Nakagawa, Akira Deguchi, Hiroshi Nasu, Tomohiro Kawaguchi
  • Patent number: 10715449
    Abstract: A layer 2 load balancing system includes server devices that provide virtual machines that each share a virtual Media Access Control (MAC) address. A switch device is coupled to each of the server devices via respective ports on the switch device. The switch device receives the virtual MAC address during a time period via each of the respective ports connected to the server devices and, in response, identifies a server device cluster that shares the virtual MAC address. When the switch device receive packets that are part of a packet flow and that are directed to the virtual MAC address, it then directs each of the packets that are part of the packet flow to one of the virtual machines that is provided on one of the server devices in the server device cluster.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Dell Products L.P.
    Inventors: Narayanaswamy Perumal, Dinesh Babu Kannan, Balaji Venkat Venkataswami
  • Patent number: 10700886
    Abstract: A driver apparatus for a differential bus is provided, having a first transistor and a fourth transistor which are connected in order to drive the bus to a dominant state, and a second transistor and a third transistor which are connected in order to drive the bus to a recessive state. The driver apparatus also comprises a collision detection circuit which is set up to detect a collision state on the bus on the basis of measurements of currents through at least one transistor of the first, second, third and fourth transistors.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Magnus-Maria Hell, Dieter Metzner
  • Patent number: 10685595
    Abstract: A connection device connected to an image display unit that is head-mounted includes a connector to which an image signal is input; and a connector to which an image signal is input and which is capable of outputting sensor data. The connection device further includes a setting unit that sets a selection between the image signals; and an output control unit that selects the connector for outputting the image signal by a connection unit according to the setting. The setting unit sets the image signal to be output from the connection unit when the image signal is input.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 16, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yuichi Kunitomo, Takehiro Ono
  • Patent number: 10657076
    Abstract: An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 19, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Kuan-Jui Ho, Yi-Hsiang Wang
  • Patent number: 10606779
    Abstract: A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 31, 2020
    Assignee: Altera Corporation
    Inventor: Evan Custodio
  • Patent number: 10567290
    Abstract: A method for managing traffic of a plurality of packets in a plurality of packet flows transmitted using a time-slotted interface. The packet flows traverse a plurality of switches of a transport network according to an assigned path from a source node to a destination node. The method comprises determining (202) an end-to-end latency of a plurality of packets traversing a current switch in packet flows and assigning (204) priority to packets to the packets traversing the current switch, wherein a priority value of a packet depends on the determined end-to-end latency of said packets. The method further comprises allocating (206) a time slot in an output interface of the current switch to the packet having the highest priority value among the packets competing for said time slot.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 18, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Fabio Cavaliere, Giulio Bottari, Stefano Stracca
  • Patent number: 10552253
    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
  • Patent number: 10545808
    Abstract: Embodiments of the present application provide a method, apparatus and system for processing data, the method is applicable to an electronic device, wherein the electronic device is connected to a memory card that has been formatted in a proprietary manner in advance and the memory card includes at least one cold data area. The method includes: obtaining the number CR of reads for data stored in a target cold data area C stored locally; determining whether the number CR of reads reaches a preset threshold TCR for reading failure of cold data; if the number CR of reads reaches a preset threshold TCR for reading failure of cold data, transmitting a start address and a end address of the data stored in the target cold data area C to a controller of the memory card, and initializing the number CR of reads for processing the stored data by the controller according to the start address and the end address.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: January 28, 2020
    Assignee: Hangzhou Hikvision Digital Technology Co., Ltd.
    Inventors: Shuang Zhou, Jian Chen, Hui Qiao
  • Patent number: 10545904
    Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Edward Wentroble, Suzanne Mary Vining, Hassan Omar Ali
  • Patent number: 10539614
    Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann, Karen E. Yokum
  • Patent number: 10530636
    Abstract: At least some embodiments of invention provide a method, device and system for link management in a Virtual Machine (VM) environment. The method includes: a heartbeat handshake link is established with a VM. After the heartbeat handshake link is successfully established, Link Aggregation Control Protocol (LACP) state information of a Physical Function (PF) of a plurality of a Network Interface Cards (NICs) is acquired. The LACP state information is sent to the VM through the heartbeat handshake link.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 7, 2020
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventor: Lijun Ma