Path Selecting Switch Patents (Class 710/316)
  • Patent number: 10409722
    Abstract: A system on-chip includes a central processing unit and a memory controller. The memory controller receives initialization information indicating an initialization address range and an initialization value from the central processing unit, determines an initialization target memory and a local initialization address range of the initialization target memory based on the initialization information, and transmits initialization data including the initialization value to the initialization target memory by a predetermined unit to initialize the local initialization address range of the initialization target memory.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyong-Ho Cho, Ki-Soo Yu, Kyung-Il Sun
  • Patent number: 10387348
    Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Maxim Dan
  • Patent number: 10372673
    Abstract: A storage network element discovery method and an apparatus, where the method includes broadcasting or multicasting, by a control network element, a heartbeat message to at least one storage network element, where the heartbeat message includes address information of the control network element, receiving, by the control network element, a response message returned by at least one storage network element according to the heartbeat message, and determining an accessible storage network element according to the response message, where the response message includes network parameter information of the corresponding storage network element. Therefore, in a storage array, by broadcasting or multicasting a heartbeat message and according to a reply from a storage network element, a control network element may determine a storage network element that can be accessed by the control network element.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 6, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Haitao Guo, Yu Zhang, Yajun Chen
  • Patent number: 10359948
    Abstract: An embodiment of the invention may include a method, computer program product, and system for improving I/O performance in a heterogeneous storage environment. The embodiment may include storage devices of different storage device types having different I/O performances. Each of the storage devices is accessible via a SAS interface. The embodiment may include identifying a plurality of storage devices of the heterogeneous storage environment. The embodiment may include creating a table including information about identifiable storage devices and attributes. The embodiment may include separating a block I/O data stream into storage device type classes. The embodiment may include routing I/O requests of corresponding device type classes to their assigned physical lanes using the information included in the table, thereby improving the I/O performance of the heterogeneous storage environment.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Itzhack Goldberg, Kai Jehnen, Frank Krick, Thorsten Muehge, Erik Rueger
  • Patent number: 10331604
    Abstract: A universal serial bus (USB) hub includes an upstream port configured to be communicatively coupled to a USB host, a downstream port, and a USB hub core circuit. The circuit is configured to determine a detachment from the downstream port, determine whether a USB element has reattached to the downstream port in USB mode, and, based on a determination that the USB element has reattached to the downstream port in USB host mode, perform USB multi-host bridging for the USB host and the USB element.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 25, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Atish Ghosh, Rekha Edamalapati, Vinoth Sekar
  • Patent number: 10333505
    Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 25, 2019
    Assignee: M31 Technology Corporation
    Inventors: Huai-Te Wang, Chih Chien Hung
  • Patent number: 10289584
    Abstract: According to one embodiment, an electronic device includes a USB Type-C connector connected to a second electronic device, a processor connected to the USB Type-C connector and including four terminals outputting an image signal, and a USB controller connected to the USB Type-C connector and including two terminals outputting USB 3.x signal. The USB Type-C connector includes two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX1, RX1, TX2 and RX2 defined under the USB Type-C standard. The image signal and the USB 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX1, RX1, TX2 and RX2.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Toshiba Client Solutions Co., LTD.
    Inventor: Hiroaki Chiba
  • Patent number: 10291415
    Abstract: A method of configuring a controller for communication with at least one instrument module includes electrically connecting an interface of the at least one instrument module to an interface of the controller, receiving with the controller an identification signal from the interface of the at least one instrument module through a portion of the interface of the controller, and executing with the controller a configuration program that corresponds to the identification signal to enable communication between the at least one instrument module and the controller.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: May 14, 2019
    Assignees: Bosch Automotive Service Solutions Inc., Robert Bosch GmbH
    Inventors: Frank E. Anderson, Bernd Heppner
  • Patent number: 10275387
    Abstract: The present invention provides method and associated interface circuit for mitigating interference due to signaling of a bus between two electronic apparatuses. The method may include: via the bus mechanically compliant to a bus specification, communicating and transporting data at a nonstandard speed which is not compliant to the bus specification. The method may further include: before communicating and transporting data at the nonstandard speed, signaling via the bus at a standard speed to configure a speed switching from the standard speed to the nonstandard speed, with the standard speed compliant to the bus specification. For example, the bus specification may be USB specification, the standard speed may be 5 Gbps (SuperSpeed of USB 3.0 specification), and the nonstandard speed may be lower than the standard speed, e.g., 2.5 Gbps, which forms a spectrum notch at a frequency of wireless connection, e.g., 2.4 GHz of Wi-Fi.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: April 30, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ming-Pei Chen, Chuing-Nien Tseng, Juei-Ting Sun, Kuo-Chieh Wang
  • Patent number: 10244558
    Abstract: A wireless communication terminal has: a wireless module part which transmits a radio frame signal; a transmission loss information detection part which detects transmission loss information representing whether or not the radio frame signal transmitted by the wireless module part has reached a transmission destination; a collision information detection part which detects collision information representing an aspect of collision between the radio frame signal transmitted by the wireless module part and another radio frame signal; and a transmission control part which controls a transmission process executed by the wireless module part, on a basis of the transmission loss information and the collision information.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 26, 2019
    Assignee: NEC Communication Systems, Ltd.
    Inventors: Yuki Baba, Akira Matsumoto, Peng Shao
  • Patent number: 10235316
    Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. Each of the plurality of PCIe subfabrics includes a managing central processing unit and a PCIe fabric switch. One or more communication paths is configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Daniel Dufresne, Matthew Mullins, Antonio Fontes, Patrick J. Weiler
  • Patent number: 10235317
    Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics including at least a first PCIe subfabric and a second PCIe subfabric. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit. The first PCIe subfabric is configured to enable multipath communication between a first element coupled to the first PCIe subfabric and a second element coupled to the second PCIe subfabric.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Daniel Dufresne, Matthew Mullins, Antonio Fontes, Patrick J. Weiler
  • Patent number: 10236974
    Abstract: A first set of signal carriers of a plurality of signal carriers may be determined to be faulty. The first set of signal carriers may be for transmitting a first set of respective lane signals of a plurality of lane signals. A second set of signal carriers of the plurality of signal carriers may be identified as not faulty. The second set of signal carriers may be for transmitting a second set of lane signals of the plurality of lane signals. Based on the determining and identifying, one or more of the first set of lane signals may be routed from the first set of signal carriers through a first subset of the second set of signal carriers, the routing of the one or more of the first set of lane signals may cause a bandwidth capacity to increase to a highest available bandwidth.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Suresh Guduru
  • Patent number: 10229085
    Abstract: Systems and methods for managing name assignments in a Fiber Channel (FC) storage arrays are provided. One example method includes receiving a port name for a slot of a controller of the FC storage array. The slot of the controller is configured to receive an FC card for providing communication between the FC storage array and an FC fabric. The method includes binding the port name to the slot of the controller, and the port name is saved to a database managed by the controller. The method further includes assigning the port name to the FC card when installed in the slot. The FC card is swappable with other FC cards, and thus other FC card will also maintain the port name of the slot.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Evan Chiu, Jason M. Fox
  • Patent number: 10225185
    Abstract: A processor initiates an execution of a network driver in a first node comprising a master node of a plurality of nodes in a switchless network. The network driver configures the plurality of nodes and service level in the switchless network by transmitting management datagrams from the master node, wherein the management datagrams include an attribute that allows the management datagrams to be propagated among the plurality of nodes of the switchless network without being terminated at host channel adapters of the plurality of nodes.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lior Chen, Gregory Etelson, Constantine Gavrilov
  • Patent number: 10216625
    Abstract: A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 26, 2019
    Assignee: SK Hynix Memory Solutions Inc.
    Inventor: David J. Pignatelli
  • Patent number: 10204067
    Abstract: A data transfer device of a display equipment and a data transfer method are provided. The data transfer device of the display equipment includes a display panel, a first transfer connector, a second transfer connector, a configuration switch and a control unit. The first and the second transfer connector are in line with a universal serial bus (USB) protocol including a plurality of data paths. When a first electronic device is connected to the first transfer connector, the control unit separates the data paths of the first transfer connector into at least one video data path and at least one data-transferring data path dynamically. A video signal of the first electronic device is transferred to the display panel through the video data path, and the first electronic device and the second electronic device transfer data to each other through the data-transferring data path.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 12, 2019
    Assignee: Wistron Corporation
    Inventor: Feng-Yuan Chen
  • Patent number: 10198392
    Abstract: There is provided a peripheral device including a multi-pole plug inserted into a jack of a jack device, the jack device including the jack, a conversion unit that converts a physical amount into an electrical signal or converts an electrical signal into a physical amount, a detection unit that detects whether the jack device is a corresponding device capable of handling multiplexed data obtained by multiplexing the electrical signal input and output to and from the conversion unit, a transmission and reception processing unit that transmits or receives the multiplexed data via a predetermined terminal of the multi-pole plug when the jack device is a corresponding device, and a function switching unit that performs assignment of an electrical function of a terminal other than the predetermined terminal of the multi-pole plug.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: February 5, 2019
    Assignee: Sony Corporation
    Inventors: Go Igarashi, Yasunobu Murata, Kohei Asada, Tetsunori Itabashi, Mitsuhiro Suzuki
  • Patent number: 10200309
    Abstract: A switch includes a chassis, a drive bay including a plurality of downlink switch ports that are configured to be connected to a plurality of storage devices, a plurality of uplink switch ports, and an embedded circuit for providing signal switching between the plurality of uplink switch ports and the plurality of downlink switch ports. The drive bay is disposed on a first side of the chassis, and the plurality of uplink switch ports are disposed on a second side of the chassis that is opposite to the first side of the chassis. The plurality of downlink switch ports is embedded in the drive bay.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Fred Worley, Sompong Paul Olarig
  • Patent number: 10176134
    Abstract: The present invention discloses a portable device and a method of controlling HDMI signal output therein. The portable device comprises: a microcontroller unit, a USB Type-C interface, and a plurality of analog switches. Each of the analog switches is arranged between a HDMI signal output pin of the microcontroller unit and a corresponding pin of the USB Type-C interface. The microcontroller unit is configured to detect a positive or reverse insertion direction of the USB Type-C interface, and output a corresponding control signal to the analog switch according to the difference of the insertion direction. The analog switch is configured to shift a switching direction according to the control signal so that the HDMI signal is output through a corresponding pin of the USB Type-C interface.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 8, 2019
    Assignee: Beijing Pico Technology Co., Ltd.
    Inventor: Guanghui Liu
  • Patent number: 10169265
    Abstract: A camera includes an input/out system and one or more input/output ports. The camera configures the pins of the input/output port according to a default pin configuration. The camera detects a peripheral device is connected the input/output ports and receives an identifier from the peripheral device indicating whether the peripheral device is a USB3 device or a non-USB3 device. If the peripheral device is a non-USB3 device, the camera remaps the pins to a first configuration. The camera authenticates with the peripheral device to determine if the peripheral device meets a criteria for an approved device. If the authentication is successful, the camera enables communication with the peripheral device and remaps the pins to a second configuration. If the authentication is unsuccessful, the camera disables communication with the peripheral device and remaps the pins of the input/output port to the default configuration.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: January 1, 2019
    Assignee: GoPro, Inc.
    Inventor: Yu Wang
  • Patent number: 10146728
    Abstract: A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB PHY-layer circuit; a first switch circuit for communicating data with an upstream port through the first USB PHY-layer circuit; a second switch circuit for communicating data with a downstream port through the second USB PHY-layer circuit; a control signal transmission interface; a signal repeater circuit; and a control unit configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples the upstream MAC-layer circuit or the signal repeater circuit with the first USB PHY-layer circuit, while the second switch circuit selectively couples the downstream MAC-layer circuit or the signal repeater circuit with the second USB PHY-layer circuit.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: December 4, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chong Liu, Luo-Bin Wang, Jian-Jhong Zeng, Neng-Hsien Lin
  • Patent number: 10140231
    Abstract: Example embodiments disclosed herein relate to configuring a flexible port. The configuration of a computing device is detected based on a coupling of an interface to a flexible input/output port. The flexible input/output port is configured based on the detected configuration of the computing device.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: November 27, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan D. Bassett, Raphael Gay, Linden H. McClure
  • Patent number: 10135127
    Abstract: A multiple-antenna positioning system with a single drive element, providing reduced weight and complexity over systems that have a drive element for each antenna. In certain examples, each antenna can be coupled with a rotating spindle, with each antenna spindle being coupled with a pair of link arms. By driving a single drive spindle, each of the antenna spindles in the system can be rotated by the associated pair of link arms. The link arms can have an adjustable length, such as through a turnbuckle mechanism, to reduce backlash in the system, and in some examples can apply a preload to the system. By reducing backlash, the multiple antenna positioning system can have improved responsiveness to a rotation of the single drive element, as well as improved stability of the positioning of each antenna when the drive element is held in a fixed position.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: November 20, 2018
    Assignee: Viasat, Inc.
    Inventors: Jack C. Newkirk, B. Wayne Holt, Bradley H. Smith, Kevin M. Skinner, E. Mitchell Blalock
  • Patent number: 10127494
    Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: November 13, 2018
    Assignee: Google LLC
    Inventors: Pierre-luc Cantin, Olivier Temam
  • Patent number: 10120832
    Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 6, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shachar Raindel, Idan Burstein, Noam Bloch, Shlomo Raikin
  • Patent number: 10101929
    Abstract: Embodiments of the present disclosure provide a method and apparatus of maintaining data consistency by receiving, when a first storage processor is in a Ready state, a request for configuration information of a storage object from a second storage processor; in response to receiving the request, setting the first storage processor to an Updating-Peer state, and sending the configuration information to the second storage processor to maintain consistency of the configuration information in the first and second storage processors; and in response to the configuration information being sent, setting the first storage processor back to the Ready state.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 16, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Hongpo Gao, Xinlei Xu, Huibing Xiao, Geng Han
  • Patent number: 10095592
    Abstract: A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a second device, a transaction processing packet, where the transaction processing packet includes processing information about access of a host to a peripheral component interconnect express (PCIe) device, the processing information is used to describe information required for resuming a transaction when the transaction is interrupted, the second device further stores topology information of the PCIe device, and a driver for the PCIe device is loaded to the second device, and when detecting that the first device fails, continuing to process, by the second device according to the topology information, the driver, and the processing information, the transaction that is about the access of the host to the PCIe device and is being processed when a first device fails.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 9, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Junjie Wang, Ruiling Wang, Yan Ye
  • Patent number: 9996284
    Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 12, 2018
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 9983953
    Abstract: The disclosure describes a system including a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations over an interconnect to a second computer system. A second computer system includes a second memory controller and a second inter-computer transfer interface to receive the information about the write operations over an interconnect, wherein the write operations are duplicated through the second memory controller. In other embodiments, a system includes a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations of the first computer system during a lockstep operation. Still other embodiments are described.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 29, 2018
    Assignee: INTEL CORPORATION
    Inventors: Kenneth W. Privitt, Scott M. Rider
  • Patent number: 9971733
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 15, 2018
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 9939487
    Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann, Karen E. Yokum
  • Patent number: 9940280
    Abstract: An electronic assembly perform data storage operations on behalf of a set of storage processors (SPs). The electronic assembly includes an enclosure, and a set of peripheral component interconnect express (PCIe) switches which installs within the enclosure. The set of PCIe switches is constructed and arranged to connect to the set of SPs while the set of SPs is external to the enclosure. The electronic assembly further includes a set of data storage devices which installs within the enclosure. The set of data storage devices is constructed and arranged to persistently store data on behalf of the set of SPs via PCIe-based communications through the set of PCIe switches.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 10, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Walter O'Brien, David W. Harvey, Robert W. Beauchamp, Steven D. Sardella, Antonio L. Fontes
  • Patent number: 9910801
    Abstract: A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer. The Input-Output (I/O) is uniformly viewed and treated as an individual First-In-First-Out (FIFO) device. Pluralities of memory areas are implemented for user stack, kernel stack, interrupt stack and procedure call stack. Only one I/O arbiter is necessary for a CPU model that arbitrates between a plurality of FIFOs substituting data caches for on-chip implementation, thus eliminating traditional data transfer techniques using Direct-Memory-Access (DMA), bus control and lock signals leaving just the interrupt signals and the new synchronous signals for an easy and streamlined system design and CPU model. Supporting an interrupt-driven, FIFO-based I/O and synchronous burst data transfer the CPU employs a simple linear large register sets without bank switching.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 6, 2018
    Assignees: UNIVERSITI TEKNOLOGI MALAYSIA, PAHLAWAN MIKRO
    Inventors: Muhammad Nasir Bin Ibrahim, Namazi Bin Azhari, Adam Bin Baharum
  • Patent number: 9880536
    Abstract: A programmable system includes a programmable analog system that is reconfigurable to perform various analog operations, and includes a programmable digital system that is reconfigurable to perform various digital operations. The programmable system also includes a microcontroller capable of reconfiguring and controlling the programmable analog system and the programmable digital system. The programmable digital system is configured to control the programmable analog system autonomously of the microcontroller.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 30, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bert S. Sullam, Harold M. Kutz, Monte Mar, Eashwar Thiagarajan, Timothy Williams, David G. Wright
  • Patent number: 9864718
    Abstract: A physical layer network interface module (PHY-NIM) adaptation system provides a PHY-NIM device and an attachable media access control (MAC) device. The PHY-NIM device interconnects with the attachable MAC device and the attachable MAC device interconnects to a network appliance to provide at least one of network switch capabilities and MAC device capabilities for use by the network appliance. The PHY-NIM device interconnects directly to the network appliance where the network appliance has at least one of an internal network switch and an internal MAC device in a southbridge input/output (I/O) interface chip of the network appliance.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James G. Douglas, James A. Heiberger, Seth D. Lewis, Robert L. Martin, III, Todd D. Podhaisky
  • Patent number: 9842071
    Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: December 12, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: James Casady, Rodney Pesavento, Sergey Pavlov
  • Patent number: 9837736
    Abstract: An apparatus comprises a printed circuit board (PCB) having a first surface and a second surface, a plurality of blind press-fit vias penetrating the first surface and extending partially through the PCB toward the second surface, the blind press-fit vias configured to receive press-fit connectors of at least one component to be connected to the PCB, and a plurality of electrical connectors disposed in a region of the second surface opposite the blind press-fit vias and configured to interface with one or more signal processing components disposed on the second surface.
    Type: Grant
    Filed: June 21, 2014
    Date of Patent: December 5, 2017
    Assignee: Keysight Technologies, Inc.
    Inventors: Kuen Yew Lam, Thiam Ping Oon, Jared Richard
  • Patent number: 9800521
    Abstract: Systems and methods are disclosed for effectuating control-plane changes at increased speeds to protect a network in which switching operations are performed. Operations to effectuate control-plane changes in the network can be divided between software and more-rapid, dedicated hardware within a line card. Examples of operations reserved to hardware implementation can include blocking and unblocking of ports, flushing of learned entries from switch tables, and coordination of control-plane changes through the generation of messages sent between nodes, and also between line cards of a node. Determinations about the need for hardware-driven, control-plane changes may be made based on events occurring in the network in accordance with any of a number of different network protection protocols. The protocol may be implemented in a state machine and the software may determine the state of the hardware through a master/slave relationship.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: October 24, 2017
    Assignee: Ciena Corporation
    Inventors: Eric Arthur Holmberg, Paul Simon Nahlous, Balaji Subramaniam
  • Patent number: 9772653
    Abstract: A Universal Serial Bus (USB) dock is provided. The USB dock includes: a plurality of downstream ports; and a upstream port, connecting the USB dock to a portable device, wherein the upstream port includes an On-the-go (OTG) ID pin and a differential pair; and a microcontroller, configured to detect operating states of the portable device, wherein when it is detected that the portable device is in a USB OTG host mode and has entered a suspend state, the microcontroller controls the portable device to switch from the USB OTG host mode to a USB device mode by toggling a state of the USB OTG ID pin, thereby charging the portable device via the upstream port.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: September 26, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Chin-Sung Hsu, Terrance Shiyang Shih, Li-Feng Pan
  • Patent number: 9760527
    Abstract: A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Data may be communicated between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Further, a network interface controller (NIC) module may be configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 12, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Norbert Egi, Guangyu Shi
  • Patent number: 9762429
    Abstract: A processor is configured to determine non-core functions to be performed by an unmanaged device disposed on a packet based computer network. A control message generator is configured to (i) generate a point-to-point control message conforming to a point-to-point control protocol for controlling the unmanaged device over a point-to-point serial bus connection to perform the determined non-core functions, and (ii) encapsulate the point-to-point control message in a transport packet for transport over the packet based computer network. A packet transmitter is configured to transmit the transport packet including the encapsulated point-to-point control message via a port coupled to the packet based computer network, the packet based computer network configured to route the transport packet including the encapsulated point-to-point control message based on a header included in the transport packet so that the point-to-point control message is received at the unmanaged device via the packet based computer network.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: September 12, 2017
    Assignee: Marvell International Ltd.
    Inventor: Ilan Elmaliah
  • Patent number: 9753880
    Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 5, 2017
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Richard David Sodke, Kuan Hua Tan, Robert Kristian Watson, Larrie Simon Carr
  • Patent number: 9747546
    Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 29, 2017
    Assignee: Google Inc.
    Inventors: Jonathan Ross, Norman Paul Jouppi, Andrew Everett Phelps, Reginald Clifford Young, Thomas Norrie, Gregory Michael Thorson, Dan Luu
  • Patent number: 9734113
    Abstract: A PCI-E signal transmission apparatus and an image forming apparatus using the same are provided. The PCI-E signal transmission apparatus includes a controller board, and at least one unit board which is connected to the controller board through a differential signal transmission cable, which uses a PCI-E protocol, to transceive data. Therefore, it is possible to transmit a signal using an inexpensive cable at a high speed.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 15, 2017
    Assignee: S-PRINTING SOLUTION CO., LTD.
    Inventors: Seung-hun Park, In-gu Kwak, Jai-yeol Lee, Eun-ju Hong
  • Patent number: 9710748
    Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 18, 2017
    Assignee: Google Inc.
    Inventors: Jonathan Ross, Norman Paul Jouppi, Andrew Everett Phelps, Reginald Clifford Young, Thomas Norrie, Gregory Michael Thorson, Dan Luu
  • Patent number: 9684530
    Abstract: A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: June 20, 2017
    Assignee: VIA Technologies, Inc.
    Inventor: Kuan-Jui Ho
  • Patent number: 9666250
    Abstract: Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: May 30, 2017
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 9652426
    Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing. A reliable TLP transmission module is configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time. A destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC. Thereby, reliable transmission of a TLP is implemented in a case of a PCIE switching dual-plane networking connection.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 16, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Dexian Su, Yimin Yao, Jing Wang
  • Patent number: 9632963
    Abstract: Embodiments of the present invention provide a system and a method for transmitting data based on Peripheral Component Interconnect Express 9PCIe). The system includes: a PCIe switching network, multiple switch terminal devices, a managing unit, multiple host processing units, multiple terminal processing units, multiple hosts, and multiple terminal devices. After a PCIe data packet sent by a host is processed by a host processing unit, a new PCIe data packet that can be transmitted in a PCIe switch is constructed, and is transferred, by using a switch terminal device and a terminal processing unit, to a terminal device. The embodiments can break through a limitation about a single root node of PCIe and implement sharing of a PCIe switching network by multiple hosts.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 25, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chang Yi, Jing Wang, Dexian Su