Abstract: An innovative circuit is disclosed that enhances performance on a SCSI bus by pipelining nexuses in order to associate all nexus attributes on a per nexus basis. For example, a pipeline of nexuses is created so as to associate all of the nexus attributes from different connections involved. A plurality of load stages is provided whereby each load stage can latch all nexus attributes received at that stage. The latched nexus attributes can be loaded and stored at that stage or shifted to the next stage. As a result of the loading and shifting operations, a pipeline of nexuses is created that associates all of the nexus attributes received from the different connections on a per nexus basis. Therefore, all types of data traffic can be processed concurrently on a SCSI bus, which enhances data throughput and bus performance.

Abstract: Various embodiments of a scalable routing system for use in an interconnection fabric are disclosed. In this routing scheme, a routing directive describes a route in the interconnection fabric between a sending node and a destination node. Either the sending node or a sending device connected to the sending node encodes the routing directive in a message to be sent to the destination node. The routing directive may include a variable number of segments. Each segment includes a distance component and a direction component that tell each node along the route how it should send the message. Generally, each distance component describes a distance in the interconnection fabric while each direction component specifies a direction in the interconnection fabric.

Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: A service processor is provided for a computer system that includes a host processor and the service processor. The service processor includes a management interface including a first port forming an external user interface and a second port forming an internal console interface. The service processor is operable to provide system management functions within the computer system. It is also operable to respond to external mode switching commands received via the user interface to operate one of two modes. The first mode is a management mode in which commands received via the user interface are processed by the service processor. The second mode is a console mode in which commands received via the user interface are passed by the service processor to the console interface for processing by the host processor. The service processor can be implemented by a dual-ported microcontroller.

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n?1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n?1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: In a printing system in which with a plurality of different types of controllers connected to one serial bus, different types of print data can be inputted to and printed by a printing unit. When a set top box and desktop and portable personal computers, different in type from each other, are connected to a IEEE 1394 serial bus, screen data is outputted from the set top box to an AV/C printer and PDL data is outputted from the personal computers to the AV/C printer. The AV/C printer judges the image type of the input data. Based on the image type, the printing system converts the print data to a type of print data supported by the AV/C printer.

Abstract: A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.

Abstract: A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (D) generating a plurality of notification signals on a plurality of lines in response to the messages as written to a plurality of addresses.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: A data storage apparatus arranged to provide redundancy in a storage enclosure containing multiple Serial ATA disk drives is disclosed. The apparatus comprises at least one disk drive of a kind having a single port for the input and output of serial data and at least two disk drive controllers each having data transmit and receive paths connected in common to the single port. The apparatus then switches control to either controller if the other should fail.

Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. The method and an apparatus is capable of selectively transmitting data over a bidirectional shared bus network including a plurality of channels between pairs of MCPEs in the networked array. The method and an apparatus then selectively transmits a sideband bit indicating a direction in which the data is transmitted in the shared bus network.

Abstract: A shared I/O subsystem that includes a plurality of I/O interfaces for coupling a plurality of computer systems where each of I/O interfaces communicatively couples one of the computer systems to the shared I/O subsystem.

Abstract: A method for further processing data recorded on a computer arranged in a computer network. A quantity of data is recorded on the computer and stored in a memory. A quantity of supplementary data describing a property of the quantity of is generated centrally or peripherally in real time and stored. This quantity of supplementary data is used to specifically access or extract a selected quantity of the quantity of data recorded and stored.

Abstract: Methods and systems consistent with certain aspects related to the present invention provide a digital network having a plurality of data storage elements, at least one client, and a switch element. The switch element may be operable to receive access requests from the client and provide access to data on the storage elements in response to one or more access requests.

Abstract: An information processing apparatus having a common storage accessible by a host includes: an NIC group connected with a plurality of communication paths connected to the host; an I/O processing unit for executing I/O processing of the common storage in response to an I/O request of the host; a storing unit for holding log information for each data transfer performed from/to the host; and a communication path selection unit for selecting, as a data transfer path, a communication path having actually indicated good I/O processing performance among communication paths used in the past data transfer approximate in a communication condition by referring to the log information held by the storing unit.

Abstract: Method and apparatus are disclosed for moving logical data entities from one storage element to another storage element in a computer storage system, when more than one user or host computer may access the logical entity. According to one embodiment of the method, all of the read requests for the logical entity are moved to a new copy of the logical entity, before writes for logical entity are moved to the new copy.

Abstract: Reversing a communication path between a first volume on a first storage device and a second volume on a second storage device includes suspending communication between the first and second volumes while maintaining operations for other volumes of the storage devices, causing the first volume to change from a source volume to a destination volume without destroying the first volume, causing the second volume to change from a destination volume to a source volume without destroying the second volume, and resuming communication between the first and second volumes. Causing the first volume to change from a source volume to a destination volume may include modifying a table of the first storage device. Causing the second volume to change from a source volume to a destination volume may include modifying a table of the second storage device.

Abstract: Systems, methods, and devices for nondestructive data transfer are disclosed. A method comprises monitoring commands directed to a storage device and evaluating the commands to determine whether the commands are harmful or benign. Benign commands are presented to the storage device. If a command is harmful to the contents of the storage medium, a replacement command is presented to the storage device, and a response expected from the storage device is emulated. A device implementing the method may include an intercept logic, a bridge unit and an isolate switch. In an embodiment of a system that implements the method, the device is coupled between a storage device and a computing device. The method may be implemented in software instructions stored on a machine readable medium and executed by a processor.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A bus interface circuit arrangement and method. In various embodiments, a bus interface circuit arrangement interfaces with a bus functioning in accordance with a bus protocol. The bus interface circuit arrangement includes a bus interface circuit having a port arranged to be coupled to the bus. The bus interface circuit provides physical and link layers of the bus protocol. A bus processing block, implemented with a programmable device, is coupled to the bus interface circuit and is configured to perform selected processing in response to selected bus messages. A filter circuit, also implemented with a programmable device, is coupled to the bus interface circuit and to the bus processing block. The filter circuit is configured to direct bus messages to a selected one of the bus interface circuit and the bus processing block responsive to a code in the bus message.

Abstract: A communications system is arranged for serially chaining multiple portable pendant peripherals to a portable host device. The system enables multiple low power input/output peripherals to communicate over a bi-directional data line with a portable host device such as a PDA or cellular phone. Fixed-length data packets are employed in a store-and-forward approach between the host device and the pendant peripherals. An upstream pendant system component controls a unidirectional clock signal that regulates data transfers to or from the host device and a downstream pendant peripheral. A device identification field associated with the data packet is incremented or decremented as the data packet is forwarded along the pendant bus chain until it reaches its destination.

Abstract: An existing disk drive storage enclosure is converted into a standalone network storage system by removing one or more input/output (I/O) modules from the enclosure and installing in place thereof one or more server modules (“heads”), each implemented on a single circuit board. Each head contains the electronics, firmware and software along with built-in I/O connections to allow the disks in the enclosure to be used as a Network-Attached file Server (NAS) or a Storage Area Network (SAN) storage device. An end user can also remove the built-in head and replace it with a standard I/O module to convert the enclosure back into a standard disk drive storage enclosure. Two internal heads can communicate over a passive backplane in the enclosure to provide full cluster failover (CFO) capability.

Abstract: Provided are a method, system, and program for increasing processor utilization. A list of work is divided for processing among a plurality of processes, wherein a process is allocated a part of the list of work to process, and the processes execute in parallel. If a process completes the list of work allocated to the process then the process is made available on an available process queue. Before a process performs any work, the process reads the available process queue and determines if any process is available to share the work. If so, the work is split up between the examining process and the available process. In one implementation, the work involves scanning a cache and if necessary destage data.

Abstract: An information communication system for performing information communication between a first system and a second system is disclosed. The communication system includes a first communication path that is used for information communication when a transfer size between the first system and the second system is smaller than a predetermined size and is capable of high-speed response, and a second communication path that is used for information communication when the transfer size between the first system and the second system is larger than the predetermined size and has a larger transfer capability than that of the first communication path. Each of the first and second systems comprises main control means for selectively using one of the first and second communication paths in accordance with a size of information subjected to information communication with a counterpart system.

Abstract: Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory configured to store context parameters for each of the virtual DMA channels, a set of DMA resources, a DMA controller coupled to the context memory, and several I/O resources. The DMA controller is configured to configure the set of DMA resources as different virtual DMA channels using context parameters associated with different respective ones of the virtual DMA channels. Each virtual DMA channel corresponds to one of the I/O resources.

Abstract: A data processing apparatus improves speed and efficiency of transfer of bit data, especially, multivalue data bit plane. For this purpose, a memory 50 holds four 8-bit multivalue data per 1 word, and bit plane coding processing is made by 4×4 (=16) multivalue data (processing block). In a memory area 51, the most significant bit (bit 7) of respective multivalue data (data 0 to 15 in FIG. 5) is collected in the order of multivalue data, and stored in one position (hatched portions in FIG. 5). Similarly, bit 6 is collected from the respective multivalue data and stored in one position.

Abstract: A method and a device for controlling data transmission between IDE apparatuses allow an IDE controller of an IDE control device to send read control signal to an IDE apparatus via a set of IDE interfaces and a signal control transmission line and then to send write control signal to another IDE apparatus via another set of IDE interfaces and another signal control transmission line. Thus, the output data from the IDE apparatus through the data transmission line can be accelerated the transmission speed thereof between IDE apparatuses so as to save the time for transmitting data.

Abstract: A system including a host processor (11) operating in combination with one or more co-processors (13) is disclosed. In this system, a file storage facility (17) stores executable files (40) that are called by a server (15) in the host processor (11) by way of an application programming interface (API) (16). In the disclosed system, the executable files (40) include both a program (obj 2) together with information (obj 2 attrs) indicative of a condition needed for execution of the program. Based on the condition information, the program (obj 2) is downloaded (67) to the co-processor (13), and executed by the co-processor (13) if the the condition is satisfied.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.

Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein.

Abstract: An embodiment of the present invention includes first and second storage elements. The first storage element stores request information transmitted from a first processor operating at a first frequency. The first and second processors operate at different frequencies. The request information is organized according to a request format. The second storage element stores response information transmitted by a second processor operating at a second frequency different than the first frequency in response to the request information. The response information is organized according to a response format.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a peripheral device from the computer system via a first link. The switch routes the data for a peripheral device to a console via a second link and routes the graphics data to a graphics controller via a third link. The graphics controller forms a part of the graphics card and is communicatively coupled to the switch via the third link, wherein the graphics controller generates a video signal to drive a video display.

Abstract: A memory architecture for a disk drive system in which (Synchronous Random Access Memory) SRAM and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. The SRAM is an “on-board” memory component, meaning that it is embodied on an integrated circuit that also includes a hard disk controller (HDC) and other disk drive components, while the DRAM is located on a separate integrated circuit externally, i.e., “off-board,” of the integrated circuit containing the SRAM. The SRAM includes a random access (RA) block that provides all RA functions, while the DRAM includes a direct memory access (DMA) block that provides all DMA functions.

Abstract: A call made with a communication device is processed using multiple call processors (CPs) operatively connected to a network. CPs use processing load information from other CPs to select which CP will handle call set up when the call is requested. A similar selection process is used for selecting one of CPs to perform other call processing functions and to terminate the call upon receiving a request to terminate the call. The CP selected to set up a call, tear-down a call or perform other call processing depends on the load associated with the processor and the load associated with setting up, tearing down performing other call processing for the call.

Abstract: Dynamically creating a communication path between first and second storage devices, includes creating a connection to a source volume on the first storage device and indicating that the source volume is not ready to transmit data on the communication path, after successfully creating the connection to the source volume, creating a connection to a destination volume on the second storage device and initially indicating that portions of one of: the destination volume and the source volume do not contain valid copies of data, where the destination volume accepts data from the source volume, and after successfully creating the connections to the source and destination volumes, indicating that the source volume is ready to transmit data on the communication path. Dynamically creating a communication path between first and second storage devices, may also include creating at least one of: the source volume and the destination volume.

Abstract: A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second (analysis) mode. During the normal mode, packets may be selectively conveyed through an I/O tunnel in the I/O node, and particular packets may be selectively conveyed to a peripheral bus interface in the I/O node. In the analysis mode, electrical signals corresponding to packets conveyed through the I/O tunnel may be replicated on a peripheral bus coupled to the peripheral bus interface. No conversion from the packet bus protocol to the peripheral bus protocol. A signal analyzer may be coupled to the peripheral bus, thereby allowing observation of the electrical signals.

Abstract: The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Abstract: An external storage device including first and second input/output units for performing input/output of information from/to an outside, a plurality of storage units connected between the first and second input/output units so that a transmission path of information forms a series connection, and a configuration control unit. The configuration control unit selects two adjacent units from the first input/output unit, each of the plurality of storage units, and the second input/output unit to set a boundary between the two units. Thus the configuration control unit causes the storage units located on a first input/output unit side of the boundary to communicate with the outside by using the first input/output unit and causes the storage units located on a second input/output unit side of the boundary to communicate with the outside by using the second input/output unit.

Abstract: A bus-repeater for coupling at least one first bus with a second bus, by way of which data may be transmitted in the form of serial digital signal pulse sequences and including at least one first and a second transmit-receive device, with which the first and, respectively, the second bus may be coupled and by way of which the bus-repeater may transmit signal pulse sequences, received via the first bus on the second bus, and vice versa. In accordance with the invention the bus-repeater includes locking device, which during transmission of a signal pulse received from the first bus to the second bus lock transmission by the bus-repeater of signal pulses, received from the second bus, via the first bus for a transmission locking time and vice versa.

Abstract: A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled.

Abstract: An apparatus for initiating partial transactions in a peripheral interface circuit for an I/O node of a computer system. An apparatus for performing partial transfers on a peripheral bus in response to a request for a stream of data includes a data buffer coupled to a control unit. The data buffer may be configured to store one or more data packets each containing data forming a portion of the data stream. The control unit may be configured to determine the presence of data packets stored in the data buffer that collectively contain a sequence of data forming a portion of the data stream. The control unit may be further configured to cause the sequence of data to be conveyed on the peripheral bus.

Abstract: An apparatus comprising one or more drive portions and a controller. The one or more drive portions may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to the one or more drives.

Abstract: A scanner, which can be a USB host, includes a hub, a scanner component, a virtual printer component and an internal host. The hub is connected to a computer host and the scanner. The scanner component stores the basic setting data of the scanner, while the virtual printer component stores the basic setting data of a printer, and both the scanner component and the virtual printer component are connected to the hub. The internal host is respectively connected to the scanner component, the virtual printer component and the printer. With the virtual printer component and the internal host, the scanner can be the USB host, which directly controls the printer to print.

Abstract: A system and methods are shown for accommodating high-speed data retention. Multimedia packetized stream data packets are received through a receiving hardware system. Program Specific Information and System Information data tables describing the programs and information in the packetized stream are sent as section packets within the packetized stream. Various fields are included with the section packets describing such information as the portion of the data table represented, the type of data table represented, and the version of the table represented. A host system configures the section parser to identify and pass only the section packets with the fields it specifies. The section parser then compares the fields to the configured values and determines whether to pass the packets to the host system or to discard the packets. Accordingly, processing overhead conventionally left to the host system is performed through the section parser.

Abstract: A SCSI selective options message delay expander includes a capability for monitoring messages transferred between a first port and a second port of the expander, for delaying a pre-selected message, for modifying the delayed pre-selected message, and for storing information obtained from the delayed pre-selected message. The ability to change messages allows the expander to be used with SCSI initiators and/or SCSI target devices that have SCSI characteristics different from the SCSI characteristics of the expander.

Abstract: A method for solving intermission of streaming data. A digital controller is used to transmit streaming data stored in a storage unit. The digital controller includes a base recording unit and a trigger recorder. The method comprises steps of (a) writing an initial address of a streaming data to the base recording unit when the streaming data is being transmitted; (b) changing a content value of the trigger recorder, and proceeding to the step (a) and a step (c) simultaneously; (c) transmitting a corresponding streaming data according to one of the initial address(es) stored in the base recording unit by the digital controller; and (d) proceeding to the step (c) when the trigger recorder indicates that there are data remained to be transmitted.

Abstract: The present invention provides a method and apparatus for a scheduling driver to implement a protocol using time estimates for use with a device that does not generate interrupts. An application calls the scheduling driver to start an Input/Output (I/O) request to a device. The scheduling driver determines if the device is busy. If the device is not busy, the scheduling driver provides an estimated processing time (EPT) for the I/O request to be completed to the application. In one embodiment, if the device is busy, the scheduling driver calculates an estimated amount of time left (EATL) until the device will be available to the application and provides this EATL to the application. When the device is not busy, the application sleeps for the estimated processing time (EPT) and calls the scheduling driver to obtain the I/O operation results. If the I/O request has been completed, the scheduling driver provides the I/O operation results to the application.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: A system, method and computer program for smart card with memory is disclosed. A very low cost approach to embodiment is disclosed, making use of a micro-controller with a FLASH memory or a WORM memory. An approach to programming a flash memory under the control of instructions within that memory itself is disclosed. In utilizing the invention, it is possible to build smart cards at a lower cost than heretofore.