Abstract: A data transmission method is provided for a medium access control (MAC) of a mobile telecommunication system. Each logical channel may transmit a response field to the transport channel. The response field may represent a data characteristic and an amount of data having a corresponding characteristic. This may be transmitted with the response field representing a data amount of a buffer. The transport channel may perform a TFC selection based on priorities of each logical channel and the data characteristic.

Abstract: A method and system for allocating logical paths between a host and a controller in a virtual data storage system such that the loads on the logical paths from storage devices are distributed evenly across the logical paths. When a connection request for connecting a storage device to the host is received by the controller, the controller counts an amount of queued connection requests from the storage devices to the host on each logical path. A logical path for the new connection request is then selected as a function of the amount of queued connection requests on each logical path and the current input/output activity on each logical path. The controller selects the logical path void of current input/output activity that has the lowest amount of queued connection requests to be the selected logical path. The controller then associates the new connection request with the selected logical path.

Abstract: An information reproducing apparatus can have access to an information providing apparatus for providing information via a network and has an information reproducing device for reproducing program information recorded on a recording medium. The information reproducing apparatus acquires identification information corresponding to the program information recorded on the recording medium. It transmits the acquired identification information to the information providing apparatus via the network when the program information recorded on the recording medium is reproduced. Then, it receives related information composed of at least any one of accompanied information related the program information and advertisement information related the program information or the accompanied information via the network, the related information being transmitted from the information providing apparatus according to the identification information.

Abstract: A communication system having a controlled device (105), for which an abstract representation (AR) (107) is provided as interface on a controlling device (103). When the quality of the connection between the controlling device (103) and the controlled device (105) drops below a predetermined level, or if some similar criterion is met, the system selects a second controlling device (104) which is better suited for controlling the controlled device (105) and generates a migration event to indicate this. The first controlling device (103) transfers control over the controlled device (106) to the second controlling device when it receives said migration event. This can be done by uploading the AR (107) to the second controlling device (105), possibly supplemented with the current state of the AR (107) to perform a fully transparent transfer.

Abstract: In a computer (e.g. an 80×86-compatible personal computer) in which peripheral devices (e.g. hard drives, floppy drives, CD-ROMs, etc.) are accessed through more than one chain of handlers for the peripheral devices (e.g. via interrupts 13h and 40h), an improved device handler for a peripheral device (e.g. a device that complies with the “El Torito” standard) is inserted in both chains (e.g. by “hooking” both interrupts 13h and 40h), so the device handler cannot be bypassed when an access request directed to the device handler is passed through either chain and so the device handler can direct the access request to the next device handler in the correct chain, when appropriate.

Abstract: The present invention is a method and apparatus to self update a firmware device. A communication interface receives programming information. A parser coupled to the communication interface to parse the programming information into control commands and program data.

Abstract: A method for scheduling execution sequence of read and write operations is disclosed, which is used for controlling the read and write operations between a first device and a second device. First, if there are more than two write operations waiting to be executed, the write operations are executed only after the completion of all of the read operations. If there are no more than two write operations waiting to be executed and there are read operations waiting to be executed, all of the read operations are to be executed when the read operation to be executed is associated with a data address different from the data address associated with the write operation next to the read operation. After all of the read operations are executed, the write operations are to be executed.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: Bus control apparatus solves the problem that a high-speed bus which supports only burst transfer cannot be used when the boundary of a transfer memory address is not coincident with a unit boundary. A scanner controller and printer controller connected to a G bus capable of performing only burst transfer and a B bus capable of performing even single transfer determine from the address and data length of data to be transferred whether the data does not match the memory boundary. If the data does not match this boundary, a data portion which is not accommodated within the burst transfer unit is single-transferred using the B bus. A data portion which is accommodated within the burst transfer unit is burst-transferred using the G bus.

Abstract: An accelerated filesystem includes a fast-path and a slow-path. The fast-path includes an enhanced storage controller and an enhanced network processing function. Uncontested READ and WRITE operations are processed on the fast-path. A READ session is initialized by obtaining file-storage metadata that is tagged with a session ID. The session ID is provided to the enhanced network processing function, and to the application as a file handle, and the tagged metadata is provided to the enhanced storage controller. Subsequent access is facilitated by communicating the file handle from the application to the enhanced network processing function, which passes the file handle to the enhanced storage controller in response. The enhanced storage controller executes a file handle to block list translation by employing the tagged metadata to retrieve the appropriate data. The retrieved data is transmitted to the application via the enhanced network processing function.

Abstract: A disk array control device includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention, the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

Abstract: In order to enable a pointer register device including registers called shadow registers to conduct updating operation rapidly by arithmetic operation of a pointer value between the registers, a front/back register set includes a first register and a second register. A switch control section allows a read select switch and a write select switch to select different registers. When the read select switch selects the first register and the write select switch selects the second register, the sum obtained by an adder can be stored in the second register while retaining the pointer value of the first register. In this case, the pointer value need not be transferred between the registers.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: A device, system and methods of data management are disclosed, which facilitate the implementation of improved mirroring, back-up, volume remapping, extent relocation, prefetching, caching, data reformatting, statistic gathering, and data translation, among others. A new, intelligent I/O stream splitter is disclosed that may intercept and alter an I/O stream received by the splitter from a communications link. For example, in the case of mirroring, the intelligent splitter may intercept write commands and associated data from a mainframe that target a specific storage location on a specific control unit. The splitter may then transmit the intercepted I/O stream to the targeted control unit and storage location over one link and in parallel transmit on another link an altered version of the intercepted I/O stream to another control unit, which is responsible for holding a mirrored version of the data.

Abstract: The present invention relates to an asynchronous interface for communication between two devices. It comprises signalling lines and at least eight data lines and is especially suitable for connections over short distances the interface provides a signal ground line, power supply line, power supply ground line and seven signalling lines between the two devices. The present invention also presents a method for communication by an asynchronous interface. The method comprises a procedure for changing the transmission direction from a forward direction to a reverse direction, a procedure for transmitting data in the reverse direction and a procedure for changing back the transmission direction to the forward direction from the reverse direction.

Abstract: A reporting system capable of reporting the end of a scanning session to a user through existing computer peripheral devices is proposed. By reporting at the end of a scanning session, the user can proceed with subsequent scanning operations with no delay. Hence, idle time of the scanner is greatly reduced.

Abstract: An external storage device including first and second input/output units for performing input/output of information from/to an outside, a plurality of storage units connected between the first and second input/output units so that a transmission path of information forms a series connection, and a configuration control unit. The configuration control unit selects two adjacent units from the first input/output unit, each of the plurality of storage units, and the second input/output unit to set a boundary between the two units. Thus the configuration control unit causes the storage units located on a first input/output unit side of the boundary to communicate with the outside by using the first input/output unit and causes the storage units located on a second input/output unit side of the boundary to communicate with the outside by using the second input/output unit.

Abstract: An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.

Abstract: Provided is a method, a computer program product, and a computer system each of which features queuing data transfers between a data port and a system memory to minimize the latency between queuing a data transfer and effectuating the transfer of the same and to remove the chance of more than one device trying to talk to the OS at the same time through the same port. This facilitates backwards compatibility of non-USB compatible computer resources, such as applications, operating systems (O/S) and the like, with USB compatible peripheral devices.

Abstract: Disclosed is a codec (coder/decoder) system with shadow buffers and method of performing a Power Down/Suspend mode operation on this codec system, which allows all the codecs in the codec system to know the operating status of each other so that system crash can be prevented during a power down/suspend operation. The codec system includes two or more codecs and associated codec controllers, with each codec controller including a status data buffer and a shadow buffer; and each codec controller utilizes the status data buffer therein for registering the operating status thereof and meanwhile utilizes the shadow buffer therein for storing a copy of the operating status data stored in the status data buffer of the other codec controller. The provision of the shallow buffers allows all the codecs in the codec system to be capable of knowing the operating status of each other. This feature can help prevent system crash during power down/suspend operation.

Abstract: The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Abstract: Embodiments of a method and apparatus are described which provide for a consistent, continuous and/or repeating signal. Such a repeating signal may be used to set the controls for a processor. For example, an embodiment of a preview sampler described herein allows a user to repeatedly output a data segment into a processor so that the processor can be adjusted to achieve a desired effect. Such a method and apparatus provides improved results when compared to an individual attempting to repeatedly generate a data signal (e.g., a note or chord on a musical instrument).

Abstract: A multi processor system includes a first processor having a data input terminal and a data output terminal, which first processor is programmed so as to decide destinations to which data items successively input from an input terminal thereto should be delivered and deliver the input data items to the decided destinations, and a plurality of second processors, each of which has a data input terminal and a data output terminal and is programmed so to execute a predetermined process on data items delivered from the first processor. A FIFO circuit includes a memory portion, a write pointer assigned to a first master; and a plurality of read pointers each of which is assigned to one of a plurality of second masters.

Abstract: Apparatus and method for PCI bus extension, via a PCI bridge circuit, as well as PCI device function, via a PCI device circuit and I/O connector, all on a single I/O card. Further, the present invention provides for stackable, partial-height PCI cards. Further, provided are stackable, partial-height I/O card mounting plates. In yet another embodiment, a functional PCI extension card also provides one or more right-angle connector sockets in order to allow multiple additional PCI cards at right angles to the functional PCI extension card.

Abstract: Digital pixel data is transferred from a computer system to video display hardware in a forward direction. However, there are many reasons for digital pixel data to be transferred in both directions along a cable connecting a computer and a monitor. This invention describes a method of sending digital data from a monitor back to the computer in a reverse direction. In transmission of digital pixel data in a forward direction, there are horizontal and vertical blanking periods during which special characters are transmitted in order to resynchronize the digital pixel data to a clock signal. In such a system the transmission of these special characters only requires a portion of the blanking periods. During the remainder to the blanking period, some of or all of the data paths can be used in order to transmit digital data in a reverse direction. Where all data paths are used, the beginning and end of the usable portion of the blanking periods may last for a fixed number of clock cycles.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses, using a bypass of the memory array.

Abstract: The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a bi-directional data bus for conveying plural bits of data or command between a master controller and one or more client controllers; direction signal controlling the direction in which data or command bits are conveyed on the data bus as between the master controller and a connected one of the one or more client controllers; a pair of ready signals including a transmit ready signal asserted by a source of data or command bits placed on the data bus and including a receive ready signal asserted by a destination for the data or command bits placed on the data bus; and a clock signal for indicating the presence of valid data or command bits on the data bus on a leading or trailing edge thereof. Preferably, a command/data signal is also provided to indicate the type of information placed on the data bus by the source.

Abstract: A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means,for executing a first DMA transfer from said first stream storing means to said main storage unit; first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity; a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit; second stream storing means for storing the second stream of said main storage unit; second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and second DMA transfer controlling means for controlli

Abstract: A call made with a communication device is processed using multiple call processors (CPs) operatively connected to a network. CPs use processing load information from other CPs to select which CP will handle call set up when the call is requested. A similar selection process is used for selecting one of CPs to perform other call processing functions and to terminate the call upon receiving a request to terminate the call. The CP selected to set up a call, tear-down a call or perform other call processing depends on the load associated with the processor and the load associated with setting up, tearing down performing other call processing for the call.

Abstract: A method for transferring data (for example, image data) from disk storage directly to a peripheral device (for example, a pelbox) in which address information identifying disk storage locations where the data is stored is sent to the peripheral device, and a command is sent to the peripheral device to initiate data transfer from disk storage directly to the peripheral device using the address information received by the peripheral device.

Abstract: A reception apparatus or transmission and reception apparatus has a plurality of input terminals, and a plurality of apparatus are connected by a chain connection to a predetermined one of the input terminals. The input terminal at which the apparatus is to receive a signal is successively switched among the input terminals by selection operation of a user, and the apparatus connected to the predetermined input terminal are successively searched in response to the same selection operation of the user.

Abstract: A method of transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data to other devices in the computer system. The computer system identifies, from a plurality of responding devices within the computer system, a target device that contains the data. In response to a determination that the target device does not support higher-performance transactions, the computer system disables higher-performance transactions and transfers the data to the requesting device via a lower-performance transaction process.

Abstract: A method and system which will provide data processing systems having memory controllers with the ability to intelligently schedule accesses to system memory. The method and system provide a memory controller having a page-state sensitive memory arbiter. The method and system further include one or more memory state tracking units operably coupled to the page-state sensitive memory arbiter, and the one or more memory state tracking units operably coupled to a system memory. The one or more memory state tracking units operably coupled to a system memory further include the one or more memory state tracking units operably coupled to one or more system memory devices. The method and system track system memory status, monitor pending memory access requests, and schedule one or more pending memory access requests for execution dependent upon the system memory status and the pending memory access requests.

Abstract: A data processing apparatus that efficiently performs processing of a transmission job with a plurality of destinations includes an inputter, a discriminator, and a processor. The inputter inputs an instruction for a transmission job. The instruction includes a plurality of destinations and information indicating a transmission type. The discriminator discriminates whether or not the transmission type corresponding to the information included in the inputted instruction is a type for which the plurality of destinations should be processed in a batch. When it is discriminated that the plurality of destinations should not be processed in a batch, the processor divides the transmission job into a plurality of jobs.

Abstract: A multi-design integrated circuit having I/O buffers that are shared by multiple designs in the integrated circuit, the multi-design integrated circuit being designed by combining netlists and pin-pad assignment lists for the individual designs into one overall netlist or multi-design netlist.

Abstract: An input/output (I/O) module has a programmable memory having a first memory address for receiving a module number and a second memory address for receiving a signal direction indicator. The I/O module is for use with a programmable controller system having a master controller serially connected to a plurality of I/O modules. The I/O module has a signal line operatively coupled with the memory. The signal line has a pair of inputs. Both inputs are configured and adapted for receiving a module number signal across a line connected therewith. The other one of the inputs will then propagate the module number signal downstream. A logic circuit sets the second memory address with the signal direction indicator corresponding to the module number signal being received by a particular one of the inputs.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: An address translation arrangement and associated method for use in a digital system are described. The system includes a plurality of modules and a bus arrangement which interconnects the modules for executing data transactions using the bus arrangement. Each data transaction includes an address portion which defines a data portion. A first one of the modules is configured for initiating the address portion of the data transaction on the bus arrangement.

Abstract: A master/slave control system and method of communicating messages between a master controller and slave devices, especially for use in a vehicle. The system includes a data communication bus, a plurality of slave devices coupled to the data communication bus which are addressable and capable of reading messages broadcast on the data communication bus and broadcasting reply messages to the data communication bus, and a master controller coupled to the data communication bus for broadcasting command messages. The command messages include an address for addressing at least one of the plurality of slave devices and a direction indicator parity bit for identifying the command message. The addressed slave device produces a reply message which includes a reply direction indicating parity bit for identifying the reply message.

Abstract: In a system in which data transfer interfaces respectively of apparatuses are connected via a bidirectional bus to each other, the availability ratio of the bus is improved. An apparatus to issue read and write requests includes a write buffer to store write data and a bus changeover unit to monitor an operation status of the bus for a read data transfer. The apparatus immediately sends a read request via the bus to a communication partner and then receives read data via the bus from the partner. A write request and associated write data are once stored in the write buffer. When a predetermined number of write data is accumulated, a data transfer direction of the bus is changed if the bus is not being used by a read data transfer to successively transmit the write requests and write data thereof to the partner.

Abstract: A tenant processor module is shown comprising a processor core, a plurality of strapping devices, and an input bus. The plurality of strapping devices are configured to indicate configuration information to a receiving circuit board assembly coupled to the processor module. The input bus, coupled to the processor core, receives the configuration information back from the circuit board assembly and provides them to the processor core at a first time. At a second time, the input bus receives operational data from the circuit board assembly and provides them to the processor core.

Abstract: Direct memory access controller (DMAC) (54) adapted to directly execute C language style FOR tasks assigned by a processor (70), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) (88, 90, 92), each to perform an arithmetic or logical operation, and a FOR task controller (80, 82, 86) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

Abstract: Circuit, apparatus, method, and signal set for sending and controlling bi-directional data flow between a microprocessor (or other device) and a peripheral device having a standard UART-based, SPI-based, or similar interface over a single input/output (I/O) port line, utilizing the differences of the instantaneous source impedance of the I/O port line operating with data in and data out states. Circuit, apparatus, method, and signal set for separating the 1-wire data into standard 2-wire and 3-wire UART-based, SPI-based, or similar interfaces for use with unmodified peripheral devices. The exchange of data on a bit-by-bit or analog basis, with insignificant return delay, allows operation independent of any signaling protocol.

Abstract: An output data path scheme including a feedforward portion may be configured to drive a data signal from a selected local bus line onto a global bus and a feedback portion may be configured to drive the data signal from the global bus onto a deselected local bus line. A first sense amplifier may be configured to drive the data signal onto the selected local bus line. A second sense amplifier may be coupled to the deselected local bus line and may be configured to tristate.

Abstract: Apparatus and method for PCI bus extension, via a PCI bridge circuit, as well as PCI device function, via a PCI device circuit and I/O connector, all on a single I/O card. Further, the present invention provides for stackable, partial-height PCI cards. Further, provided are stackable, partial-height I/O card mounting plates. In yet another embodiment, a functional PCI extension card also provides one or more right-angle connector sockets in order to allow multiple additional PCI cards at right angles to the functional PCI extension card.

Abstract: The invention prevents data transfer in a computer network from being sent via a path incapable of transfer or of poor data transfer efficiency. A central processing unit, a main memory unit, and storage devices for storing data and data processing devices are connected in the network, and the data is transferred mutually between the storage devices and the data processing devices without passing through the central processing unit or the main memory unit. The apparatus includes a data transfer control module that identifies the capability/incapability of data transfer based on the physical positions of the storage devices, the physical positions of the data processing devices, and the transfer paths incapable of data transfer. The volume management module specifies a combination of storage devices capable of data transfer based on the physical positions of the storage devices, the physical positions of data processing devices, and the transfer paths capable of data transfer.

Abstract: A method for transmitting data between a microprocessor and an external memory module through external package pins of the microprocessor, which includes the steps of: a) deciding N-bit full sized data to be transferred by using M, wherein N and M are positive integers and N is greater than M; b) sequentially transferring N/M number of M-bit divided data; c) temporarily storing N/M number of M-bit divided data; and d) combining the N/M number of M-bit divided data into the N-bit full sized data.

Abstract: A host computer logs in an image providing device such as a scanner connected by a serial bus, and reverses flow control of data transfer by issuing a Reverse command. The image providing device opens a transfer channel by an OpenChannel command, transfers image data in form of blocks. When the transfer of the image data has been completed, the image providing device closes the transfer channel by a CloseChannel command, and reverses the flow control of the data transfer again by the Reverse command. This changes the data transfer direction of a device having a bi-directional data transfer function, i.e., a device having a data reception function and a data providing function.

Abstract: There is disclosed a configuration for multiplexing the USB signals onto the IEEE 1284 signals thereby allowing a single connector on the device to support either protocol. Within the device, each protocol block is connected to transceiver to compensate for differences in driver/receiver characteristics for the protocol. The outputs of the transceivers are connected to a signal conditioner to allow proper selection of termination impedance. A controller senses whether a passive adapter is attached to the connector. When the passive adapter is not connected the controller selects the 1284 protocol and its associated transceiver and signal conditioning. If the passive adapter is connected, the controller selects the USB protocol and its associated transceiver and signal conditioning. The passive adapter connects pre-selected pins on the device's connector to a USB connector. There is also described an arrangement to allow the passive adapter and device to provide USB hub functions.

Abstract: A method and apparatus for extracting data from a stream of data includes processing that begins by receiving at least one bit of data from a bit stream of data. The bit stream of data represents packetized data that is formatted based on a data packetizing protocol (e.g., HDLC encapsulated data packetizing formats). Next, a data packet associated with the at least one bit is identified based on time occurrence of receiving the bit. Next, the status of the data packet is determined based on the time occurrence of the bit and the data packet (e.g., the content of the data contained within the data packet and/or the bit). The processing continues by extracting data from the at least one bit based on the status of the data packet and the content of the bit. Next, the processing updates at least a portion of the status of the data packet based, at least partially, on the content of the bit.