Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: A method and apparatus in a data processing system for generating a metadata stream. A request is received to render an object. A determination is made as to whether a device hint associated with the object is present. The object is placed in the metadata stream. The device hint is placed in the metadata stream, responsive to the device hint associated with the object being present. Then the device can take advantage of the hints without requiring it to preprocess the set of objects.

Abstract: A method and apparatus are provided for bidirectionally transmitting a plurality of data values between a first processor and a second processor. Each data value represents a respective plurality of data bits. A direction indicating signal is formed and transmitted from the first processor to the second processor. The direction indicating signal enables the second processor to transfer data to the first processor when the direction indicating signal is in a first state. The direction indicating signal notifies the second processor that the first processor is ready to transfer data to the second processor when the direction indicating signal is in a second state. A clock signal is formed and transmitted from the first processor to the second processor. The clock signal is asynchronously changed from a first state to a second state when each respective one of the plurality of data values is transferred.

Abstract: A method and apparatus for providing modular I/O expansion. Apparatus are provided on a host computing device and an expansion unit to support multiple port types, and multiplexing apparatus are provided to support simultaneous I/O sessions between multiple applications on the host computing device and multiple I/O ports on the expansion unit over a single host I/O port. The expansion unit is equipped with one or more port interface modules that are each configured to support data transmission in accordance with one port type from a set of port types. Apparatus on the expansion unit perform multiplexing and demultiplexing of data transmitted between the host computing device and the port interface modules of the expansion unit. Port interface objects in the host computing device each support data transmission in accordance with one port type from the set of port types.

Abstract: A modem interface communicates data between a computer and a modem that is coupled to an external communication network. The modem interface includes a host interface for coupling to a host processor of the computer, an analog interface for coupling to the modem, and a digital signal processor for processing the data communicated with the modem and the host processor. A memory is coupled to the host interface, the digital signal processor and the analog interface. The analog interface provides clock signals and converts data between analog and digital for communicating between the memory and the modem. The analog interface provides an interrupt to the digital signal processor to control the transfer of data from the digital signal processor and the memory. The modem interface processes data at sampling rates while the host processor processes data at rates less than the sampling rate of the analog interface.

Abstract: A method and apparatus for reconfiguring a file or logical volume stored on a magnetic disk storage system for optimal performance. The magnetic disk storage system contains a cache volume constituted as free storage. When appropriate, a file can be copied from its normal storage location to the cache volume with a different format to optimize the file for subsequent operations. After such operations are complete, the file can be transferred from the cache volume back to the normal storage location in the original format.

Abstract: A method and apparatus for processing data in a computer system from a keyboard wedged device and a keyboard hook device. The keyboard wedge converts the data into standard keyboard keystrokes for transmission over a keyboard line. The keyboard hook provides a window through which scanned data is detected. Scanned data is distinguished from typed data using a software data processing application. The software is configured to identify scanned data based on characteristics of the scanned data. Processing functions are next performed on the detected data according to the particular application being used.

Abstract: A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.

Abstract: A method and apparatus for transferring data associated with synchronous transfer mode (STM) calls through an asynchronous transfer mode (ATM) network are described. The apparatus includes a voice interface control unit, a signaling interface and a TDM peripheral device associated with each edge node in the ATM network. The voice interface control unit controls the ingress and egress of STM calls to the network. The signaling interface sends and receives common channel signaling messages associated with calls originating in the STM network and passes message content to the voice interface control unit. The TDM peripheral device converts STM network and passes message content to the voice interface control unit. The TDM peripheral device converts STM calls to ATM cells, and vice versa.

Abstract: A serial port is shared by a microcontroller and a host application. The microcontroller initially responds to a remote user making connection to the serial port. Upon the remote user requesting connection to the host application, a hardware switch connects a serial port connector to serial port hardware utilized by the host application. The connection between the remote user and the host application is monitored, so that when the connection between the remote user and the host application is discontinued, the serial port connector is reconnected to the microcontroller.

Abstract: A system and method for manufacturing a hard disk master for copying a hard disk are provided. The manufacturing system includes a server computer and a client computer for logging in on the server computer and generating the hard disk master. The server computer includes a program storing portion for storing programs and drivers, a user interfacing portion for selecting the programs and drivers required by the hard disk master and for storing the selected programs and drivers, a setup file generating portion for generating information on the selected programs and an order in which the programs and drivers are installed, and a script file generating portion for generating information on the setting of the hardware environment and operating conditions.

Abstract: A data processing system includes a bus, one or more loads coupled to the bus, and a clock generator. The clock generator generates a bus clock signal that is coupled to at least one of the loads. While the clock generator is generating a bus clock signal having a first frequency, the number of loads connected to the bus is determined. In response to this determination, the frequency of the bus clock signal is automatically changed from the first frequency to a second frequency. In one embodiment in which the bus is a PCI local bus having a plurality of slots, the determination of the number of loads is made by examining at least one storage location associated with each of a plurality of slots.

Abstract: A method and apparatus for transporting data include processing that begins by receiving a bit stream of data at a rate of at least a bit per input interval. The bit stream of data corresponds to ingress packetized data that has been packetized based on one of a plurality of data packetizing protocols (e.g., HDLC encapsulated data, frame relay, PPP, and/or SMDS). As the bit stream is received, the data is extracted from the bit stream to produce extracted data, which is stored in ingress local memory. When a sufficient amount of extracted data is stored in the ingress local memory (i.e., an ingress data word is stored), it is transported to a non-local memory, where the transporting is based, at least in part, on content of the ingress data word. The processing also includes transporting stored egress data words from a non-local memory to an egress local memory based, at least in part, on content of the egress data words.

Abstract: A new distributed control mechanism for managing bi-directional interfaces of symmetrical multiprocessor systems in such a manner as to minimize the latency to storage, yet fairly distribute the use of the interfaces amongst the various components. This bi-directional interface can be designed to perform with differing characteristics depending upon the direction of information flow. These characteristics are implemented into the control logic of the source and destination components interconnected by the bi-directional interface, thus yielding two interface behaviors using only one interface. Each component is able to track the state of the interface by using only its own request state in conjunction with the detected request state of the opposing component, when both units are operating under the joint control algorithm present in the control logic of the source and destination component.

Abstract: A system and method are provided for remotely managing memory in a programmable portable information device, such as a programmable watch, from an external computer. The portable information device has an optical sensor and a rewritable data memory. The computer has a frame-scanning graphics display device and a memory with a capacity larger than that of the device memory. The device memory is mapped into a portion of the computer memory to create a virtual device memory therein. An input device for the computer is provided to permit a user to enter programming changes to be made to the information device,. The programming changes alter the virtual device memory within the computer memory from an initial arrangement to a modified arrangement. Upon modification, a memory manager resident in the computer determines what memory transactions are effective to change the virtual device memory from its initial arrangement to its modified arrangement.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A method, apparatus and article of manufacture for hardware independent system level control of storage units in an array is disclosed. The method comprises the steps of scanning the array of storage devices to find available I/O paths, storing a list of available I/O paths to each storage device in a memory, receiving an I/O request directed at a virtual disk memory location, mapping the virtual disk memory location to a corresponding storage device, selecting an I/O path for the I/O request from the list of available I/O paths in stored in the memory, and transmitting the I/O request to the storage device over the selected I/O path. The apparatus comprises a virtual disk driver functionally coupled between the computer and the disk array with a core driver and a subordinate driver customized for storage device arrays from different hardware vendors. Selection of the subordinate driver is accomplished via a switch table stored in the computer memory.

Abstract: A modem interface communicates data between a computer and a modem that is coupled to an external communication network. The modem interface includes a host interface for coupling to a host processor of the computer, an analog interface for coupling to the modem, and a digital signal processor for processing the data communicated with the modem and the host processor. A memory is coupled to the host interface, the digital signal processor and the analog interface. The analog interface provides clock signals and converts data between analog and digital for communicating between the memory and the modem. The analog interface provides an interrupt to the digital signal processor to control the transfer of data from the digital signal processor and the memory. The modem interface processes data at sampling rates while the host processor processes data at rates less than the sampling rate of the analog interface.

Abstract: A digital data transfer system transfers digital data along a path in a ring topology. The digital data transfer system comprising a host controller and a digital data transfer subsystem. The host controller generates and receiving digital data and the digital data transfer subsystem receives the digital data from the host controller and transferring the digital data to one or more devices connectable thereto, and further receives digital data from the last of the devices connectable thereto for provision to the host controller, thereby to define the ring data transfer topology. The digital data transfer subsystem comprises an upstream port, a plurality of input/output ports and a port control. The upstream port transfers digital data from an external source to the input of the first input/output port in the series and transfers digital data received from the last input/output port in the series to the host controller.

Abstract: An initiator device, in a data processing system utilizing a Serial Storage Architecture subsystem, directs an I/O process via secondary path if a primary path is unavailable, even if the primary path is shorter. Also, an initiator device may send outbound data frames, on a secondary path, simultaneously with the SCSI command. Additional flexibility is attained by utilizing an adapter and target storage devices that all support Out of Order Transfers ("OOT"). If a target supports OOT, individual data frames that comprise an I/O process may be sent on multiple paths, allowing greater flexibility in routing. Also, an initiator device may send outbound data frames, on an alternate path, simultaneously with the SCSI command.

Abstract: A method and apparatus for reconfiguring a file or logical volume stored on a magnetic disk storage system for optimal performance. The magnetic disk storage system contains a cache volume constituted as free storage. When appropriate, a file can be copied from its normal storage location to the cache volume with a different format to optimize the file for subsequent operations. After such operations are complete, the file can be transferred from the cache volume back to the normal storage location in the original format.

Abstract: A compound control/data channel connects an I/O bridge (IOB) and a data buffer unit (DBU) in a high performance I/O subsystem. Generally, data movements among an I/O bridge, data buffer unit, system bus and I/O bus are dominated by separate control signal groups issued from the I/O bridge. The compound control/data channel permits integration of these control signal groups onto the data channel connected between I/O bridge and data buffer unit. A data controller can control and transfer data to/from a data buffer using this unique channel, alternately, for control information and data streams.

Abstract: A modem interface unit is provided for coupling a communications modem to a host processor. The modem interface unit includes a host interface for coupling to a host processor, an anlog interface for coupling to a communications modem and a digital signal processor for performing signal processing operations on modem signals as they are transferred from the host interface to the analog interface and vice versa. A memory is provided for use in moving the modem signals through the interface unit. A sleep mode mechanism is provided for discontinuing the supplying of operating current to the digital signal processor when no modem signals have been transmitted or received for a predetermined period of time.

Abstract: A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer system itself. The code usually implemented in the microcontroller is instead implemented as a virtual modem controller to be called by the operating system of the computer itself. Further, this virtual modem controller includes a virtualized UART, that appears to the operating system software as a hardware UART, and the operating system driver software need not even have its input and output instructions replaced. Instead, debug registers are provided as breakpoints whenever an input/output instruction is executed to the I/O port range at which the UART would normally appear.

Abstract: A dynamic allocation system and method is provided for allocating memory bandwidth associated with a store and forward memory communicating between a node processsor and a network. Dynamic allocation is controlled by a state machine in a network adapter, which monitors on a real time basis the active users of the network adapter memory, the node processor writing or reading adapter memory, the network sending port, and the network receiving port. Bandwidths are allocated to users with instant response to user bandwidth demand changes. Programmable options allow a node processor to control bandwidth allocations for various user scenarios.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: Many digital processors have an asynchronous bus controlled by two control signals. To interface a synchronous memory to an asynchronous bus, interface logic is required. In an interface for transferring data from an asynchronous circuit to a synchronous circuit, data to be written are written in an intermediate register while timing control signals are being synchronized to a system clock by means of flip-flops. Correspondingly, in an interface for transferring data from the synchronous circuit to the asynchronous circuit, a signal indicating a read transaction from the synchronous circuit is synchronized to the system clock by means of a flip-flop circuit.

Abstract: A modem interface communicates data between a computer and a modem that is coupled to an external communication network. The modem interface includes a host interface for coupling to a host processor of the computer, an analog interface for coupling to the modem, and a digital signal processor for processing the data communicated with the modem and the host processor. A memory is coupled to the host interface, the digital signal processor and the analog interface. The analog interface provides clock signals and converts data between analog and digital for communicating between the memory and the modem. The analog interface provides an interrupt to the digital signal processor to control the transfer of data from the digital signal processor and the memory. The modem interface processes data at sampling rates while the host processor processes data at rates less than the sampling rate of the analog interface.

Abstract: Method and apparatus for selectively enabling a pull device coupled to a multiplexed terminal connector based on the function of the terminal connector. When the terminal functions as a general purpose input/output (GPIO), the pull device is enabled on reset or on setting a control bit. For operation as a data port, the pull device is disabled, and on reset the pull device is enabled only after any pending data transaction has completed. Upon completion of the reset period the pull device is again disabled for data port operation. In one embodiment, a terminal has a first interruptible function and a second uninterruptible function. The terminal is coupled to a pull device and control logic. If the second function is active, the control logic enables the pull device with a time delay sufficient that the second function is completed prior to the enabling of the pull device.

Abstract: If consecutive read or write requests imposed on a DASD are of the same type and bear a defined sequential logical address relationship (pure sequential, near sequential), then a circular buffered data path using a pair of a synchronously managed read/write ports respectively coupling either a cyclic, concentric, multitracked storage medium or a cyclic, spiral-tracked storage medium and a device interface can continue data streaming unabated. Otherwise, the path would ordinarily have to be disabled and reconnected using a control microprocessor in respect of any random sequence of requests.

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: A bidirectional communication method, bidirectional communication device and storage medium for automatically setting the communication mode without complications to the user and not causing the malfunctioning of the computer system and the printer are disclosed. The control register of the personal computer is used to set data reception from the laser printer in a byte mode. A specific data is written to the data register, and the value of the data register is read. If the value of the data register is not the specific data, it is recognized that the personal computer can be set to the byte mode. If, on the other hand, the read value of the data register is the specific data, another specific data is written to the data register, then the value of the data register is read, and if the value of the data register is another specific data, it is recognized that the personal computer cannot be set to the byte mode.

Abstract: A system and method for providing multiple modes of parallel communications between a host and a peripheral. In the system and method, a driver provides support for a plurality of transfer modes while satisfying the streams requirements of a host kernel during both forward and reverse transfers. The driver begins in a known mode and negotiates the host and peripheral into a best mode supported by both the host and the peripheral. The driver satisfies streams requirements, thereby permitting high level handshaking and use of ioct1s in UNIX based systems. When data is to be transferred, a message is placed on a queue to be serviced in the order received. The type of the message is indicative of the direction of the desired transfer. Each message is serviced in turn, and the transfer conducted using the most efficient mode available.

Abstract: This invention relates to a system and method for adapting the ports of computing elements in transferring data between computing elements on a network. Ports of the computing elements are interconnected for data transfer through a switch complex. The interconnected ports are adapted to cooperate together in transferring the data. Data which is ordinarily designated to be transferred through one port of a computing element may be transferred through a different port.

Abstract: A high speed data transfer apparatus includes a data transfer controlling unit for outputting a signal to the standby mode system during the active mode system, and during the standby mode system, reading data and the data information stored in the second storing unit of the active mode system, storing the read contents in the second storing unit of the standby mode system, and transferring a right to a bus use through the local bus of the standby mode system, the signal being used for informing that there exists data to be transferred.

Abstract: A programmable configuration selector is provided to an apparatus having at least one configurable device. The programmable configuration selector comprises a non-volatile memory having at least one storage register for storing configuration information corresponding to the at least one configurable device, and a multiplexer driver. The multiplexer driver comprises at least one output port coupled to the at least one configurable device, for asserting configuration information, received from the non-volatile memory, on the at least one output port to configure the at least one configurable device at a first time, and for asserting operational data, received from a data bus, on the at least one output port to the at least one configurable device at a second time.

Abstract: A data transfer system includes a host which provides a timing signal and data at an output, and a peripheral device which receives the timing signal and data from the host output, and produces an internal timing signal based on detection of a change in either the data or the polarity of the timing signal provided by the host.

Abstract: A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.

Abstract: A programmable direction control scheme for an efficiently wired array of like integrated circuit chips which is capable of producing a rightward or leftward sequence of designated interaction is described. The member chips are incorporated into a system by connecting their existing addressing, data, and clock pads onto a mutual bus. The chips are additionally chained together by their qualification pads so that they may be individually designated for interaction with the system, by way of sequential token passing. A direction control bit within a programmable configuration register is included on each member chip in lieu of a dedicated input. The configuration register is given free access irrespective of the designation status of its incorporating chip, and thus the direction control bits of all of the member chips of the array may be expediently programmed even when the elsewise process of sequencing through the chips would be paradoxically self obstructed by an initial directional chaos condition.