Abstract: According to one aspect there is disclosed an apparatus. The apparatus may include a first device.

Abstract: An information processing system includes a plurality of processors for executing processing according to a predetermined processing request sent from a different device; a switching device for performing data transfer between the individual processors and the different device; and a storage device which is connected to the switching device and enables data transfer to and from the individual processors. At least one of the processors includes a processing request storing unit for storing processing request data sent from the different device to the processor, into the storage device by data transfer. At least another one of the processors includes a processing request reading unit for reading the processing request data stored in the storage device from the storage device by data transfer.

Abstract: The invention relates to an electronic system having at least one host processing electronic device and at least one peripheral electronic device. The peripheral electronic device performs at least two functions. The host processing electronic device and the peripheral electronic device are interconnected via at least one interface. The host processing electronic device and the peripheral electronic device communicate via a single, common, “multi-function” interface, so that the host processing electronic device and the peripheral electronic device exchange at least one item of data relative to each of the two functions via the multi-function interface.

Abstract: Described are techniques for performing path selection. A data operation is received for a metadevice comprising a plurality of metadevice members. A first of the plurality of metadevice members is determined. The first member is the member to which the data operation is directed. In accordance with a load balancing technique for the first metadevice member, path selection is performed to select a first of a plurality of paths. The metadevice is accessible over each of the plurality of paths. The data operation is sent over the first path.

Abstract: A device and a method for testing a DMA controller. The device includes: (i) a DMA controller that includes a first data transfer path and a second data transfer path, wherein the first data transfer path and the second data transfer path are mutually independent; (ii) a test unit, connected to the first and second data transfer paths, that is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data.

Abstract: An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed IHS video signal and IHS bus information is received by a display multiplexer, where it is demultiplexed. Demultiplexed IHS video signal information is received by a video interface receiver, where it is used to generate an image on a digital display. Demultiplexed IHS bus information is received by a host bus interface transmitter/receiver, where it is used to support peripheral devices attached to the digital display.

Abstract: Managing a data transfer from one or more source storage devices to one or more target storage devices. The data transfer comprises concurrent transfer of a multiplicity of data units pursuant to respective data transfer commands. The concurrent transfer of the multiplicity of data units is currently in-progress. A computer determines a currently-overloaded storage component involved in the data transfer. The computer determines a plurality of the data transfer commands that involve the overloaded storage component. The computer determines an approximately-minimum number of the data transfer commands to cancel to stop overload of the overloaded storage component. In response, the computer cancels the minimum number of the data transfer commands.

Abstract: Provided is a serial control device that makes the length of data transferred as one frame variable. The serial control device transfers serial data having an arbitrary length, and uses end information indicating inclusion or non-inclusion of end data of the serial data. The serial control device transfers data having a transfer unit length in the serial data when the end information indicates non-inclusion of the end data, and transfers an untransferred part of the serial data when the end information indicates inclusion of the end data.

Abstract: Methods and systems for advancing to another service from a plurality of services in a digital radio broadcast receiver are described. The methods and systems include the steps of receiving an instruction to advance to another service from a man-machine interface of the digital radio broadcast receiver, selecting an entry from a set of entries stored in a memory of the digital radio broadcast receiver responsive to the instruction, wherein each entry identifies a service, and wherein at least some of said services correspond to services identified as receivable, tuning to a first service identified by the selected entry, rendering content received on the first service at the digital radio broadcast receiver, and updating the set of entries stored in the memory of the digital radio broadcast receiver based on at least one criteria.

Abstract: A transfer-indication storage unit indicates an address and a data length of data to be transferred by a DMA circuit. An expected value table refers to a transfer indication of the transfer-indication storage unit and stores therein expected values of the address and the data length of the data to be transferred. A transfer-monitoring unit retrieves tag data and a data length of data in a bus. Based on the data length and the tag data notified by the transfer-monitoring unit, a table updating unit updates a start address and the data length in the expected value table. A determining unit determines whether the start address, corresponding to the DMA circuit after data transfer, matches with an end address, and further determines whether the data length has become zero.

Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract: An image input and output system is provided in which a common operation screen for a plurality of image output devices having different attributes is displayed. Based on attribute information of each of printers, the server generates a signal for generating an operation screen, and transmits the signal to the scanner. At the scanner, image data is inputted, and a common operation screen, which is generated based on the signal for generating the operation screen, is displayed on a display panel. When information designating the printer and information relating to an output format of an image is inputted from the display panel, the inputted information and the image data are transmitted to the server. The server transmits, to a designated printer, the image data and the information relating to the output format of the image, which are transmitted from the scanner, and images are outputted.

Abstract: A method for controlling a user station configured for communications with a multiplicity of independently-operated data sources via a non-proprietary network includes steps for providing a user interface to enable a user at the user station to select multiple ones of the multiplicity of independently-operated data object sources to be polled; automatically polling each of the selected data object sources in order to determine availability of desired data at each of the selected data object sources; and automatically transporting desired data determined to be available from each of the selected data object sources to the user station. Software and a user station for implementing the method are also described.

Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.

Abstract: In a presentation system, a source device provides uncompressed presentation content in an HDMI format. A first conversion device converts the uncompressed presentation content to an uncompressed second format and entirely transmits the uncompressed presentation content in the second format along an electrically conductive member. A second conversion device receives the uncompressed presentation content in the second format from the conductive member and converts the uncompressed presentation content to the HDMI format. For example, the conductive member may be that of a coaxial cable.

Abstract: A method, apparatus, and program product retrieve data for a task utilizing demand-based direct memory access (“DMA”) requests. The method comprises, prior to the execution thereof, analyzing a first portion of a task to determine whether data required for execution thereby is stored in a local memory, and, in response to determining that the data required for execution by the first portion of the task is not stored in the local memory, proactively issuing a first DMA request for the data required for execution by the first portion of the task. The method further comprises, in response to determining that the first DMA request is not complete, determining whether to proactively analyze a second portion of the task prior to the execution thereof for a determination whether data required for execution thereby is stored in the local memory.

Abstract: A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.

Abstract: Data processing arrangements including a channel adaptor shared by a plurality of operating systems (OS's) for data transmission/reception, coupled to the PCI bus on a PCI bus side of the channel adapter, and including only one connecting port on an input/output (I/O) side of the channel adaptor. An input/output process is executed between each OS and the channel adaptor by using input/output process control data specifying I/O data each having an identifier. Configuration information is provided, defining the identifier of the input/output process control data which is usable by each respective OS. The channel adaptor can process a plurality of input/output process control data; and each OS uses the input/output process control data corresponding to a usable identifier and defined in the configuration information, and thereby, a plurality of OS's control input/output process control data have different identifiers relative to the channel adaptor to execute the input/output process.

Abstract: An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

Abstract: A method, system and computer program product for providing driver functionality in computing system includes installing an operating system on the computing system; forming a plurality of isolated sandboxes running on the computing system under control of the operating system; during an attempt to install a driver, installing driver stub in the operating system; installing the driver in one of the isolated sandboxes, wherein the driver directly uses at least part of system resources; using a gateway between the driver stub and the installed driver to provide an interface for transmitting requests from the driver stub to driver.

Abstract: In accordance with one or more embodiments, a method and system of managing animation data and related control data for recording on an enhanced navigation medium is provided. The method comprises constructing animation data comprising first image data into a first graphic MNG file in chunk data format, wherein the first graphic file comprises a first header portion, a second end portion, first control data and a frame containing additional data; and recording the first graphic file on an enhanced navigation medium.

Abstract: A system, computer-implementable method, and computer-readable medium for improving sequential serial attached small computer system interface storage device performance. According to a preferred embodiment, a microprocessor within a target device receives a collection of tasks from at least one initiator device via a collection of initiator paths. The target device is a cyclic non-volatile memory medium. The microprocessor queues the collection of tasks according to a collection of task list. Each task list corresponds to a respective initiator path. The microprocessor combines the collection of tasks in an execution queue. The collection of tasks on the execution queue is reordered based on a priority scheme. The microprocessor executes the collection of tasks from the execution queue.

Abstract: Managing a data transfer from one or more source storage devices to one or more target storage devices. The data transfer comprises concurrent transfer of a multiplicity of data units pursuant to respective data transfer commands. The concurrent transfer of the multiplicity of data units is currently in-progress. A computer determines a currently-overloaded storage component involved in the data transfer. The computer determines a plurality of the data transfer commands that involve the overloaded storage component. The computer determines an approximately-minimum number of the data transfer commands to cancel to stop overload of the overloaded storage component. In response, the computer cancels the minimum number of the data transfer commands.

Abstract: Scheduling a proposed additional data transfer from one or more source storage devices to one or more target storage devices. A computer receives a request for the proposed additional data transfer, and in response, determines a measure of the proposed additional data transfer. The computer determines a measure of recent actual data transfers. The recent actual data transfers involve one or more of the source storage devices and one or more of the target storage devices. In response to the request for the proposed additional data transfer, the computer estimates performance of one or more of the source storage devices and one or more of the target storage devices that would occur during the proposed additional data transfer based on the measure of recent actual data transfers combined with the measure of the proposed additional data transfer.

Abstract: The present invention relates to a portable storage device communicating via a USB 3.0 protocol and a computer system having the same. The computer system according to one embodiment of the present invention comprises a portable storage device and a computer. The portable storage device includes an operating system (OS) storage region for storing OS data and boot data which are not sent to the computer through a transmission channel used for data transmission via the USB 3.0 protocol, requested by a receiving channel used for receiving data via the USB 3.0 protocol, and loaded on the computer to drive the computer.

Abstract: In accordance with one or more embodiments, a method of managing animation data and related control data for recording on an enhanced navigation medium is provided. The method comprises constructing animation data comprising first image data into a first graphic MNG file in chunk data format, wherein the first graphic file comprises a first header portion, a second end portion, first control data and a frame containing additional data; and recording the first graphic file on an enhanced navigation medium.

Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

Abstract: Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, which provides data storage/reading services through an SAS/SATA interface. The SAS/SATA type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; an SAS/SATA host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the SAS/SATA host interface unit and the memory disk unit to control a data transmission/reception speed between the SAS/SATA host interface unit and the memory disk unit.

Abstract: Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.

Abstract: The present invention provides an improved method and system of improving the efficiency, and ensuring the integrity, of a data transfer in a serverless backup, or third party copy, system having one or more physical storage devices. The present invention provides improvements to the processing of serverless copy, or EXTENDED COPY, commands, and transfers of data associated with such commands. These improvements increase the speed at which such commands are executed and completed, and increase the capabilities of copy managers in serverless backup systems. The improvements also make better use of the storage devices involved in the data backup process. Certain aspects of the invention allow for execution of data segments of any size, and providing a compiler for generating input/output actions.

Abstract: Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described.

Abstract: This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.

Abstract: It is assumed that the image data inputted are subjected to run-length compression and compressed encoding based on Huffman encoding. The first step configuration configured on a reconfigurable circuit includes run-length compression circuits 102a and 102b of two ways for parallel processing and FIFOs 108a and 108b which hold the output data from the circuits, respectively. For example, the data of odd pages are supplied to the run-length compression circuit 102a and the data of even pages are supplied to the run-length compression circuit 102b. After the compression processing proceeds, when at least one of the FIFOs 108a and 108b becomes full, the reconfigurable circuit is reconfigured into the second step configuration. In this configuration, the FIFOs 108a and 108b holding the compression results are left and two Huffman encoding circuits for encoding the data supplied from these FIFOs are included.

Abstract: A data processing apparatus includes a register file having a set of registers for storing data values for processing by processing circuitry. The apparatus has first shift circuitry arranged to receive a data value from the register and selection circuitry is responsive to a second control signal to select between the first shifted data value and a load data value received from a memory. Second shift circuitry is arranged to receive the data value selected by the selection circuitry and is responsive to a third control signal indicating a second shift amount S2 of a x (n+1) bit positions to generate a second shifted data value by shifting bit values within the received selected data value by the second shift amount S2, where a is zero or an integer. The second shift circuitry is then operable to output the second shifted data value to the register file.

Abstract: An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing a burst, such that the reception physical-layer queue includes a plurality of word lines. The burst includes one or more PDUs that each occupy one or more word lines of the reception physical-layer queue, such that a particular word line stores a portion of a first PDU and a portion of second PDU. The MPC is also configured to receive from the reception physical-layer queue the first PDU including the portion of the first PDU stored in the selected word line.

Abstract: One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.

Abstract: A circuit for controlling a peripheral device interface is to enable a central processing unit to detect a peripheral device. The circuit includes a control chip and first to sixth capacitors. The control chip includes a power supply input pin, first to second differential signal output pins, first to second differential signal input pins, and an expansion pin. The power supply input pin is connected to a power supply and grounded via the first and second capacitors in parallel. The first and second differential signal output pins are connected to the peripheral device interface via the third and fourth capacitors respectively. The first and second differential signal input pins are connected to the peripheral device interface via the fifth and sixth capacitors respectively. The expansion pin is grounded via a resistor.

Abstract: An apparatus comprising an interface circuit and a controller. The interface circuit may be configured to calculate a speed signal in response to data traffic measured over a network. The controller may be configured to present and receive data from an array in response to (a) the speed signal and (b) one or more input/output requests. The interface circuit may generate the speed signal in response to a plurality of predetermined factors. The controller may present and receive the data at one of a plurality of speeds in response to the speed signal.

Abstract: A universal serial bus (USB) device and a USB system are provided. The USB device comprises an electrical physical layer (EPHY) module, a logical physical layer (LPHY) module and a link layer module. The EPHY module reads the voltages of first and second transmission lines of a USB cable to extract a recovery clock and data. The LPHY module detects the recovery clock and data to output an indication signal. When the recovery clock is not detected, the LPHY module sets the indication signal to a predetermined value. The link layer module determines whether the indication signal is at the predetermined value, and makes a state machine thereof leave a normal operation state when the indication signal has been maintained at the predetermined value over a predetermined time period.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for live media playback adaptive buffer control. For example, when media accumulated in the live buffer exceeds a user-configured threshold, media can be played out faster. In this manner, the media player is configured not to discard media packets, but rather to render the buffered media faster to slowly eliminate accumulated backlog. Preventing unbounded buffer accumulation may be desirable in applications like video surveillance, live video broadcast, webcast, and the like.

Abstract: A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance.

Abstract: A network system comprising a plurality of servers communicatively-coupled on a network, a network-attached memory coupled between a first server and a second server of the server plurality, and a memory management logic that executes on selected servers of the server plurality and migrates a virtual machine from the first server to the second server with memory for the virtual machine residing on the network-attached memory.

Abstract: A method and device for time determination in a bus system and a bus system having at least two users which are connected via a communication link are provided, where at least one user stores a specifiable base time in at least one memory, in particular a register, when an event occurs on the communication link whose moment of occurrence is to be determined.

Abstract: Embodiments of the invention provide a method of storage array with frame forwarding capability to reduce the complexity of an IT platform system having a large number of hardware devices. In one embodiment, a storage system comprises one or more storage devices; a storage controller having a storage controller processor and a storage controller memory and being coupled with the one or more storage devices; an interface controller receiving an input/output command directly from a host computer; and an internal bus. The interface controller and the storage controller are coupled by the internal bus. In another embodiment, a storage system comprises one or more storage devices; a storage controller having a processor and a memory and being coupled with the one or more storage devices; and a network interface controller which provides virtual Ethernet bridging.

Abstract: A device control device includes a transmission signal receiving/outputting unit configured to receive/output a signal containing a control signal for controlling an internal status from/to another device, the other device being connected to the transmission signal receiving/outputting unit, an application obtaining unit configured to obtain an application as necessary by accessing an application server via a network, a display control unit configured to control display based on the application obtained by the application obtaining unit, and an operation control unit configured to control an operation of the other device by performing the application obtained by the application obtaining unit. The display control unit changes content to be displayed in accordance with a type of the other device.

Abstract: A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.

Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.