Abstract: Methods and systems are provided to allow personal computer users to virtualize a local audio device so that they can remotely connect to a server and interact with the server as if the local audio device was physically connected to the server. They connect a remote audio target hardware device to the target system through a physical USB connection, and the device interacts with the local user's computer over a network. The target system is unaware that the audio device is not connected directly to the system through a physical connection, and the target system does not need special software to implement the remote audio device. The audio target hardware device connected to the target computer may be physically connected and disconnected.

Abstract: An information processing method includes calculating a reception estimated time when the data are received based on a last reception time of the data and a reception time interval of the data for transfer source devices; calculating a shift completion estimated time based on a shift time period necessary to shift an assignment of a data transfer process of a transfer source device of the plurality of the transfer source devices from the transfer processing device to another transfer processing device; and transferring the assignment of the data transfer process from the transfer processing device to the another transfer processing device, the assignment of the data transfer process being relevant to a transfer source device having the calculated reception estimated time later than the shift completion estimated time and closer to the shift completion estimated time than any other transfer source devices.

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract: A network device may include an off-chip memory to store a free-list of buffer pointers. The network device may further include an on-chip controller that includes a prefetch buffer. The prefetch buffer may store unallocated buffer pointers that point to available memory locations in a different off-chip memory. The on-chip controller may receive an unallocated buffer pointer, determine, in response to receiving the unallocated buffer pointer, whether the prefetch buffer is full, store the unallocated buffer pointer in the prefetch buffer when the prefetch buffer is determined not to be full, and store the unallocated buffer pointer in the free-list, in the off-chip memory, when the prefetch buffer is determined to be full.

Abstract: A storage system of an embodiment of this invention comprises a first transfer engine, a second transfer engine, a first storage device, a second storage device, a processor, and a transfer sequencer which is a device different from the processor. The processor creates transfer sequence information for indicating a sequence of transfers of user data. The transfer sequencer receives the transfer sequence information made by the processor and controls the first and the second transfer engines in accordance with the transfer sequence information. The first and the second transfer engines transfer user data between storage devices in accordance with instructions from the transfer sequencer.

Abstract: A display apparatus, a control method thereof and a control method of an external device are provided. The display apparatus includes a contents processing unit which reproduces contents, a communication unit which communicates with an external device which reproduces contents, and a control unit which receives reproduction information of the contents reproduced in the external device from the external device through the communication unit, and controls the contents processing unit to reproduce contents corresponding to the contents reproduced in the external device, based on the received reproduction information.

Abstract: The present invention is directed toward a system and method for simultaneously switching multiple input image streams to multiple output devices while providing optional image processing functions on the image streams. The incoming image streams may come from computers, cameras, radar, or other image stream generating devices. The incoming streams may vary in resolution, frame rate, format, and protocol according to the characteristics and purpose of their respective source devices. The incoming image streams can be iteratively routed through a reconfigurable array of image processing circuit cards to operate on one or more streams using preprogrammed algorithms. A processed stream can be routed through another processing function, or to an output circuit card that sends the completed image to the external display, recording device, across a network, or to another logical destination.

Abstract: A data transfer device includes a transfer method setter that sets the transfer method to either a first transfer method or second transfer method that differ from each other, and a transfer controller that causes data to be transferred. The transfer controller causes data to be transferred according to the transfer method that was set by the transfer method setter. The first transfer method, for example, is a transfer method that has a smaller expected writing disabled time than the second transfer method when the probability that writing will occur during the transfer process is high. The second transfer method, for example, is a transfer method that has a smaller expected writing disabled time than the first transfer method when the probability that writing will occur during the transfer process is low.

Abstract: A data storage device is provided, including a first data storage device electrically storing write data, a second data storage device magnetically storing write data, and a controller partitioning write data into first and second write data portions. The first write data portion is programmed to the first data storage device and the second write data portion if magnetically written to the second data storage device at the same time.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.

Abstract: Prior to customer use of a device, communication with the device is allowed via multiple pins of an external interface of the device. One or more pins of the multiple pins via which communication with the device is to be prevented during customer use of the device are identified. The one or more pins are monitored, and a remedial action is taken if particular activity is detected on the one or more pins. Various different remedial actions can be taken, such as resetting or disabling the device.

Abstract: A device control apparatus in a video image display system including a plurality of connected devices. The apparatus includes an obtaining unit which obtains a logical address of a first device connected to the device control apparatus as a control object, a specifying unit which specifies the device type of the first device if the obtained logical address of the first device is not a logical address according to the device type, a selection unit which selects a second device which is connected to the device control apparatus and is of the same device type as the first device, and a control unit which controls a logical address assigned to the selected second device according to the device type thereof so that the first device obtains a logical address.

Abstract: A method, system, and computer program product containing instructions for handling legacy BIOS services for mass storage devices using system management interrupts. In response to receiving a request for an input/output service, a system management interrupt is generated to enter system management mode. A system management RAM (SMRAM) is accessible to code executing inside system management mode. Sub-operations to perform the requested service are identified, and code is executed outside the SMRAM to perform a sub-operation to fulfill the request. The sub-operations identified for execution outside SMRAM include any sub-operations that require waiting for data to be transferred. Other code executing inside the SMRAM may perform additional sub-operations that do not require waiting for data transfers to fulfill the request. System management mode is exited before invoking the code to perform the sub-operation to execute outside the SMRAM.

Abstract: Provided is a serial control device that makes the length of data transferred as one frame variable. The serial control device transfers serial data having an arbitrary length, and uses end information indicating inclusion or non-inclusion of end data of the serial data. The serial control device transfers data having a transfer unit length in the serial data when the end information indicates non-inclusion of the end data, and transfers an untransferred part of the serial data when the end information indicates inclusion of the end data.

Abstract: Video data is transmitted from a video source to a video sink via a fixed rate serial link with a substantially constant unit interval for transmission of each symbol of the encoded data. The unit interval of the serial link is maintained substantially constant, and does not vary regardless of the display parameters of the video data. The video data is encoded into a plurality of video data streams, with each data stream including a plurality of fields. The fields include at least a clock offset field and video payload data fields. The clock offset field includes phase information indicative of the phase of the display clock offset with respect to a time reference, indicated in terms of the number of unit intervals offset from the time reference. The video sink recovers the display clock based on the display clock offset information, and thus no display clock itself is transmitted from the video source to the video sink.

Abstract: Circuits, methods, and apparatus that may improve networking techniques for transferring data among various electronic devices. One example may provide sharing data among various devices by daisy-chaining devices together. That is, several devices may be connected to each other through a series of cables to form a chain of devices. In this physical configuration, data may be shared among multiple devices using a series of single-hop virtual tunnels. Alternatively, a number of tunnels may be formed by a host device, each having a target device in the daisy chain. Each tunnel may originate at the host device and terminate at their target device. Each tunnel may bypass devices between the host device and the tunnel's target device. These two techniques may also be combined. Another example may provide a method of simplifying the routing of high-speed data signals through a network topology.

Abstract: A method and system are provided for transferring data in a networked system between a local memory in a local system and a remote memory in a remote system. A RDMA request is received and a first buffer region is associated with a first transfer operation. The system determines whether a size of the first buffer region exceeds a maximum transfer size of the networked system. Portions of the second buffer region may be associated with the first transfer operation based on the determination of the size of the first buffer region. The system subsequently performs the first transfer operation.

Abstract: Various embodiments of systems, methods, computer systems and computer software are disclosed for implementing a control I/O offload feature in a split-path storage virtualization system. One embodiment is a method for providing split-path storage services to a plurality of hosts via a storage area network.

Abstract: A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.

Abstract: The invention relates to an assembly comprising a main device and an accessory, which can be connected by a safe connector and a safe detection method. According to the invention, the assembly comprises:—a main device (2),—an accessory (3) connectable to the main device (2),—the accessory (3) comprising an accessory connector (4) for mating with a device connector (5) of the main device (2),—the accessory connector (4) and the device connector (5) each comprising one or more supply contacts (7) for transmitting electric power from the main device (2) to the accessory (3),—the main device (2) comprising a detection device (9), which, if connecting the accessory (3) to the main device (2), receives complex accessory data stored by the accessory (3) and which by positive evaluation of the complex data enables applying a supply voltage at the one or more supply contacts (7) of the device connector (5).

Abstract: A method of facilitating communications between a computer device and a smart card reader having an associated smart card, the computer device including a smart card resource manager and a smart card reader service, the smart card reader service acting as a relay for commands between the smart card resource manager and the smart card reader, the method comprising: receiving from the smart card resource manager a first command for setting a protocol for communications with the smart card; and responding, prior to receiving a reply from the smart card to the first command, to the smart card resource manager with a message indicating that the smart card has successfully received the first command.

Abstract: Method and apparatus for inter-IC communication are described. In some examples, an integrated circuit (IC) includes core circuitry configured to process input data and provide output data; input/output (IO) circuitry configured to receive the input data, and transmit the output data; a control circuit configured to provide a selection signal; and an inter-IC communication port coupled between the core circuitry and the IO circuitry and configured to pass the input data and the output data, the inter-IC communication port having a memory interface and a memory controller, the inter-IC communication port configured to selectively couple either the memory interface or the memory controller between the core circuitry and the IO circuitry responsive to the selection signal.

Abstract: A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.

Abstract: A system and corresponding method for transferring data via an interface assembly. The data may be transferred between a USB port of a first device and a media port of a second device. Uncompressed high definition media data may be received from the USB port. The received uncompressed high definition media data may be supplied to a media connector in accordance with a first media standard, such that the supplied data can be transmitted in accordance with the first media standard via the media connector to the media port of the second device. The uncompressed high definition media data may include multimedia data and side-band communication data. A single signal may be encoded and decoded in accordance with a protocol that enables the single signal to communicate all side-band communication to and from the source device via a single pin of a USB connector.

Abstract: Systems and methods are described herein to provide for improved hardware device connectivity. Other embodiments include apparatus and system for receiving messages from an operating system and sending messages to one or more hardware devices. Further embodiments include methods for receiving messages from an operating system regarding operations on a hardware device and responding to those messages. Other embodiments include methods for receiving interrupt messages and mapping those interrupt messages to hardware devices. Other embodiments are described and claimed.

Abstract: An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.

Abstract: A modular development platform is described which enables creation of reliable, compact, physically robust and power efficient embedded device prototypes. The platform consists of a base module which holds a processor and one or more peripheral modules each having an interface element. The base module and the peripheral modules may be electrically and/or physically connected together. The base module communicates with peripheral modules using packets of data with an addressing portion which identifies the peripheral module that is the intended recipient of the data packet.

Abstract: An interface circuit includes: a first transmitting section transmitting a first signal as an in-phase signal to an external device through a transmission path; and a second transmitting section transmitting a clock signal, which is synchronized with the first signal to be transmitted by the first transmitting section, as a differential signal to the external device through the transmission path.

Abstract: In a computer system supporting memory compression, wherein memory compressed data is managed in units of memory sectors of size S, wherein data is stored on disk in a different compressed format, and wherein data on said disk is managed in units of disk sectors of size D, a method for storing memory compressed data on a compressed disk includes combining at least one of compressed memory directory information, a system header, compressed data controls, and pads into a data structure having a same size S as a memory sector, grouping the data structure and the data contained in the desired memory sectors into groups of D/S items, and storing each of the groups in a separate disk sector.

Abstract: After reading data from a memory in response to a read request received from a bus master and burst transferring the read data, a memory interface 100 continues to read and store (i.e., continuously reads and stores) data starting from an address that follows all of addresses of the read data. Upon receiving a new read request from the bus master within a predetermined time, the memory interface 100 determines whether a difference between an address specified by a previous read request and an address specified by a new read request falls within a predetermined range. If it is determined positively, the memory interface 100 successively transfers the stored data in response to the new read request. If it is determined negatively, or if the reception of the new read request is not performed within the predetermined time, the memory interface 100 terminates the continuous data read.

Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.

Abstract: A computer-implemented method for selectively discovering storage devices connected to a host computing device may include: 1) identifying at least one storage device connected to the host computing device that provides storage for at least one resource managed by the host computing device, 2) identifying a discovery classification assigned to the storage device that is based at least in part on an availability requirement associated with the resource, and then 3) discovering the storage device in accordance with the discovery classification assigned to the storage device. Various other methods, systems, and configured computer-readable media are also disclosed.

Abstract: The present invention relates to a method for data transfer between a host and a device as well as to respective apparatus. A host is seen as a communication apparatus which organizes data traffic. A device is seen as dependent on the host. In a tiered-star topology there are usually multiple devices connected to one host. A method for data transfer between a host and a device through pipes is presented. The available memory in the host is divided into multiple segments. The assignment of segments is changed between pipes in dependence on the pipe traffic.

Abstract: In a storage system including a host computer, and a disk control device connected to the host computer for communications therewith, and performs control over a disk device that stores therein data requested for writing from the host computer, for data transmission from a host interface section or a disk interface section to a memory section, when the data asked by a transmission source for storage is stored in a transmission destination, the transmission destination is put in a first mode for communications of forwarding a response back to the transmission source. With such a configuration, favorably provided is the storage system that offers a guarantee of reliability with the improved processing capabilities thereof.

Abstract: Methods and systems for measuring available direct memory access (DMA) throughput are disclosed, including providing a plurality of DMA channels, the DMA channels comprising a measuring DMA channel and other DMA channels, the measuring DMA channel having a lowest data rate priority, and determining an available DMA throughput by measuring a current data rate at which the measuring DMA channel is serviced in response to initiating a data transfer on the measuring DMA channel.

Abstract: A communication control device in an audio visual device system has disconnection detection unit for detecting that an audio visual device is disconnected from the audio visual device system, device detection unit for detecting an audio visual device which has not acquired a logical address according to a device type, and control unit for performing control for causing the audio visual device without a logical address to acquire a logical address, when disconnection of a audio visual device is detected by the disconnection detection unit. With this configuration, in an audio visual device system in which an upper limit is set to the number of logical addresses according to a device type, it is possible to cause an audio visual device which cannot acquire a logical address according to the device type to acquire a logical address when it is made available.

Abstract: A serial data transfer apparatus includes a transport controller that performs a process of a transport layer, a link controller that performs a process of a link layer, and a physical layer circuit that performs a process of a physical layer. The serial data transfer apparatus transmits and receives data with a destination apparatus via a serial bus. The link controller outputs idle data, which is received from the destination apparatus, to the physical layer circuit, and stops to operate of a unit responsible for generating data to transmit to the destination apparatus while outputting the idle data to the physical layer circuit. This enables to output idle data defined in the standard in an idle period of the serial data transfer apparatus and also reduce the power consumption.

Abstract: Storage devices can maintain metadata on a per-block basis, enabling the storage device, the file system, or other higher-level software to store and obtain information about individual blocks of data. A handshake between the storage device and a computing device can include an exchange of feature tables, whereby a commonly supported set of features and attributes can be selected and agreed upon. Such features and attributes can include access pattern specification in the per-block metadata, frequency of access or importance designations and specifications of the longevity of temporary data. The per-block metadata can either be provided by an application or the file system, or it can be generated by the storage device itself. Likewise, per-block metadata can be utilized by the storage device, either on its own or at the behest of an application or the file system, or it can be utilized directly by the application or file system.

Abstract: According to the embodiment, a memory system includes a first memory which includes a memory cell array and a read buffer, a second memory, a command queue, a command sorting unit, and a data transfer unit. The command sorting unit dequeues commands excluding a later-arrived command whose access range overlaps with an access range of an earlier-arrived command from the command queue. The data transfer unit performs a data preparing process of transferring data that is specified by dequeued read command and is read out from the memory cell array to the read buffer, a first data transfer of outputting the data stored in the read buffer, and a second data transfer of storing data that is specified by dequeued write command in the second memory. The data transfer unit is capable of performing the data preparing process and the second data transfer in parallel.

Abstract: The present invention relates to the field of processing within hardware security modules, such as for example debugging of compiled programs. A debugging module includes a microprocessor and a compiled program to be executed by the microprocessor in order to carry out an operation, and is configured to exchange with an external entity, in a master/slave mode, messages relating to the operation. The compiled program includes at least one debugging instruction which whether or not it is executed does not modify the execution of the operation. The hardware security module is moreover configured to transmit, during the execution of the compiled program, data generated, for example by the debugging instruction, over a communication channel initiated by the hardware security module, to an entity external to the hardware security module.

Abstract: A method for generating a device description for a measuring apparatus in a target field bus protocol is described. The method comprises the reception of a first device description of the apparatus. The first device description of the apparatus comprises at least one variable. The at least one variable is related to a storage cell of the apparatus. The target field bus protocol is selected from a plurality of field bus protocols, and at least one block is formed from the at least one variable. The at least one block has a maximum block size that corresponds to the smallest maximum block size of at least two field bus protocols of the plurality of field bus protocols. The maximum block size can be transmitted via a field bus with a single request when the respective field bus protocol is used. Subsequently, the at least one block is provided as device description for the apparatus in the target field bus protocol.

Abstract: A method and apparatus for allowing a limited functionality Universal Serial Bus (USB) host controller to manage specific USB peripheral devices on a downstream facing USB port is provided. The port is also capable of dynamically interfacing to any USB compliant peripheral device, even one not supported directly by the limited capabilities of the host controller.

Abstract: A method for transferring image data by using an interface with at least two transfer pipes to transfer from an image accessing unit to a computer is disclosed. The method includes: obtaining image data in response to a control command from the computer; converting the image data to sampled structure data and transferring the sampled structure data to the computer through at least one of the data transfer pipes; and providing information to the computer to recover the received sampled structure data.

Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device.

Abstract: A universal serial bus (USB) communication system, the communication system including: (a) at least one asynchronous transmission queue manager configured to queue, in at least one asynchronous transmission queue, information for asynchronous transmission through at least one asynchronous pipe; (b) at least one guaranteed transmission queue manager configured to insert into at least one queue information for transmission through a dedicated pipe utilized by the communication system; wherein the at least one queue is selected from the at least one asynchronous transmission queue, at least one periodic transmission queue and at least one additional queue; and (c) a transmitter configured to transmit information through the at least one asynchronous pipe and the dedicated pipe, wherein the transmitting through the dedicated pipe is prioritized over the transmitting at the at least one asynchronous pipe, wherein the transmitting at the dedicated pipe is irrespective of time in which information for transmission a

Abstract: A method for transferring digital content, involving defining a first region of space associated with a first device and a second region of space associated with a second device, wherein the first device includes digital content to be transferred to the second device, performing a first action within the first region, obtaining the digital content to be transferred from the first device in response to performing the first action to obtain captured digital content, performing a second action within the second region, and transferring the captured digital content to the second device in response to performing the second action.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial communications port.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.