Abstract: This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A computer system may comprise a second device operating as a producer that may steer data units to a first device operating as a consumer. A processing core of the first device may wake-up the second device after generating a first data unit. The second device may generate steering values after retrieving a first data unit directly from the cache of the first device. The second device may populate a flow table with a plurality of entries using the steering values. The second device may receive a packet over a network and store the packet directly into the cache of the first device using a first steering value. The second device may direct an interrupt signal to the processing core of the first device using a second steering value.

Abstract: According to an aspect of the present invention, the communication between processors and peripheral controllers is provided using packets. In an embodiment, the access requests are specified according to a common format such that all the information required for performing each access request is included in a single packet and sent to the peripheral controller. The peripheral controller performs the access request on the external device and generates a response. According to another aspect, the packet format enables the peripheral controller to send responses, requests originating from the external devices and interrupt requests. According to yet another aspect, the packets from processors are first stored in a random access memory (RAM) and a DMA controller retrieves the packets and delivered to the respective peripheral controllers.

Abstract: A method for point-to-point ethernet communication over point-to-multipoint shared single conductor channel topology comprises transmitting an ethernet signal upstream over the point-to-multipoint topology from one end point of the topology to the root of the topology, transmitting the ethernet signal downstream over the point-to-multipoint topology from the root of the topology to all end points of the topology, and selectively processing only at a designated end point the ethernet signal received at all end points. An ethernet system may comprise single conductor channel cabling (e.g., coaxial cabling) including a trunk line and a plurality of branch lines connecting to the trunk line at a plurality of points along the trunk line, a single root transceiver (root-PHY) connected at an end of the trunk line, and a plurality of end point transceivers (EP-PHYs), each connected to a respective one of the plurality of branch lines.

Abstract: There is provided a data transfer method in an IEEE1394 system including a band request node and a transfer band management node. The method includes generating, at the band request node, a transfer request that can detect a data amount of transfer data and transmitting the transfer request from the band request node to the transfer band management node, determining, by the transfer band management node, whether a transfer band requested by the transfer request is ensured or not, notifying, from the transfer band management node, the band request node of the determination result, and transferring data from the band request node according to the determination result.

Abstract: Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.

Abstract: An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.

Abstract: A computer system reduces an overhead by using an I/O switch high in versatility when realizing the sharing of an I/O between virtual computers. The system includes a CPU module #0 having plural CPU cores, an AS bridge 15 connected to the CPU cores, and a main memory that can be accessed from the CPU cores or the AS bridge 15, and AS switches SW0 and SW1 that connect the AS bridge 15 of the CPU module #0 and an I/O blade #5. The CPU module #0 has a hypervisor that divides the plural CPU cores and the main memory into plural logical partitions, and the AS bridge 15 adds virtual path information set in each of the logical partitions and path information of from the AS bridge 15 to the I/O blade #5 to the path information of the AS packet to switch over the AS packet between each of the logical partitions and the I/O blade #5 when relaying the AS packet transmitted or received between the logical partitions and the I/O blade #5.

Abstract: A server machine, connectable to a peripheral device and to a client machine via a network, includes: a device interface for connecting with a peripheral device; a network interface for connecting with a network; and a device interface control section configured to relay data communications between the client machine and the peripheral device via the device interface and the network interface, and to execute a first process, if a first condition, including that predetermined first data has been received from the client machine is satisfied, of causing the peripheral device to transition into a first state in which the peripheral device is communicable with the server machine, and execute a second process, if a second condition, including that predetermined second data has been received is satisfied, of causing the peripheral device to transition into a second state in which its power consumption is lower than that in the first state.

Abstract: A processor determines whether a prescribed period of time has elapsed or not. When the processor has determined that the prescribed period of time has elapsed, the processor determines whether a mode 0 is set or not. When it is determined that the mode 0 is set, a wireless packet including remote controller button data, remote controller acceleration data and remote controller DPD data is generated. Then, the generated wireless packet is transmitted to a game device. When the processor has determined that a mode 1 is set, a wireless packet including remote controller information including the remote controller button data and the remote controller acceleration data and biological information including previous pulse wave data, present pulse wave data and light reception level data, instead of the remote controller DPD data, is generated.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: The invention describes a method for the monitoring and management of data traffic in a communication system with several communication nodes which communicate via interfaces monitored by a bus monitor, comprising the following steps: a) provision of a predefined communication time schedule for all communication nodes, b) initialization of the bus monitor, c) synchronization of the communication time schedule of the bus monitor with the predefined communication time schedule executed by the communication nodes in a distributed arrangement, the synchronization taking place on the basis of activities observed at the interfaces, d) monitoring of the activities of the communication nodes by the bus monitor, e) comparison of the activities with the predefined communication time schedule, and f) deactivation of the interface for any communication node for which an activity not compatible with the predefined communication time schedule has been detected. A circuit arrangement and its use are also described.

Abstract: An on-vehicle device with a storage unit that includes a transfer unit that transfers data stored in the storage unit to another on-vehicle device of equal capability that is also equipped with a storage unit. In the on-vehicle device, the transfer unit is configured by a data transfer jack provided to each of the on-vehicle device and the another on-vehicle device, and a data transfer cable for connecting the transfer jacks.

Abstract: An isolated highway addressable remote transfer (HART) interface with programmable data flow is provided. The isolated HART interface includes a HART channel having at least one pair of terminals configured to connect with a HART device via a current loop. The HART channel is programmable to have each pair of terminals assigned as a current loop input or a current loop output.

Abstract: A method for storage virtualization in user space. The method includes providing a first emulation module running in the OS kernel and providing a second emulation module in the user space of the computer, which may emulate a media changer or other SCSI or other storage device. The method continues with a kernel-resident driver receiving a packet of data at a port of the computer that is linked to a data communications network (such as a SAN). The packet of data may include command data for a particular data storage device (e.g., a SCSI command for a SCSI device). The method includes operating the first emulation module to communicate with the driver and to then pass through the packet of data to the second emulation module, allowing the second emulation module to run in user space but efficiently receive data from the kernel-resident driver via the first emulation module.

Abstract: The invention relates to a method for setting an operating parameter in a peripheral IC. In this method, the operating parameter is transmitted from a central IC via a bus connection to the peripheral IC. The method is characterized in that the operating parameter is initially buffered in a preregister in the peripheral IC, and in that the buffered operating parameter is transferred into a working register only if a transfer signal is sent from the central IC via the bus connection. This method has the advantage that, for example in the case of rapidly changing receive conditions in a send/receive unit, adjustment of the send or receive gain setting is very flexible, and it is easy to avoid an incorrect setting due to a detected signal fluctuation. The invention also relates to a device for carrying out said method.

Abstract: A semiconductor memory device includes a nonvolatile memory device having a plurality of physical sectors, and a memory controller configured to translate a logical address received from a host to a physical address, with reference to mapping data that defines a correspondence between the logical address and the physical address. The nonvolatile memory device is configured to access a first physical sector corresponding to the physical address, and, when a data delete command is provided from the host to the memory controller to delete first data that is stored in the first physical sector, the memory controller delays an erase and/or merge operation for the first physical sector in which the first data is stored.

Abstract: Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an error sensed on the link. Based on the at least one counter, the SAS/SATA device determines whether to maintain the first signal rate. The link is re-established at a second signal rate based on the determination such that the second signal rate is lower than the first signal rate.

Abstract: A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: Provided are a relocation system and a relocation method capable of relocating a virtual volume that is formed based on thin provisioning while ensuring security against exhaustion of pools. A database stores attribute information for pools and virtual volumes for thin provisioning that exist in a storage device as well as parameters for predicting time period till exhaustion of the pools. When a virtual volume is to be relocated between a plurality of pools, a relocation control section predicts time periods till exhaustion of the pools before and after relocation based on information in the database and determines the relocation is possible or not based on the result of prediction or determines an appropriate relocation plan. This enables control of relocation of virtual volumes.

Abstract: A DMA control system includes: a plurality of DMA control units that are controlled in a manner that, while one of the plurality of DMA control units use a transmission path, the other DMA control units other than the one of the plurality of DMA control unit are prevented from using the transmission path; and a transfer instruction unit that defines transfer amounts of DMA transfers for the respective DMA control units and gives transfer instructions thereto. The transfer instruction unit, when the transfer instruction unit gives a transfer instruction to a first DMA control unit of the plurality of the DMA control units, defines a transfer amount for the first DMA control unit and gives the transfer instruction thereto in accordance with a state of utilizing a second DMA control units of the plurality of the DMA control units.

Abstract: A video decoder includes a memory (140) operable to hold entropy coded video data accessible as a bit stream, a processor (100) operable to issue at least one command for loose-coupled support and to issue at least one instruction for tightly-coupled support, a bit stream unit (110.1) coupled to said memory (140) and to said processor (100) and responsive to at least one command to provide the loose-coupled support and command-related accelerated processing of the bit stream, and a second bit stream unit (110.2) coupled to said memory (140) and to said processor (100) and responsive to said at least one instruction to provide the tightly-coupled support and instruction-related accelerated processing of the bit stream. Other encoding and decoding processors, circuits, devices, systems and processes are also disclosed.

Abstract: An apparatus and a method for processing high speed data using hybrid Direct Memory Access (DMA) are provided. The method includes determining a size of data to be transmitted, determining a memory access method of the data by comparing the determined size of the data with a first threshold, and determining an I/O bus access method of the data by comparing the determined size of the data with a second threshold.

Abstract: A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog front ends is operative to perform signal conversion between a digital domain and an analog domain. The physical layer device further includes a digital switching circuit coupled to the digital core and to the first and second analog front ends. The digital switching circuit is operative to electrically connect the digital core to the first analog front end or the second analog front end as a function of a control signal applied to the digital switching circuit.

Abstract: In a system for communicating data from a processor to a plurality of register groupings that includes a plurality of registers and a plurality of register decoding logic entities, each register is associated with one of the plurality of register groupings. The plurality of register decoding logic entities is arranged in a data communication ring and is assigned to a register grouping.

Abstract: An information processor (program processing unit 1) for managing a data sequence in a fixed order comprises a direction array (reference data storage section 2) for storing a reference to each data item of the data sequence in an element of the index associated with the key to the data, and means (CPU 3) for changing all data keys referenced by elements within an arbitrary range of indexes in the direction array by the same amount, where memory contents within the range of the direction array are shifted by the number of indexes corresponding to the changed amount.

Abstract: An apparatus, system, and method are disclosed for converting a synchronous interface into an asynchronous interface. The apparatus includes a receive module, a generate module, and a return module. The receive module receives a request for a transaction from a synchronous requester, the generate module generates a delaying object and a forwarding interface compatible with the requested return type, and the return module returns the delaying object with the forwarding interface to the requester. Additionally, services for implementing such an apparatus, system, and method are disclosed. Implementation of the apparatus, system, and method provide for increased computing performance, reduced application run time, and decreased usage of computing resources.

Abstract: An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed IHS video signal and IHS bus information is received by a display multiplexer, where it is demultiplexed. Demultiplexed IHS video signal information is received by a video interface receiver, where it is used to generate an image on a digital display. Demultiplexed IHS bus information is received by a host bus interface transmitter/receiver, where it is used to support peripheral devices attached to the digital display.

Abstract: The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.

Abstract: A system, method, and computer readable medium. A method includes setting a maximum translation delay. The method includes, while a current delay is less than the maximum transfer delay, repeatedly performing the steps of searching for an additional transfer having a same source and target as a current transfer, and when an additional transfer is found, adding the additional transfer to a transfer list that identifies transfers to be made together. The method includes performing a transfer of the transfers identified by the transfer list when the current delay has met or exceeded the maximum transfer delay.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A data logging system that utilizes a schedule of data transfer periods for transferring data from devices to a server. A communication of an actual data transfer size of stored data in a first device of the devices is obtained by the server from the first device. A corresponding future data transfer size of the stored data is estimated by the server, based on a historic data transfer size for data previously transferred from the first device to the server. The schedule is currently based on the historic data transfer size for the first device. The server updates the schedule if the server has determined that a difference exists between the actual data transfer size and the corresponding estimated future data transfer size. A transmission from the first device of the data actually stored in the first device is received by the server in accordance with the schedule.

Abstract: A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated.

Abstract: An integrated system to control peripherals in a vehicle includes a control and interconnection system having a supervisory processor and/or supervisory control. The control and interconnection system is responsive to feedback from peripherals associated with the vehicle. Moreover, the supervisory processor supervises a plurality of peripherals in communication with the control and interconnection system, where at least one of the plurality of the peripherals includes a controller and is associated with at least one of the: vehicle dynamics, vehicle power train and vehicle body, of a corresponding vehicle. Still further, the supervisory processor provides control information to each of the plurality of peripherals to coordinate performance characteristics based upon at least one operating condition that is determined by the control and interconnection system.

Abstract: A computer system may comprise a second device operating as a producer that may steer data units to a first device operating as a consumer. A processing core of the first device may wake-up the second device after generating a first data unit. The second device may generate steering values after retrieving a first data unit directly from the cache of the first device. The second device may populate a flow table with a plurality of entries using the steering values. The second device may receive a packet over a network and store the packet directly into the cache of the first device using a first steering value. The second device may direct an interrupt signal to the processing core of the first device using a second steering value.

Abstract: A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: DMA in a computing environment that includes several computers and DMA engines, the computers adapted to one another for data communications by an data communications fabric, each computer executing an application, where DMA includes: pinning, by a first application, a memory region, including providing, to all applications, information describing the memory region; effecting, by a second application in dependence upon the information describing the memory region, DMA transfers related to the memory region, including issuing DMA requests to a particular DMA engine for processing; and unpinning, by the first application, the memory region, including insuring, prior to unpinning, that no additional DMA requests related to the memory region are issued, that all outstanding DMA requests related to the memory region are provided to a DMA engine, and that processing of all outstanding DMA requests related to the memory region and provided to a DMA engine has been completed.

Abstract: Systems, methods, and computer-readable media for resuming a media object presented following a data loss event are provided. A physical disconnection that occurs at a point during the presentation of the media object is detected. The physical disconnection interrupts the presentation of the media object. Upon detecting the physical disconnection, a reestablishment of the physical connection is detected. Subsequently, an option to resume the presentation of the media object at the interrupted point is presented to a user.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: An image capture device has a first image transfer method for storing a captured digital image on a storage medium and transferring the digital image to a communication device, and a second image transfer method for storing the digital image on the storage medium, reading the digital image from the storage medium and then transferring the digital image to the communication device. The first image transfer method or the second image transfer method is manually or automatically set.

Abstract: A software installation system comprises an interface component that receives a request to access data resident upon a flash memory card. An installation component compares a unique identifier associated with the data with a unique identifier embedded within the flash memory card, and the installation component determines whether to allow access to the data based at least in part upon the comparison. The installation component prohibits access to the data if the unique identifier associated with the data does not match the unique identifier embedded within the flash memory card.

Abstract: An enhanced migration descriptor migrates a plurality of source sub-pages in a large source page accessible by direct memory access devices. A splitter and selector are integrated into a configuration of a computer. Responsive to a request to migrate a large page containing the plurality of source sub-pages in the source page, the splitter divides a plurality of high order page numbers from a plurality of low order page numbers. The selector selects the high order page number of the large page and creates an enhanced migration descriptor comprising the high order page number and a size of the large page. The selector, by the enhanced migration descriptor, combines the low order page number for a sub-page with the destination address and size of the enhanced migration descriptor to migrate the large page and each of the plurality of sub-pages.

Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.

Abstract: A method, system, and computer usable program product for a self-tuning I/O device are provided in the illustrative embodiments. A change is detected in an adapter communicating with the I/O device, the I/O device being a consolidator configured to communicate with the adapter in a data network. A type of the adapter is determined. Values for each parameter in a set of parameters corresponding to the type of the adapter are determined. The values of a first subset of the parameters are applied to the consolidator, applying the values of the first subset causing the consolidator to be configured to operate in a preferred configuration with the adapter.

Abstract: A system and method for testing and calibrating a control unit including a microcontroller includes an influencing device and an adaptation unit. The adaptation unit includes a memory that can store at least part of a data of a data communication between the influencing device and the control unit. The memory can be read from and/or written to by the microcontroller of the control unit when the control unit is in an on state.