Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: I/O tracing is implemented in a system in which an I/O device is configured for protocol offload. A data unit having headers and payload is replicated and the replicated unit sent to the end node along with the payload data. In an alternative embodiment, the I/O device keeps track of the one or more protocol headers layers separately from the application payload. Information defining the relationship between the headers and payload is sent to the end node to enable it to reconstruct the data unit.

Abstract: An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operation having both input and output data. The TCW specifies a location of the output data and a location for storing the input data. The host computer system forwards the I/O operation to the control unit for execution. The host computer system gathers the output data responsive to the location of the output data specified by the TCW, and then forwards the output data to the control unit for use in the execution of the I/O operation. The host computer system receives the input data from the control unit and stores the input data at the location specified by the TCW.

Abstract: An accurate, highly reliable peripheral device control system is realized by issuing notifications related to a print job having the correct content from a printer driver with accurate timing and in the correct order, and conveying correct information to an application with accurate timing and in the correct order in a peripheral device control system that uses a low-performance printer. In an peripheral device control system composed of an information processing apparatus and a peripheral device, the information processing apparatus acquires peripheral device information related to the peripheral device from the peripheral device, generates job information from the peripheral device information, and notifies the job information. At this time, a notification not yet issued is created based on notified printing and printed page numbers and a current printing page number, and issued.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.

Abstract: A method, apparatus, and computer program product for processing a chained-pair linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying that a device command word (DCW) list is encoded in a data message associated with the first command message as part of the chained-pair linked transport control channel program. The method further includes receiving a second command message chained-pair linked to the first command message, the second command message specifying data attributes associated with the DCW list. The method additionally includes extracting the DCW list from the data message in response to receiving the data message, and executing the DCW list.

Abstract: An article of manufacture, an apparatus, and a method for determining an extended measurement word at a channel subsystem of an I/O processing system using data from a control unit are provided. The article of manufacture includes at least one computer usable medium having computer readable program code logic. The computer readable program code logic performs a method including sending a command message to the control unit, and receiving a transport response information unit message at the channel subsystem in response to sending the command message to the control unit. The computer readable program code logic additionally extracts a plurality of time values from the transport response information unit message as calculated by the control unit, calculates an extended measurement word as a function of the time values, and writes the extended measurement word to computer readable memory in the I/O processing system.

Abstract: A content processing apparatus includes a first transferor which transfers a predetermined content to an external device when accepting a transfer operation to any one of contents stored in a memory device. A predictor predicts a time period required for a transfer process of the content designated by the transfer operation, based on the time period taken for the transfer process of the first transferor and a size of the content designated by the transfer operation. A second transferor transfers the content designated by the transfer operation to the external device. A controller determines whether or not the time period predicted by the predictor falls below a reference based on a remaining amount of a battery, so as to permit a transfer process of the second transferor when the determined result is positive while restrict the transfer process of the second transferor when the determined result is negative.

Abstract: A method for expediting data access of a Universal Serial Bus (USB) storage device is disclosed. In a first embodiment, a data transmission procedure without the need of sending command block wrappers (CBW) is executed if a read command for reading data of a large memory space is received, and the addresses of the read commands are continuous. In a second embodiment, several write commands of continuous addresses are stored in a buffer area and combined into a larger single request command before sending to the USB storage device, so as to reduce the number of times of sending CBW and command status wrapper (CSW) required for the data transmission. In a third embodiment, more data are read and stored in a buffer area in advance when a read command is received, such that the next command can read data from the buffer area to improve the speed of reading data.

Abstract: A method to preserve a logical communication path in a data processing system, that includes a host computer, a storage controller that comprises a first logical control unit (“LCU”), and a logical communication path that is in communication with the host computer and the first LCU, comprising deleting the first LCU and setting a first status for same. The method then configures a second LCU, and establishes a second status for same, wherein the second LCU includes all or a portion of the first LCU, but is not the same as the first LCU. The deleting, setting, configuring, and establishing are performed while maintaining the logical communication path, which is in communication with the second LCU.

Abstract: An Electronic Media System is disclosed herein. The system preferably comprises a terminal, stored electronic data and an accessory unit. The terminal is located in a public location and includes stored electronic data such as downloadable historic and current electronic newspapers and magazines or movies which may be purchased via a slidable magnetic payment means and which may be connectably uploaded to the accessory unit. The hand held accessory unit is purchasable by users and may be used to store and display the downloaded data.

Abstract: A method, system, and computer program product containing instructions for handling legacy BIOS services for mass storage devices using system management interrupts. In response to receiving a request for an input/output service, a system management interrupt is generated to enter system management mode. A system management RAM (SMRAM) is accessible to code executing inside system management mode. Sub-operations to perform the requested service are identified, and code is executed outside the SMRAM to perform a sub-operation to fulfill the request. The sub-operations identified for execution outside SMRAM include any sub-operations that require waiting for data to be transferred. Other code executing inside the SMRAM may perform additional sub-operations that do not require waiting for data transfers to fulfill the request. System management mode is exited before invoking the code to perform the sub-operation to execute outside the SMRAM.

Abstract: Methods and arrangements of monitoring applications active on a plurality of computers are discussed. Embodiments include transformations, code, state machines or other logic to connect a plurality of computing devices via a keyboard video mouse (KVM) switch and to detect applications active on the computing devices. In some embodiments, each computing device may be connected to a display separate from the KVM switch. The embodiment may include detecting applications signaling a user for attention and displaying a list of active applications of the plurality of computing devices in response to a command from the user. The displaying may include giving priority to the applications signaling a user for attention.

Abstract: A method and system for data traffic management in a storage area network subsystem connected to multiple hosts via plural ports through a connection network is provided. Traffic management involves, for each port, determining input/output (IO) traffic utilization load of the port based on workloads from one or more hosts assigned to that port; and detecting if a port is in utilization overload. Then, upon detecting a port utilization overload, port traffic is managed by adjusting traffic utilization of the overloaded port and one or more other ports in the storage subsystem, to reduce traffic utilization of the overloaded port.

Abstract: In some embodiments a method is disclosed that includes creating a network connection status between a host device and a peripheral network device, determining characteristics of the peripheral device such as receive capacity or a quality of service classification for the transmission and flow control for performing control and data transfers. A transfer is initiated when a uniform serial bus request block (URB) is generated by a host application. The URB can have parameters that can be utilized to generate a transaction over a wireless network providing Quality of Service (QoS) guarantees. Other embodiments are also disclosed.

Abstract: A network device is described that concurrently executing more than one instance of an operating system on a single processor. Each of the instances of the operating system executes completely independent of the other instances. In this way, disparate instances may exist for the same operating system or for different operating systems. The techniques allow the processor to concurrently execute, for example, an instance of the operating system may emulate a routing engine and an instance of the operating system may emulate an interface controller. A hyper scheduler performs context switches between the operating systems to enable the processor to concurrently execute the instances of the operating system. The techniques may provide a low cost alternative to employing multiple processors within a network device, such as a router, to execute multiple independent operating systems.

Abstract: A device for data packet processing is disclosed. In one embodiment, the device includes a processor implemented on a chip, an on-chip internal segment memory accessible by the processor, an off-chip external segment memory and a data transfer channel between the internal segment memory and the external segment memory. The external segment memory comprises first and second memory segments wherein the first and second memory segments are different in size.

Abstract: The present invention discloses a method of editing a multi-media playing schedule for a digital photo frame, a system and a computer readable storage medium thereof, which are characterized in that users can edit a multi-media playing schedule on the data processing apparatus when the digital photo frame is electrically connected to the data processing apparatus, and after editing of the multi-media playing schedule is finished, the multi-media playing schedule is transmitted to the digital photo frame and stored in the digital photo frame. Therefore, the problem of being unable to edit complicated multi-media playing schedules due to simple operation interface of digital photo frames can be solved.

Abstract: A method and apparatus for associating geotag information obtained from a barcode with image or video data is provided. The apparatus includes a camera module for capturing an image or video of an object, a barcode decoding module for receiving barcode data related to the object and for extracting geotag information from the barcode data, and a processor for associating the geotag information with the image or video.

Abstract: A USB host system includes: a USB host module having a USB host function for performing USB transfer to/from a USB device; a different-function module having a predetermined function using transfer data that is to be an object of the USB transfer; at least one shared memory shared between the USB host module and the different-function module; and at least one dedicated memory exclusively used by the USB host module. At least part of management data for performing the USB transfer is stored in the dedicated memory.

Abstract: An interface between USB devices employs isolation techniques to provide electrical isolation of a USB signal for transmission of the USB signal between the devices. Unidirectional isolator channels are utilized to transmit the USB signals, and a selection of an isolator channel operating in an intended direction is performed by either direction control logic or a USB hub function. Logic may be employed to detect a device attempting to initiate a USB signal. The logic operates to enable a transmitter on a receiving side and isolate the USB signal through an isolator channel operating in a transmission direction.

Abstract: A distributed storage processing unit can generate data slices and determine metadata for each of the data slices. The metadata includes information that can be used to determine storage diversity preferences, which can include requirements that data slices generated from a common data segment each be stored in memories of the same (or different) type and model, memories with the same (or different) failure rates, memories having fast read (or write) characteristics, and so on. Decisions about which memory units to use for storing data slices can be made based on how closely the characteristics of the memories match the storage diversity preferences. The decision can be made at a distributed storage processing unit that generates the data slices, at a distributed storage unit receiving the data slices for storage, or elsewhere.

Abstract: A method of performing a burst read access at a memory device using a multiplexed data/address bus and a control signal including transferring a first portion of address information in a first phase via the multiplexed data/address bus to the memory device; transferring second portion of address information in a second phase via a multiplexed data/address bus to the memory device; transferring a series of data words from the memory via the multiplexed data/address bus; toggling the state of the control signal at the memory device as each data word is transferred; and suspending the transfer of the series of data words from the memory via the multiplexed data/address bus and the toggling of the state of the control signal.

Abstract: A cryptographic processing device 100 includes an interruption timing judgment circuit 101. The interruption timing judgment circuit 101 includes an interruption timing judgment register 101a, a transfer state reference unit 101b, and an interruption timing judgment unit 101c. The interruption timing judgment register 101a stores a table 200 used by the interruption timing judgment unit 101c to judge whether to interrupt transfer performed by a DMAC 102. The transfer state reference unit 101b monitors how many bytes among blocks read from a memory 14 the DMAC 102 has input into a cryptographic computing circuit 103. The interruption timing judgment unit 101c judges whether to switch a transfer target during transfer of image data by the DMAC 102, based on the table 200 stored in the interruption timing judgment register 101a and a result of the monitoring by the transfer state reference unit 101b (i.e. the number of transferred bytes).

Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.

Abstract: Method and system for processing storage and network packets is provided. The system includes a computing system executing a storage application for sending an input/output request for communicating with a storage device, the storage application transmits the I/O request to a storage driver that includes (a) an operating system interface to communicate with an operating system executed by the computing system and (b) a storage protocol interface that executes operations related to the storage protocol for processing the I/O request; wherein the storage driver sends the I/O request to a network driver that encapsulates the I/O request into a combined network and storage packet; and the encapsulated network and storage packet is transmitted via a network link using a network protocol.

Abstract: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

Abstract: A method and apparatus for determining a bandwidth needed for services to be provided over an Internet Protocol (IP) network such as a Voice over Internet Protocol (VoIP) network and a Service over Internet Protocol (SoIP) network are disclosed. For example, the service provider utilizes a tool (e.g., an algorithm or a software application) that calculates the effective compression ratio and effective data rate of traffic on an IP network based on customer specified traffic information and standards for coding, protocol overhead, sampling, etc. In one embodiment, the network service provider presents a menu to a customer to allow the customer to enter the pertinent traffic information. Once the traffic information is received, the tool will determine the Effective Data Rate (EDR) and Effective Compression Ratio (ECR).

Abstract: A substrate processing apparatus is capable of giving notice to a user to prevent an improper removal of a removable storage medium and providing a manipulation screen through which it can be determined whether the removable storage medium can be removed. The substrate processing apparatus comprising: a controller configured to control display of a manipulation screen through which substrate processing information is manipulated; and an attachment/detachment part to which a removable external storage device is attached, wherein when an external storage device is attached to the attachment/detachment part, the controller disposes and enables an external storage device remove button, and when an external storage device is not attached to the attachment/detachment part, the controller disables the button.

Abstract: A relay connector unit for communicating an electronic control unit with a plurality of electronic devices includes: a first connecting unit connected to the electronic control unit; a second connecting unit having a plurality of circuits connected to the electronic devices respectively; and a transferring unit connected to the first connecting unit and the second connecting unit. The transferring unit transmits first information received by the first connecting unit from the electronic control unit to at least one of the electronic devices through a corresponding circuit, on the basis of circuit identifying data included in first information, the circuit identifying data indicating the corresponding circuit to be transferred to or from. The transferring unit appends the circuit identifying data to second information received from one of the electronic devices through the corresponding circuit to transmit the second information to the electronic control unit through the first connecting unit.

Abstract: A data transfer system is provided, in which divided data generated by data generation terminals are randomly transmitted to data transfer apparatuses by a host terminal, a parameter list controlling the order of transfer of divided data is generated by a parameter list generation part, and a transfer processing part transfers divided data transferred in a DMA mode to an electron beam drawing apparatus according to the parameter list through a general-purpose high-speed data transfer bus by bypassing a CPU.

Abstract: An interface between USB devices employs isolation techniques to provide electrical isolation of a USB signal for transmission of the USB signal between the devices. Unidirectional isolator channels are utilized to transmit the USB signals, and a selection of an isolator channel operating in an intended direction is performed by either direction control logic or a USB hub function. Logic may be employed to detect a device attempting to initiate a USB signal. The logic operates to enable a transmitter on a receiving side and isolate the USB signal through an isolator channel operating in a transmission direction.

Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.

Abstract: A CPU reads a system initialization program from a first recording area and stores the read system initialization program to an internal memory, and then reads the system initialization program from the internal memory and executes the system initialization and initialization of a second recording area. A DMA control unit transfers a system control program included in the program from the first recording area to the second recording area without through the CPU. A memory management unit manages a processing state of the transfer of the system control program to the second recording area by the DMA control unit. The CPU reads the program from the second recording area and executes the system control in collaboration with the memory management unit.

Abstract: A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one embodiment, a system of an integrated circuit includes a signal line located in the integrated circuit to communicate an electrical signal, a receiver circuit located in the integrated circuit coupled to the signal line, a transmitter module located in the integrated circuit to communicate a data stream to the receiver circuit through the signal line, and a throughput monitor circuit coupled to the signal line to measure a throughput value during a communication period of the data stream from the transmitter module. The system may include a processor module located in the integrated circuit configured to interrupt an operation of the transmitter module and a receiver module if the throughput monitor circuit generates the interrupt signal.

Abstract: A system capable of efficiently transferring a command set for controlling an image forming apparatus to the image forming apparatus from a host apparatus. A command separate/storage unit separates an image forming command set into a context command set and an object command set, and allocates both command sets in a main memory device. A command read instruction transmission unit transmits a command read instruction having a transfer size and a storage address of each of the allocated context command set and object command set, to the memory access controller. The memory access controller compares the storage address of the context command set included in the received command read instruction with a previous storage address, and reads the context command set from the main memory device only when both storage addresses differ from each other.

Abstract: An apparatus and associated method are provided for performing a storage transaction associated with a network I/O command by employing an ASIC having an interconnect selectively coupling a plurality of dedicated purpose function controllers in the ASIC to a policy processor via a list manager in the ASIC communicating on a peripheral device bus to which the policy processor is connected.

Abstract: A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.

Abstract: Methods and systems for automatically, dynamically reconfiguring multiplexing functions of a PHY of a SAS device in response to monitored performance of the PHY and/or in response to changes in configuration of devices in the SAS domain. A SAS device such as a SAS initiator or a SAS expander in a SAS domain may monitor performance of PHYs of the device to detect bandwidth utilization and may reconfigure multiplexing functions of a PHY to improve bandwidth utilization of the PHYs of the device. The device may also detect changes in the topology of the SAS domain such as addition of new devices or removal of device and adjust multiplexing functions of its PHYs accordingly to improve performance of communications in the SAS domain.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract: A recording and/or reproducing apparatus includes a plurality of devices in which a first device has a connecting unit connected with a host device to perform a data transfer with the host device, a second device shares a temporarily recording area with the first device to perform the data transfer between the first and second devices via the temporarily recording area, and the data transfer is performed by using the temporarily recording area shared with the first device and using the connecting unit of the first device when the second device performs the data transfer with the host device, in this way, a power consumption is reduced.

Abstract: A data processing system including a processing unit on which a control program runs, a plurality of operating systems (OS's) configured to run under control of said control program, a Peripheral Component Interchange (PCI) bus coupled to the processing unit, and a channel adaptor for data transmission/reception, wherein: the channel adaptor is coupled to the PCI bus on a PCI bus side of the channel adapter, and the channel adapter includes only one connecting port on an input/output (I/O) side of the channel adapter; an input/output process is executed between each OS and said channel adaptor by using input/output process control data specifying input/output (I/O) data, the input/output process control data being provided via a Queue Pair having a Queue Pair identifier and including a Send Queue, Receive Queue and Complete Queue; configuration information is provided, exclusively defining the Queue Pair identifier of said Queue Pair of said input/output process control data which is usable exclusively by eac

Abstract: Systems, methods, and computer-readable media for resuming a media object presented following a data loss event are provided. A physical disconnection that occurs at a point during the presentation of the media object is detected. The physical disconnection interrupts the presentation of the media object. Upon detecting the physical disconnection, a reestablishment of the physical connection is detected. Subsequently, an option to resume the presentation of the media object at the interrupted point is presented to a user.

Abstract: Methods and systems for input/output pads in a mobile multimedia processor are disclosed and may include receiving data from a host device in an integrated circuit having at least one contact pad and generating at least one control signal that controls the contact pads. The received data may be processed by the MMP based on the generated at least one control signal, or may be passed through the MMP in a bypass mode based on the control signal, thereby allowing the received data to pass through the MMP without processing to an external memory via the at least one contact pad, thereby sharing the external memory with the host device. The data may be transferred to external memory coupled to a contact pad on the MMP when the received data is to be passed through the MMP. The received data may be stored temporarily before transfer to an external device.

Abstract: A data transfer system includes: a local unit (LU) that transmits data from the USB device connected to a local computer (LC) to a remote computer (RC); and a remote unit (RU) that acquires the data from LC and transfers the data to an application. LU includes: a unit that receives the data from the USB device to store the data in a memory, and notifies the USB device about the reception: and a unit that reads non-transferred data, converts the data to a network format, and transfers the data to RC when the amount of non-transferred data stored in the memory is equal to or greater than a threshold. RU includes: a unit that receives the data from LC and stores the data in a memory: and a unit that reads the unread data in the memory and transmits the data in an application format.

Abstract: Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

Abstract: A computing system having an apparatus for providing an inline data conversion processor. The inline data conversion processor includes a host processor interface, a network interface, a peripheral interface, and a packer stream address for defining a data transformation applied to a block of data as it passes between the host processor interface and the peripheral and network interfaces.

Abstract: An asynchronous serial communication method and the apparatus including a sender transmitting a one bit of serial data by firstly making a signal transition on the data line, secondly putting the one bit of serial data on the data line after a predetermined time T1 yet before another predetermined time T1+T2, and a receiver receiving the one bit of serial data by firstly detecting the signal transition on the data line and secondly capturing the one bit of serial data after a predetermined time T3 (where T3>T1+T2).