Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: A webcasting system and the audio data regulating methods to be used in the webcasting system are presented. The webcasting system includes a host and an audio playing apparatus. The host, which is loaded with an operating system and drivers, determines the audio data output according to an expected data received by the operating system. The drivers provide the expected data according to the audio data received and transform the audio data for network transmission. The audio playing apparatus receives the network data and processes the network data for audio playing.

Abstract: A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation.

Abstract: In a data processing system having a processor, a DMA controller, a peripheral, and a memory, a method includes initiating a DMA transfer between the peripheral and the memory, wherein the DMA transfer comprises N subsets of data to be transferred between the peripheral and the memory, N having a value of two or more; asserting, by the peripheral, an event status indicator each time an event is completed by the peripheral; in response to each assertion of the event status indicator, the peripheral, based on a data request enable signal from the DMA controller, performing one of asserting a data request signal provided to the DMA controller or providing an interrupt request to the processor; and in response to each assertion of the data request signal, the DMA controller initiating transfer of a next subset of data of the N subsets of data between the memory and the peripheral.

Abstract: A data transmission method is provided, which includes: obtaining a current queue length of a queue corresponding to an output port; when the current queue length meets a back-pressure requirement, determining a back-pressure priority corresponding to the current queue length according to the current queue length and a mapping relationship between a preset queue length and the back-pressure priority, and generating back-pressure information, where the back-pressure information inhibits a line card from sending data with a data priority less than or equal to the back-pressure priority to the output port; and sending the back-pressure information to a line card.

Abstract: Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.

Abstract: A system and methods of uploading payload data to user buffers in system memory and of uploading partially processed frame data to legacy buffers allocated in Operating System memory space are described. User buffers are stored in a portion of system memory allocated to an application program, therefore data stored in user buffers does not need to be copied from another portion of system memory to the portion of system memory allocated to the application program. When partially processed frame data is uploaded by hardware to a legacy buffer in system memory, a tag, uniquely identifying the legacy buffer location is transferred by the hardware to a TCP stack, enabling the TCP stack to locate the legacy buffer.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: The present invention relates to a method for data output control, which comprises: obtaining the length of idle bits in the cache queue of a data output interface, and if the idle-bit length is equal to or longer than the length of the data to be sent on the interface, putting the data into the cache queue of the interface. In addition, this present invention discloses another data output control method, and two types of data output control apparatuses. Using this invention can avoid flow interruption.

Abstract: Methods, systems, and apparatus are provided for enabling communication with a computer management device. According to a method one or more vendor specific commands for communicating with a management device are defined according to a first communication standard. The one or more vendor specific commands are then transmitted to the management device over a communication link conforming to a second communication standard. A device conforming to the second communication standard may be emulated on the communication link. If vendor specific commands are received by the management device that are not intended for the emulated device, the commands may be used for communicating with the management device.

Abstract: A data transfer apparatus includes a virtual channel unit configured to time share a serial bus for a first virtual channel and a second virtual channel and include a buffering control unit configured to receive data via the first virtual channel and the second virtual channel, first and second receive buffers being configured to store the data received via the first virtual channel and the second virtual channel, respectively; and a switching unit configured to control storing the data received via the first virtual channel in the second receive buffer when the buffering control unit receives the data from another data transfer apparatus which is configured to use only the first virtual channel and the capacity of the first receive buffer is smaller than that of the second receive buffer.

Abstract: A method of operating an input/output interface is described. The method comprises eliminating a current path into an output pin of an input/output interface while the input/output interface receives an operational power signal during a first mode of operation; and enabling the current path into the output pin of the input/output interface to limit a voltage magnitude externally applied to the output pin of the input/output interface during a second mode of operation.

Abstract: A storage device is connected to a tape library having a plurality of tapes holding data and a host device. The storage device includes a receiving section, a first determining section and a reading section. The receiving section receives a request for data held in one of the tapes from the host device. The first determining section determines whether the data requested by the host device is stored in a storage section on the basis of the request received by the receiving section. The reading section reads the data in a predetermined amount to a memory from the tape in a case where the first determining section determines that the data is not stored in the storage section. The transferring section transfers the data in the memory to the host device and writes it on the storage section.

Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.

Abstract: Method and apparatus for managing item sequence numbers in an item processing system. The invention provides for overrun prevention and management of item sequence numbers, which form a part of an image key. In example embodiments, a buffer is provided to determine how close a current item sequence number (ISN) is permitted to be to an overrun value. When the current ISN reaches the buffer value, new entries of documents are prevented or at least restricted from being processed. In some embodiments, a “force mode” is provided in which a sorter can be made to start a new entry even if the buffer value has been exceeded. In such an embodiment, the system can be set up so that a hard stop is enforced when the ISN is within a certain range of the overrun value.

Abstract: A method, system, and computer program product containing instructions for handling legacy BIOS services for mass storage devices using system management interrupts. In response to receiving a request for an input/output service, a system management interrupt is generated to enter system management mode. A system management RAM (SMRAM) is accessible to code executing inside system management mode. Sub-operations to perform the requested service are identified, and code is executed outside the SMRAM to perform a sub-operation to fulfill the request. The sub-operations identified for execution outside SMRAM include any sub-operations that require waiting for data to be transferred. Other code executing inside the SMRAM may perform additional sub-operations that do not require waiting for data transfers to fulfill the request. System management mode is exited before invoking the code to perform the sub-operation to execute outside the SMRAM.

Abstract: In some embodiments, a switching device is configured to couple a first computer to a first peripheral device and one or more second peripheral devices. The switching device includes: (a) a switch configured to couple to the one or more second peripheral devices; (b) a first hub including: (1) a first upstream port configured to couple to the first computer; (2) a first downstream port configured to couple to the first peripheral device; and (3) at least one second downstream port coupled to the switch. Other embodiments are also disclosed herein.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.

Abstract: A bulk transfer control method of a universal serial bus (USB) device includes a timer for counting transmission time of a buck transfer. When the transmission time counted reaches a transmission time setting value, a trigger signal is issued to a transfer end event generator. Then, the transfer end event generator issues a transfer end event signal to a data processing unit so as to end the bulk transfer. Moreover, a USB device and its bulk transfer control circuit are also provided.

Abstract: A data transfer device includes a storage controller that stores received response data in a buffer with respect to each piece of identification information included in the response data when receiving the response data from a first device, the response data being transferred from the first device in response to a transfer request transferred from a second device, a counting unit that counts a number of pieces of the response data stored in the buffer by the storage controller with respect to each piece of the identification information, and a determination unit that determines whether the number counted by the counting unit reaches a specified value preliminarily set with respect to each piece of the identification information.

Abstract: System and method for a four-slot asynchronous communication mechanism with decreased latency. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots. The client may comprise first information indicating a status of write operations to the data structure on the host and second information usable to determine a slot that should be written to. If the first information indicates that the second information is accurate, the client may determine which slot in the data structure should be written to based on information stored only on the client device. The determined slot may be the slot that has not been written to more recently of the pair of slots that has not been read from most recently. The client may write data to the determined slot. The client may update at least a portion of the information stored on the client device to reflect the write of data to the determined slot.

Abstract: The present invention discloses a single wire transmission interface comprising: a signal detection circuit detecting level switchings of a transmission signal from a single wire, and generating an enable signal and a decoded signal corresponding to the transmission signal, the level switchings including first switchings from a first level to a second level and second switchings from the second level to the first level, wherein the enable signal starts according to one first switching of the transmission signal, and stops when no first switching occur in a predetermined period after one second switching of the transmission signal, and wherein rising edges (or falling edges) of the decoded signal correspond to the first switchings of the transmission signal; a counter, under enablement by the enable signal, counting a number of the rising edges (or the rising edges) of the decoded signal or the first switchings of the transmission signal, and generating a count; a single short pulse generator generating a shor

Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: Each received piece of configuration data is added at a next currently free location in a volatile buffer. The contents of the volatile buffer are compressed after adding each received piece of configuration data. The compression result is stored in a non-volatile flash memory. If the compression result was shorter than a limit, it is allowed to be overwritten in the flash memory by a next compression result. If the compression result was longer than the limit, it is stored in the flash memory and the next compression result is directed to a different location in the flash memory.

Abstract: There is provided a data transfer method in an IEEE1394 system including a band request node and a transfer band management node. The method includes generating, at the band request node, a transfer request that can detect a data amount of transfer data and transmitting the transfer request from the band request node to the transfer band management node, determining, by the transfer band management node, whether a transfer band requested by the transfer request is ensured or not, notifying, from the transfer band management node, the band request node of the determination result, and transferring data from the band request node according to the determination result.

Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.

Abstract: There are provided a transfer request module 2 for interpreting a data transfer request received from outside; a transfer instruction module 1 including a receiving section 10 for receiving the data transfer request after interpretation by the transfer request module 2, a remaining data setting section 12 for setting a data volume to be transferred in accordance with the data transfer request after the interpretation the receiving section 10 receives, a remaining data retaining section 16 for holding the data volume set by the remaining data setting section 12, a remaining data reading section 13 for reading the data volume held in the remaining data retaining section 16, a counter setting section 14 for setting a limit of the number of times of transfer unit settings in accordance with the data transfer request after the interpretation the receiving section 10 receives, a counter 17 for holding the limit of the number of times of the settings carried out by the counter setting section 14 and for counting dow

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: A DMA control system includes: a plurality of DMA control units that are controlled in a manner that, while one of the plurality of DMA control units use a transmission path, the other DMA control units other than the one of the plurality of DMA control unit are prevented from using the transmission path; and a transfer instruction unit that defines transfer amounts of DMA transfers for the respective DMA control units and gives transfer instructions thereto. The transfer instruction unit, when the transfer instruction unit gives a transfer instruction to a first DMA control unit of the plurality of the DMA control units, defines a transfer amount for the first DMA control unit and gives the transfer instruction thereto in accordance with a state of utilizing a second DMA control units of the plurality of the DMA control units.

Abstract: A DMA transfer control device includes a setting register group for setting transfer informations, a number-of-transfers register to which the number of transfers to be performed is set, and which updates a value thereof every time one DMA transfer is completed, a transfer control unit, a secondary setting register group for setting other transfer informations different from the transfer informations, and a specified ordinal-number-of-transfer register. Every time one DMA transfer is initiated, either a value of the setting register group or a value of the secondary setting register group is selected for each of the transfer informations in accordance with a result of an arithmetic operation between a value of the number-of-transfers register and a value of the specified ordinal-number-of-transfer register, and inputted to the transfer control unit. As a result, by making settings for one DMA transfer, it is possible to temporarily change the transfer informations.

Abstract: A USB device can be configured for multi-packet data transfer to and from endpoints with minimal software intervention. Minimal software intervention allows a Central Processing Unit (CPU) of the USB device to handle other tasks, maximizing USB bus utilization.

Abstract: A webcasting system and the audio data regulating methods to be used in the webcasting system are presented. The webcasting system includes a host and an audio playing apparatus. The host, which is loaded with an operating system and drivers, determines the audio data output according to an expected data received by the operating system. The drivers provide the expected data according to the audio data received and transform the audio data for network transmission. The audio playing apparatus receives the network data and processes the network data for audio playing.

Abstract: Provided are a method, system, and article of manufacture, in which a logical path is established between a control unit and a channel over a fiber channel connection. Code for persistent information unit pacing is loaded into the control unit and the channel. An indicator is set in node descriptors of the control unit and the channel to indicate concurrent enablement of persistent pacing while retaining the established logical path between the control unit and the channel.

Abstract: A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract: A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value.

Abstract: A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.

Abstract: A transfer apparatus includes a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer block. The transfer block can automatically transfer candidate data to a memory device when a connected status is detected by the connection status block, the transfer candidate stored status is detected by the storage status detection block, and a no-operation status is detected by the no-operation status detection block.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: A method for expediting data access of a Universal Serial Bus (USB) storage device is disclosed. In a first embodiment, a data transmission procedure without the need of sending command block wrappers (CBW) is executed if a read command for reading data of a large memory space is received, and the addresses of the read commands are continuous. In a second embodiment, several write commands of continuous addresses are stored in a buffer area and combined into a larger single request command before sending to the USB storage device, so as to reduce the number of times of sending CBW and command status wrapper (CSW) required for the data transmission. In a third embodiment, more data are read and stored in a buffer area in advance when a read command is received, such that the next command can read data from the buffer area to improve the speed of reading data.

Abstract: The present invention discloses a method of editing a multi-media playing schedule for a digital photo frame, a system and a computer readable storage medium thereof, which are characterized in that users can edit a multi-media playing schedule on the data processing apparatus when the digital photo frame is electrically connected to the data processing apparatus, and after editing of the multi-media playing schedule is finished, the multi-media playing schedule is transmitted to the digital photo frame and stored in the digital photo frame. Therefore, the problem of being unable to edit complicated multi-media playing schedules due to simple operation interface of digital photo frames can be solved.

Abstract: A serial ATA interface interfaces an ASIC with a HDD. A transfer start monitoring unit monitors start of data transfer between the ASIC and the HDD and a transfer completion monitoring unit monitors completion of the data transfer. A power management control unit controls power consumption of the ASIC and the HDD based on monitoring results obtained from the transfer start monitoring unit and the transfer completion monitoring unit.

Abstract: Optimizing collective operations using direct memory access controller on a parallel computer, in one aspect, may comprise establishing a byte counter associated with a direct memory access controller for each submessage in a message. The byte counter includes at least a base address of memory and a byte count associated with a submessage. A byte counter associated with a submessage is monitored to determine whether at least a block of data of the submessage has been received. The block of data has a predetermined size, for example, a number of bytes. The block is processed when the block has been fully received, for example, when the byte count indicates all bytes of the block have been received. The monitoring and processing may continue for all blocks in all submessages in the message.

Abstract: A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one embodiment, a system of an integrated circuit includes a signal line located in the integrated circuit to communicate an electrical signal, a receiver circuit located in the integrated circuit coupled to the signal line, a transmitter module located in the integrated circuit to communicate a data stream to the receiver circuit through the signal line, and a throughput monitor circuit coupled to the signal line to measure a throughput value during a communication period of the data stream from the transmitter module. The system may include a processor module located in the integrated circuit configured to interrupt an operation of the transmitter module and a receiver module if the throughput monitor circuit generates the interrupt signal.

Abstract: A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.

Abstract: A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation.

Abstract: A modular system comprises an appliance and an adaptive adapter configured to alternately couple two consumer electronic devices to the appliance and to supply a different electrical service between the appliance and the consumer electronic devices depending on the device selected. The adaptive adapter supplies a first category of electrical service to a first consumer electronic device and a second category of electrical service to a second consumer electronic device. The appliance may comprise a refrigeration appliance and the adaptive adapter can couple the consumer electronic devices to the appliance.