Abstract: A DMA control circuit controls DMA transfer between a flash memory and a main memory. An S/P bus conversion circuit converts serial data output from the flash memory into parallel data and outputs the parallel data to the main memory. This eliminates the need for the CPU downloading file data from the flash memory to the main memory, allowing connection of a non-volatile memory with a large capacity, without reduction in the processing speed of the system.

Abstract: A method for ensuring data coherency in buffered direct memory access (DMA) data transfers. The DMA controller realizes the last piece of data is being transferred to the write buffer. The DMA controller then sends a “Last Write Data” signal to the external memory access arbitration unit. The external memory access arbitration unit then allows completion of all pending memory operations. If a memory request occurs, a wait line is asserted such that memory operations (i.e., reading from, or writing to, the memory) are prevented for all sources other than the DMA channel associated with the “Last Write Data” signal. The external memory access arbitration unit also grants priority to the DMA channel associated with the “Last Write Data” signal. This effectively flushes the write buffer and completes the buffered DMA data transfer. The external memory access arbitration unit then deasserts any asserted wait lines and memory operations are no longer prevented.

Abstract: A system and corresponding method for improving set-top box boots up efficiency while, at the same time, reducing the memory allocation required for set-top box boot-up is disclosed. The boot-up method includes performing a vertical direct memory access transfer of relevant program instructions from a system non-volatile memory to system main memory. The transferred program instructions are then re-arranged into consecutive locations within the main memory.

Abstract: A data bus bridge circuit and method are provided for coupling a slave device with a data bus in a system in which data words are transferred between a master device and the slave device over the data bus. The bridge circuit removes master-induced stalls of burst transfers by converting those burst transfers into a plurality of separate, independent sub-bursts.

Abstract: A system, method and article of manufacture are provided for storing an incoming datagram in a switch matrix of a switch fabric. The switch matrix has a pair of buffers with each buffer having a pair of portions. Data of a datagram is received and the buffer portions are sequentially filled with the data. Periodically, transfer of data is allowed from the buffers into the switch matrix. At each period where transfer of data is allowed in the sequence that the buffer portions were filled, the data in one of the buffer portions may be transferred into the switch matrix.

Abstract: Provided are a method, system, and program that configures an address window of a device controller that communicates with an initiator over a bus, wherein the device controller accesses requests transmitted to one address in the address window on the bus, and configures a maximum number of outstanding read requests the initiator is capable of having to memory addresses in the address window based on a size of the address window.

Abstract: Methods and systems are provided to fast fill media players and buffers associated with media players. A bandwidth associated with initial startup of a media player is overloaded to rapidly fill the buffer and initiate the media player. Alternatively, multiple simultaneous data communication sessions are established with a media data source device, and the media data are concurrently received from the simultaneous sessions into the buffer or transferred of out the buffer at startup, thereby decreasing the latency associated with initiating the media player.

Abstract: Inform writes to inform a controller of availability of a plurality of replacement data buffers are optimally batched as a single message. Batching the inform writes lets the controller maintain control of a bus, thereby letting the controller continue with input operations with less interruption, while still allowing for timely replenishment of data buffers that can be made available to the controller. The number of available data buffers to indicate in the single message can be chosen so that the controller need not be starved of data buffers while waiting for a threshold number of available data buffers to be reached.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions, a burst controller for executing the burst instructions, a burst instructions element for providing burst instructions in a sequence for execution by the burst controller, and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute. Burst instructions are provided by the first processor to the burst instructions element and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the data buffer in accordance with burst instructions executed by the burst controller.

Abstract: An addressing scheme and associated hardware allows for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells. The peripheral devices include a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays and an address sequencer for routing certain of the address bits to the reorder circuit during a read operation. The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device.

Abstract: A bus arbiter (34) monitors characteristics associated with the type of information that is transferred via a global data bus (12) during burst transactions of information. A user-controlled arbitration policy register (56) may be programmed with values that are decoded to control whether interruption by a requesting bus master are permitted. Various factors can be used to determine interrupt permissions. Examples of such factors include the type of requesting device, whether a burst transaction is bounded or unbounded, whether a transaction is a read or a write of a system memory and the identity of the particular device requesting bus mastership.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: A FIFO buffer arrangement is disclosed that is capable of buffering and transferring data between multiple input and output datapaths of varying widths. All of the input and output buses may be used to transfer data concurrently. Data that are written to the FIFO via any of the input buses may be extracted from the FIFO via any of the output buses. The FIFO efficiently carries out all necessary width conversions when performing the data transfers.

Abstract: A conversion circuit is devised to convert burst signals referencing to a plurality of clocks, respectively. A burst signal referencing to a first clock is decomposed into a plurality of non-burst signals by a plurality of phase signal generators and corresponding signal fetching units. The plurality of non-burst signals are converted to signals referencing a second clock by a plurality of converters and those signals are synthesized into an output signal by a synthesizer. Therefore, the burst signal referencing to the first clock can be converted to the burst signal referencing to the second clock.

Abstract: The present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. A remote memory controller of the present invention may ensure that an acknowledge signal is sent only after a memory operation has been actually completed. This may provide for remote direct memory access without coherency problems and data corruption problems while a high bandwidth data flow internal architecture is being utilized.

Abstract: DMA transfer request signals corresponding to respective channels are received and held in respective transfer request holding circuits. DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lower priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.

Abstract: For improving data efficiency of a bus in a system using address/data multiplex bus, in a processor for information processing equipment, there are provided buffers which store plural sets of write addresses and data for a system bus, a comparator for deciding whether write addresses in succession forming a continuous write address exist in the write addresses stored in the buffers, and apparatus for converting access corresponding to writing operations for the continuous write addresses into a fixed length burst transfer protocol which can be transferred with a series of continuing data cycles following one address cycle, when the comparator 27 decides that write addresses in succession exist.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data storage registers on the data communication connections during a predetermined number of consecutive clock cycles by adjusting a burst length of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: A data processing system includes a bus, a plurality of devices connected to the bus, and a unit for executing data transfer between at least two of the plurality of devices via the bus, using one of a first bus cycle mode that enables data transfer with handshaking operation therebetween and a second bus cycle mode that enables stream data transfer without handshaking operation therebetween.

Abstract: A system and method for increasing the performance of a flash-based storage system, using specialized flash memory controller(s). Several methods of performance improvement are suggested such as adding DMA capability to flash memory controller to reduce the data transfer time; connecting flash chips to a multitude of flash memory controllers, which allow continuation of the data transfer to the system, even after the page programming operation has started; and connecting flash chips to a multitude of DMA-capable flash memory controllers to allow data transfer directly from one flash chip to another. In addition, a multi-controller design is suggested, which efficiently combines these performance-improving methods. In its best mode of operation, the present invention is a Flash-based storage system with several flash controllers or a multi-controller with DMA interface, organized in a way that reduces the page programming, page fetch and page copy time.

Abstract: The present invention is directed to a buffer partitioning system and a method employing the system to dynamically partition buffer resources among multiple data streams. The buffer partitioning system utilizes context information relating to the streaming data to control the flow of data through the buffer resource. By including a buffer partitioning system, multiple data streams may be more efficiently transferred through buffer resources thus resulting in faster data transfers.

Abstract: A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to process a message written in the local memory. The circuit may operate independently of the processor. The circuit may be configured to (i) monitor writes to the local memory for the message having a first pointer and (ii) program the DMA engine to copy a first buffer identified by the first pointer in response to the first pointer having a non-null value.

Abstract: According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the data transfer and terminate the data in burst upon completion of a portion of the data transfer.

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract: A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base address and linear or interleaved burst sequence controls. For every I/O, eight bits of data are presented to a 9-to-1 multiplexer. The first of eight bits in the burst sequence is the access time-limiting bit and is preselected by the burst base addresses of the 9-to-1 multiplexer. Subsequent bits in the burst sequence have extra half-cycles to be output, and use look-aside 8-to-1 multiplexers controlled by a burst counter with timings synchronized to the burst data clock timings.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: Bus control apparatus solves the problem that a high-speed bus which supports only burst transfer cannot be used when the boundary of a transfer memory address is not coincident with a unit boundary. A scanner controller and printer controller connected to a G bus capable of performing only burst transfer and a B bus capable of performing even single transfer determine from the address and data length of data to be transferred whether the data does not match the memory boundary. If the data does not match this boundary, a data portion which is not accommodated within the burst transfer unit is single-transferred using the B bus. A data portion which is accommodated within the burst transfer unit is burst-transferred using the G bus.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: The present invention, generally speaking, provides an efficient method of sending a long message from a first compute node to a second compute node across an interconnection network. In the first compute node, a message header field is set to a predetermined value and the message is sent. In the second compute node, the message header is received and processed, and a memory location is read in accordance with the contents of a base address register and an index register. Using Direct Memory Access, the message is then stored in memory at a storage address determined in accordance with the contents of the memory location. Preferably, the storage address is aligned on a memory page boundary.

Abstract: A digital device interface for transferring information between a processor and a control device includes a first serial peripheral interface (SPI), e.g., with “data in,” “data out” and “clock” ports, in serial communication with a second SPI. The first SPI can be coupled to, and associated with, the processor; the second SPI, with the control device. A first transfer logic section, e.g., a shift register engine, transfers bytes, word, longwords or other multi-bit datum between the processor and the control device. A second transfer logic section effects a transfer transaction between the processor and the control device—that is, the transfer of plural multi-bit datum relating to a common data access operation or a common data generation operation. For sensor-type control devices, such a transaction may include, for example, the “continuous” transfer of data sensed by the device.

Abstract: A DMA controller includes a burst/single mode control circuit for automatically converting a DMA transfer operation mode to a burst mode and/or a single mode regardless of a data transfer counter value, and for performing the DMA transfer operation. The burst/single mode control circuit carries out the burst mode DMA transfer operation without the need for a control operation of the CPU a number of times corresponding to a quotient which is the result that the data transfer counter value divided by the burst length, and carries out successively the single mode DMA transfer operation by the number of times corresponding to the remainder of the division.

Abstract: A method to buffer a data stream at its reception, performed by a receiver of the data stream. Data sent by a sender is transferred over a connection-less network in packets encapsulated into frames. The method of buffering itself includes the steps of storing the packets into a buffer of a specific size (Bs). When the receiver received at least one of the packets, its delay (jitter) is measured and compared with some predefined value. Depending on the result of that comparison, said buffer size (Bs) will be adapted dynamically such to optimize the transfer of the packets according to some predefined criteria.

Abstract: The read position or write position of data is decided by the base address of a ring buffer and an offset from the base address and the offset is updated by the amount of DMA-transferred data. When the offset becomes equal to or more than a value that indicates a total amount of transferred data, the offset is reset to zero to generate an address for circulating through and accessing the ring buffer. Moreover, a stop address showing the stop position of the DMA transfer operation is set to update the stop address by the amount of data read from or written in the ring buffer without depending on the DMA transfer operation. When the offset coincides with the stop address, the DMA transfer operation is stopped.

Abstract: Two transfer modes of a band-guaranteed cycle and an event-driven asynchronous cycle are defined in a multimedia bus. In the band-guaranteed cycle, stream data is transferred between nodes in real time using a reserved band for each cycle time. Both a single-edge access and a double-edge access are provided for the stream data transfer in the band-guaranteed cycle, and it is possible to select one of the single-edge access and double-edge access for each data transfer between nodes. The transfer band of stream data on the bus can thus be expanded and the transfer efficiency of AV stream can be improved.

Abstract: A memory controller is provided that has an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester. It also has a RAM controller for connection with a RAM connected to the memory data and address buses and/or a ROM controller for connection with a ROM connected to the memory data and address buses. Each such RAM controller and/or ROM controller are connected to the access priority arbiter with one or more control lines. The access priority arbiter receives access requests on one or more of the requester buses and grants access to the memory address and data bus to one requester bus at any one time based on logic internal to the access priority arbiter.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: An embedded system that has a general purpose central processing unit CPU and a digital signal processor DSP, the CPU is adapted to perform various tasks such as code consuming tasks associated to the transmission and reception of information and the DSP is adapted to perform tasks that require less program code and that are associated to the transmission and reception of information. Most of the time the CPU can handle tasks that are not related to the transmission and reception of data.

Abstract: A print data management system includes a memory to store print data; a controller to transfer the stored print data to a printer; and a user interface to indicate to a user a degree of occupation of the memory by the print data, the user interface including first and second distinct forms of indication respectively corresponding to a range of low occupation and a range of high occupation of the memory, the user interface further including a setting unit to variably set boundaries of at least one of the ranges of high and low occupations by the user.

Abstract: Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operation can be successively carried out without latency even though an address region moves from the first semiconductor memory device to the second memory device.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this invention, parallel size calculation/write annulment decision capability is employed. This technique facilitates the process of setting up complex transfers without risking brute force inefficient processor cycles. Annulment determination allows detection of cases when a set of data cannot be output immediately and the destination pipeline postpones execution of the write command.

Abstract: An integrated circuit comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The logic circuit may be configured to generate a predetermined number of the internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) one or more control signals. The generation of the predetermined number of internal address signals may be non-interruptible.

Abstract: A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.

Abstract: Disclosed is a frame processing device (10) for processing frames having a plurality of data bits, a plurality of flag bits and a plurality of zero bits inserted within the data bits to avoid there being a pattern of the data bits which coincide with the pattern of flag bits, the frame processing device (10) comprising a host interface (16) for receiving and transmitting said frames having a first data rate, an encryptor (22) and decryptor (28) for encrypting and decrypting the data bits respectively, a network interface (26) for transmitting and receiving encrypted data bits having a second data rate, and an adaptive first-in first out (FIFO) buffers (22 and 30) for compensating for the difference between said first data rate and second data rate.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.

Abstract: A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.

Abstract: In a first embodiment, an applications programming interface (API) implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an asynchronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more, asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The API also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors.