Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue.

Abstract: Methods and apparatus for remotely controlling an ATA device via a packet-based interface are disclosed. In one implementation, a remote host constructs command blocks corresponding to the ATA register-delivered commands that it would like executed. These command blocks are packetized and transported to a packet-to-ATA format bridge. At the bridge, each command block is parsed, and appropriate ATA read or write register commands are performed. The bridge performs requested data transfers via the packet-based interface. This embodiment can allow a non-ATAPI ATA device to connect externally to a host computer, e.g., via a USB plug-and-play packet interface. This can provide inexpensive and portable mass storage capability that does not require internal mounting or external routing of the short ATA cables that are intended for internal use only.

Abstract: In one embodiment, monitoring data traffic through a memory controller; and dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: A device for writing descriptors, the device including a local memory comprising a multiplicity of mini-queues, wherein each of the mini-queues temporarily stores a plurality of descriptors, wherein each of the descriptors is associated with one of the data packets. Additionally including an output memory comprising a multiplicity of output queues, wherein each of the output queues in output memory is associated with one of the queues in said local memory, and a burst writer which writes N descriptors simultaneously from the mini-queue in the local memory to its associated output queue in output memory.

Abstract: A computer system includes a host bus, a CPU connected to the host bus, a main memory connected to the host bus, a cache memory and a memory controller. The cache memory is connected to at least one of the host-bus and the CPU, and stores cache data. A tag address and a flag are provided for each of the cache data and the flag indicates one of a clean state in which the corresponding cache data is written back into the main memory and a dirty state in which the corresponding cache data is not yet written back into the main memory. The memory controller is connected to the host bus, the cache memory and the main memory. The memory controller writes back dirty write back cache data into the main memory in a continuous write back mode, when the host bus is not used, wherein the dirty write back cache data is a part of the cache data stored in the cache memory, and each of the dirty write back cache data is not written back and includes a predetermined portion in the tag address.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: A controller for a memory partitioned into a plurality of banks and divided into addresses that are accessed by a plurality of row access strobe signals and a plurality of column access strobe signals. The controller generally comprising a queue state machine, a plurality of transaction state machines and an arbitor. The queue snare machine may be configured to allocate a plurality of memory commands received by the controller among a plurality transaction state machines. A first of the transaction state machines may be configured to issue a first strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a first of the memory commands. A second of the transaction state machines may be configured to issue a second strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a second of the memory commands.

Abstract: The present invention provides for data flow enhancement in processor architectures having one or more caches by allowing DMA-type transfers to and from these caches. Specific examples allow such direct transfers between a peripheral logic device and the cache memory, or between either the main memory or a special memory and the cache memory. This is done by the processor reserving a portion of cache for the direct transfer, which is then carried out by a DMA-type controller. While this transfer is occurring, the processor is able to carry out other tasks and access the unreserved portion of cache in the normal manner. In the preferred embodiment, the transfer is performed by a cycle stealing technique. Once the transfer is complete, the reserved portion of the cache may be accessed by the processor. The size of the reservable portion may either be fixed or dynamically determined by the operating system based on factors such as task flow management and data transfer rates.

Abstract: A monitor comprising two-way (plug and play) interface. A two-way interface is added in the monitor to achieve the function of mutual communication between a host hardware and monitor. Using the two-way interface, the specification data parameters are transferred to the host hardware, so that the host hardware can easily obtain the specification data parameters. Furthermore, the host hardware can send the parameters to the monitor controller to adjust the image data that meet the specification of the monitor to achieve the function and objective of plug-in of the monitor.

Abstract: The present invention provides a high speed, multi-ported, direct data flow memory architecture that employs memory width and speed greater than system bus width and speed to allow shallow burst depth and reduce other-port latencies, while maintaining multi-port throughput. The inventive system has a data storage device (SDRAM) and a multiplexer connected to the SDRAM. Two or more interfaces or ports are provided with data sourcing controllers respectively connected to the interfaces. A communications bus connects the SDRAM to the data sourcing controllers for facilitating data communications. A FIFO buffer memory is located between the multiplexer and the data sourcing controllers. The need for retries is eliminated and host bus widths are matched to memory data width. Read-ahead algorithms are provided that adapt the larger system bus burst sizes to the smaller memory burst sizes with the ability to cancel unneeded advance requests for data.

Abstract: A semiconductor memory device is provided in which a burst length and/or a column address strobe (CAS) latency may be fixed. The semiconductor memory device, which may be an SDRAM (synchronous dynamic random access memory) device, includes a memory cell array, a burst address generation circuit to generate a burst address and a burst length detection signal, a mode setting register for setting a CAS latency and/or a burst length using an address, a pipeline circuit to delay and output data read from the memory cell array. The semiconductor memory device also includes a latency enable control signal generation circuit to generate a latency enable control signal in response to a read command or signal and the burst length detection signal, and a data output circuit to output data being output from the pipeline circuit in response to the latency enable control signal. Therefore, a circuit configuration is simplified and a test time is reduced, by fixing latency and/or burst length.

Abstract: A system and corresponding method for improving set-top box boots up efficiency while, at the same time, reducing the memory allocation required for set-top box boot-up is disclosed. The boot-up method includes performing a vertical direct memory access transfer of relevant program instructions from a system non-volatile memory to system main memory. The transferred program instructions are then rearranged into consecutive locations within the main memory.

Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: A method and system for an I/O coupling channel to operate in a plurality of modes. The first mode is the new mode providing peer operation with many times more message passing facilities as the old mode. The second mode is used to connect the new channels through a converter to multiple old channels. In this mode, the new channel distributes its message passing resources among the multiple sink ports of the converter that are attached to old channels. The converter keeps no state information and only adjusts line speeds, routs outbound packets, and adds source information to inbound packets. The new channel operating in old compatibility mode gives the illusion to the software of multiple separate channels, one for each converter sink port.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: A method and system of fast program downloading to a target system that includes a printed circuit board. A processor is on the printed circuit board and a target interface having electrical contact pads is embedded on the printed circuit board. The processor includes information signals coupled to the electrical contact pads. The dispatcher includes a dispatcher interface coupled to the target system via the target interface, such that dispatcher interface is coupled to the information signals of the processor.

Abstract: A method and system for enhancing the efficiency of the completion of host-initiated I/O operations within a fiber channel node. The host computer component of the fiber channel node does not allocate the memory buffer for the FCP response frame received by the FC node at the completion of an I/O operation. Instead, the interface controller of the FC node processes FCP response frames in order to determine whether or not an I/O operation successfully completes. In the common case that the I/O operation successfully completes, the interface controller writes the FCP exchange ID corresponding to the I/O operation to a special location in memory which serves to invoke logic functions implemented in an ASIC that de-allocate host memory resources allocated for the I/O operation.

Abstract: The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: When stream data is reproduced through an IEEE-1394 high-speed serial bus from a hard-disk apparatus serving as a source, and is transmitted as is to another hard-disk apparatus through the IEEE-1394 bus and recorded thereinto, if the data is transferred with the use of isochronous communication, entry_type is set to an isochronous track and if the data is transferred with the use of isochronous communication, entry_type is set to an asynchronous track. When the stream data is transmitted, a payload size which indicates the size of the steam data is written into a payload information block in order to obtain a bus channel and a bus bandwidth.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract: A method and system for choosing an optimal PCI adapter burst length is disclosed. The optimal burst length is automatically determined by the adapter configuration feature of AIX software using a cache-line size of a PCI bridge and the latency timer value of the target PCI adapter as inputs. The method also provides for a user to be able to override the software-calculated setting.

Abstract: A memory access method and system which solve the problems of degradation of data transfer efficiency due to memory access waiting period and complexity of memory interface. The system has an address buffer for reading an address in synchronization with a clock, and a burst counter which generates an address of burst length. Further, a ROW address register adjusts timing by latching a ROW address, and similarly a COLUMN address register adjusts timing by latching a COLUMN address. A ROW address decoder decodes the ROW address while a COLUMN address decoder sets the decodes the COLUMN address. The system also includes a mode register which sets the operation mode of the DRAM and a command decoder which interprets and discriminates a command signal. Finally, a controller controls the operation of the overall DRAM, and a memory array holds data for use with a data input/output buffer for data transmission/reception.

Abstract: A data compressor uses data known to exist on a destination computer for compressing an input data stream by encoding portions of the input data stream as references to matching portions of the known data. The known data is preprocessed to better correlate with the input data stream. The preprocessing includes identifying and modifying internal references in the known data, such as relative offsets and addresses of jump and call instructions in executable code or cross references and hyperlinks in documents. The preprocessing is driven by generating a set of data that describes specific individual modifications or alternatively indicates relationships between the known data and the input data stream, such as code or data block motion, from which individual modifications can be deterministically made.

Abstract: The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a read/write transaction, and during the read/write transaction, the request signal and the grant signal are idle. The method comprises the steps of: (a) driving a first ready signal by the PCI bus master; (b) driving a second read signal by the selected device in response to the first ready signal, which initiates the read/write transaction; (c) using the request signal and the grant signal as a data transfer strobe signal during the write and read transaction, respectively, the data transfer strobe signal has a plurality of clocks; and (d) performing the data transfers on rising and falling edges of the clocks of the data transfer strobe signal.

Abstract: A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: A computer system with a multi-master system bus includes a memory controller that changes the burst mode of the including memory system automatically as a function of the selected master. The controller includes a programmable look-up table into which is stored a value B corresponding to a fixed memory burst mode; for each master, a multiplier is stored indicating the multiple of the burst mode that would be optimal for that master. The grant signal used to select the current master is also used to select the multiplier M associated with that master. In response to a read request by the current master, a requested address is forwarded to the memory. Then the controller generates and transmits M−1 addresses spaced B addresses apart every Bth bus cycle. This implements a memory system burst of M*B addresses with no latencies between successive B-address memory bursts. The memory system burst can be aborted if an address in the burst is not confirmed by a subsequent address request by the master.

Abstract: An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc., onto a bus together with a data transfer request without involving use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to the state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.

Abstract: A controller issues a command to an HDD interface to transfer AV data stored in HDDs to a memory. The HDD interface, in compliance with the command, transfers the AV data stored in the HDDs to a memory mapped on a bus. A memory controller reads the AV data out of the bus, and writes the AV data into the memory. The controller outputs the address of the AV data to be outputted to the memory controller. The memory controller reads out the AV data of the designated address, and outputs them to an AV data output interface. And the AV data output interface outputs the AV data. The controller issues a command to the HDD interface memory to record the AV data stored in the memory into the HDDs. The HDD interface, in compliance with the command, reads the data out of a memory mapped on the bus, and stores them in the HDDs. The memory controller reads the AV data out of the memory, and outputs them to the bus.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address.

Abstract: The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

Abstract: An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter.

Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

Abstract: A method and apparatus are for use with a computer system. Write requests to store data in one or more memory locations that are collectively associated with a cache line are received. The first requests are combined to furnish a memory operation. The computer system may include a peripheral device that furnishes a stream of data to be stored in a memory, and the apparatus may include first and second interfaces, a queue and logic. The first interface is adapted to convert a portion of the stream of data into a first request, and the queue is adapted to store the second request. The logic is adapted to determine if the first and second requests target memory locations that are collectively associated with a cache line and based on the determination, selectively combine the first and second requests. The second interface is adapted to furnish a memory operation in response to the combination of the first and second requests. The requests may be, as examples, read requests and/or write requests.

Abstract: An arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware resource. The protocol allows the networking system to determine which subsystem becomes the sender and which becomes the receiver. The protocol is based on a point-to-point communication between two peer subsystems . It is based on an asymmetrical quality such that the first or priority subsystem has a zero latency in accessing the switch while the second subsystem must wait at least one clock cycle before obtaining access to the network system after requesting it and after the end of control by the first subsystem.

Abstract: A method and apparatus for reducing data return latency of a source synchronous data bus by detecting a late strobe and enabling a bypass path. A disclosed apparatus includes a core portion clocked by a core clock and an interface circuit. The interface circuit is coupled to deliver a burst cycle to said core portion. The burst cycle includes a set of sequentially delivered bits that are transmitted with corresponding sequential edges of a transfer clock. Each bit of the burst cycle is delivered either via one of a set of receiving latches coupled in parallel to a data input or via a bypass path that bypasses the set of receiving latches.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: Methods and systems for reducing power consumption in data communications is presented. Portable devices that interface with peripheral devices reduce power consumption by minimizing the time that a communications port is open. Rather than keeping the communications port open for the duration of a program, the communications port is opened at calculated times to allow bursts of data to pass through and closed in response to certain events. This invention also works with normal power cycling methods of portable devices and peripheral devices to produce even further power savings.

Abstract: A statistics reporting process includes a status information process for receiving status information concerning individual data packets. A statistics information process receives statistical information concerning various bus conditions. A unified write process stores the status information and the statistical information on a storage device using a single write procedure.

Abstract: A method, apparatus, and computer implemented instructions for transferring data. A sender sends a plurality of data packets and a receiver receives a plurality of data packets. The data packet within the set of data packets includes a unit of data and an identifier of a location of the unit of data within the packet relative to units of data in other data packets within the plurality of data packets. Data from the units of data in the plurality of data packets are reassembled using indicators in the plurality of data packets.

Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: A method and apparatus multiplexes pins of a PC card (104) to provide communication of two-way, high quality audio data between the PC card and a host computer (102) over a conventional PC card connector. The PC card includes one or more signal drivers (310), each signal driver coupled to a unidirectional signal line conventionally conveying address data from the host computer to the PC card. The signal drivers are configured to provide data signals to the signal line for communication to the host computer in an active mode and to enter a high impedance state in an inactive mode in response to a control signal received at a control input (314).

Abstract: An apparatus is presented for improving the efficiency of data transactions over a computer system data bus. Bus efficiency is improved by providing a bus master with information to adjust the length and width of burst transactions over the bus to/from target devices. If a particular target device is not capable of transacting a full-length, full-width burst over the bus, then the bus master configures a burst to exploit the bursting capabilities of that particular target device. The bus master apparatus includes slave configuration logic that is configured to store a burst transaction capability corresponding to each slave device connected to the bus. The bus master apparatus also has transaction control logic. The transaction control logic is coupled to the slave configuration logic and uses the information to vary burst width and length for a transaction to a specific slave device according to the slave's burst transaction capability.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.