Abstract: A microprocessor circuit having an external memory interface includes a transmission element for the transmission of binary data packets between the microprocessor and the interface. The interface includes a buffer with a determined capacity for storing the transmitted data elements. The circuit also includes a controller capable of computing the capacity of the buffer that is available or unavailable owing to the storage of the data elements and capable of reporting the status of availability of the buffer to receive an additional packet. A method is also provided for the control of the interface of such a circuit. The interface comprises a decoder for decoding format data of a packet. The format data of a packet being contained in the data packet and each format data decoding operation being given to the controller in order to optimize the use of the storage capacity of the buffer and the transmission between the microprocessor and the external memory.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.

Abstract: A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.

Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract: This invention relates to an apparatus for storing and transmitting AV data. A receiving buffer unit for storing AV data temporarily, a transmitting buffer unit for storing temporarily the AV data to be transmitted, and a primary storage unit for storing AV data and a secondary storage units for storing AV data are connected to each other by means of a subnetwork. A server control unit for controlling the respective units is connected to the subnetwork. Since these units are connected by means of the subnetwork, any restriction is not given to spaces for installing the units. The capacities of the primary and secondary storage units and the transmitting buffer unit are selected so that they become larger in order of the secondary storage unit, the primary storage unit and the transmitting buffer unit. Thereby, the storage units and the transmitting buffer unit are controlled in a hierarchical form.

Abstract: A circuit architecture and methodology for providing burst data transfer in high-speed digital circuit applications implements a sequence of overlapped global-pointer signals for generating corresponding sequence of non-overlapped local-pointer signals. One of the global pointer signals starts to be activated per cycle and the pulse width of each global pointer signal is greater than the burst cycle time. A global pointer signal <i> of a sequence (where i is one of the integers <1:n>) is used to generate a corresponding local pointer signal <i> that is reset by detecting a time at which the global pointer signal <i+1> starts to be activated. This allows for generation of reliable non-overlapped local pointer signals, while using overlapped global pointer signals. Each local generated pointer signal is used to accomplish a respective data transfer, e.g., from an individual latch to a single data line.

Abstract: A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed.

Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

Abstract: A data receiver is incorporated in a controller which receives data from memory modules. The data transfer is provided with an S receiver and a D receiver. The S receiver is driven on the basis of first multiphase clocks and receives strobe signals. The D receiver is driven on the basis of outputs from the S receiver, which receives states of the strobe signals at the respective times, and the second multiphase clocks which lag the first multiphase clocks by a predetermined length of time. The D receiver receives data and transfers the same. The S receiver is controlled for burst data transfer such that the S receiver is set in an active state immediately before a strobe signal corresponding to a start item of burst data rises, and is set in an inactive state after a last item of the burst data is received. A multiphase clock generator is provided. The multiphase clock generator generates the first and second multiphase clocks which have predetermined phase differences and are equal in period.

Abstract: A method is presented that may reduce the number of I/O transactions needed to transfer data between a host device and peripheral device over a parallel port. According to one embodiment, only two I/O transactions are needed to transfer a byte of data as opposed to the eight I/O transactions need in the IEEE 1284-1994 standard. During the two I/O transactions (e.g., transferring data from the host device to the peripheral device), the host device places the data on the data signal lines of the parallel port and toggles a signal on one of the control signal lines. In response, the peripheral device reads the data from the parallel port. Additional bytes can be sent by placing the data onto the port and toggling the signal on the same control signal line. Using this method, a data rate of approximately 4 Mega bits per second may be achieved.

Abstract: A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed.

Abstract: A system and method for ordering the transfer of data words within a cache line transfer. The cache memory receives an address from a processor and selects the cache line corresponding to the address. The cache memory then determines an order for transferring cache line data words from the selected cache line based on the likelihood that each data word in the order will be needed by the processor. The data words are then transferred to the processor in the desired order.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: There is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus. The data transfer apparatus includes: a first-in-first-out buffer having a data region for storing one or more words of CPU access data which is accessed by a CPU coupled to the main bus, and a plurality of words of DMA access data which is accessed by a DMA controller coupled to the main bus; and a controller for controlling the first-in-first-out buffer. When the local bus is available, the controller controls the first-in-first-out buffer so as to consecutively transfer the one or more words of CPU access data stored in the data region to the local memory, and to burst transfer the plurality of words of DMA access data stored in the data region to the local memory.

Abstract: The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system.

Abstract: A method and system for increasing the rate of data transfer between a PC-based computer and an IDE/ATA-compliant hard drive is disclosed. Synchronous data transfer is employed in a manner that retains full compatibility with the existing IDE/ATA standard.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: A method and an apparatus for a synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM (syncDRAM) memory for special cases where data is not ready to be transferred. In the event that data is not ready to be transferred between a destination device and the syncDRAM, transfer of data is suspended. Concurrently, at the address from which data was not ready to be transferred, the address is latched by a syncDRAM interface that communicates with the system memory control and the syncDRAM memory. In the event of a read cycle, back-to-back read requests are performed until data can be transferred. In the event of a write request, a mask command is asserted to mask out the data address in the syncDRAM until data is ready to be written to the address, wherein the write request is then reasserted. For both read and write cycles, when data is subsequently ready to be transferred, data transfer is resumed at the latched address.

Abstract: An applications programming interface implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an asyncronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The API also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors. This linked descriptor list can form a circular list of buffers and include a forward pointer to the next buffer in the list and a backward pointer to the previous buffer in the list for each buffer.

Abstract: A master transaction control unit capable of starting an I/O read transaction is arranged in a DVD decoder, and a DVD control driver controls both the DVD decoder and a DVD interface. With this arrangement, motion picture data can be directly transferred from the DVD interface to the DVD decoder without the mediacy of a main memory. Therefore, the same data can be prevented from being output onto a PCI bus several times, and the bus traffic can be reduced. Because of a transfer scheme without the mediacy of the main memory, illegal copying can be prevented.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A cable detection method is provided for detecting the existence of an 80-conductor cable used in connecting a host device to peripheral devices of a computer system. An 80-conductor cable is required for Ultra-ATA to function at data transfer rates of modes 3 or 4. In compliance with ATA/ATAPI standards and requirement, the cable detection method includes the placement of a capacitor on the PDIAG- signal at the host. A device would assert the PDIAG- signal to a low state for a predetermined length of time to discharge the capacitor, release the signal then measure the state of the signal within a window of time, thereby assuring a high state for an 80 conductor cable and a low state for a non-80 conductor cable.

Abstract: A system and method for interfacing between an input/output system, that includes a local computer bus, a processor connected to the local computer bus and an interface to a computer system bus, and a computer system having a main memory is provided. The system includes a memory system with a memory controller that controls access and storage of data. The system may initiate sequential or burst ordered blocks of data over the computer bus from the computer system in anticipation of random access requests for data by the processor. A system and method for interfacing a plurality of processors to a computer system having a system bus and a main memory is also provided.

Abstract: An apparatus is employed for providing for efficient communication between high level and low level processing engines in a disk formatter for formatting a disk, the high-level engine outputting at least one instruction to control disk operations to the low-level engine which processes the instruction. The apparatus includes an instruction queue within the low-level engine. The instruction queue stores the instruction received by the low level processing engine from the high level processing engine, which outputs the instruction to the memory in accordance with a first clock signal generated by the high-level engine. The instruction queue outputs the instruction in accordance with a second clock signal of the low level processing engine which corresponds to a predetermined disk transfer rate. In accordance with another embodiment of the present invention, a method is also employed for providing for efficient communication between high and low level processing engines in a disk formatter for formatting a disk.

Abstract: An improved method and apparatus for performing burst read operations in a nonvolatile memory includes a burst read device coupled to the nonvolatile memory, wherein the burst read device senses a page of data from the nonvolatile memory, latches the page of data, synchronously reads the data one word at a time, and senses a next page of data concurrently with the synchronous reading.

Abstract: A microprocessor and a data processor therefor which have separate data and instruction buses, and wherein a data address and an instruction address are output over a single address bus in a time-shared manner, thereby allowing a data access and an instruction access to be pipelined without the need for separate address buses between the microprocessor and caches holding data and instructions.

Abstract: A data storage system wherein a host computer section having host computer processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a plurality of controllers coupled to a bus. Each one of the controllers is adapted to request a data transfer between the bus and an addressed one of the addressable memories. Each such request is transmitted to the addressed one of the memories in bursts. Each one of the bursts in a request has a tag unique to such request. The bursts from one of the requesting controllers to the one of the addressed memories addressed by such one of the controllers are interleaved with bursts of requests from another one of the requesting controllers to the same or another one of the addressed memories addressed by said another one of the controllers. Each one of the addressable memories has a control logic coupled to the bus for receiving the request from the one of the controllers addressing such one of the addressable memories.

Abstract: An improved burst mode for accessing a storage medium is provided which enables the storage medium to be accessed in any freely specifiable address increments/decrements. The accessing process begins with a bus arbiter receiving a set of request information from a host system specifying a starting address, an incremental/decremental (I/D) value, and a count n. These specified values are stored by the bus arbiter in an address register, an I/D register, and a count register, respectively. Then, the bus arbiter allows the host to access the storage medium beginning with the location having the address indicated by the value stored in the address register which, at this point, is the starting address specified by the host system. Once that location is accessed, the arbiter decrements the value in the count register by one. If the value in the count register is now equal to zero, the process stops.

Abstract: A system is disclosed for improving the efficiency of data transactions by permitting the length of burst transactions to be modified based upon system performance. A bus interface unit monitors the response times of memory devices, and, if WAIT periods are required before the memory device responds, the bus interface unit increases the length of the burst. Preferably, the bus interface unit includes a table of historical response times of various memory ranges, and determines an optimal burst length for each memory range. When a data transaction is made to a particular memory location, the BIU accesses the table and asserts a BURST signal for a sufficient period of time to accomplish the optimal burst length. After the optimal burst length has been reached in the existing memory transaction, the BURST signal is deasserted to end the burst cycle.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: A method and system for transferring data between a processor and a device residing at a non-cacheable address. The method includes the steps of asserting the non-cacheable address onto an address bus, asserting a first signal indicating that the processor has data ready for burst mode transfer between the processor and a device residing at the non-cacheable address, asserting a second signal indicating that the device is ready for the burst mode transfer, and performing a burst mode transfer of a plurality of bytes between the processor and the non-cacheable address. The method of the invention provides both sequential and non-sequential burst transfer modes. The system of the invention provides a processor, a device, bus control logic, and non-cacheable address logic.

Abstract: A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host.

Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values. The memory management unit also includes a descriptor management unit for controlling DMA transfers between the transmit and receive buffers and the system memory.

Abstract: A system for managing burst data transfers from a sending device to the buffer memory of a receiving device and for managing read operations upon the buffer memory after receiving data. In one arrangement, the system includes data management apparatus that is used in a tape storage device. The data management apparatus uses a Start of Burst pointer, a Current Position pointer and a Tape Mechanism pointer to simplify several functions. These functions include the determination of whether to enable a burst from a sending device and the determination of whether to perform a series of read operations upon the buffer memory. In addition, the Start of Burst pointer and the Current Position pointer are used to re-write a burst into the buffer memory if a previously received burst is determined to be invalid.

Abstract: System and method for selectively adapting the burst mode writeback from cache to main memory consistent with the extent of a cache line actually modified by the processor and at the granularity of the bus connecting the cache to main memory. A cache controller speculatively reads a cache line with each address issued by this processor. When the address is related to a read cycle of the processor, the data is forwarded to the processor. When the address is related to a write cycle of the processor, the data read from the cache is compared to the write data from the processor to detect changes at a granularity consist with the size of the system data bus. The cache line stored in the cache upon such writing is marked at the granularity of the system data bus with tag bits to indicate which portions have been modified. Upon deallocation, the tag bits stored in the cache directory identify those portions of the cache lines requiring transmission back to main memory as an aspect of the burst writeback operation.

Abstract: An apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device, such as a bus bridge.

Abstract: A method and apparatus for performing a mid transaction refresh of DRAM and handling a suspend signal from a master. A timer is used to provide a refresh request at predetermined intervals. The refresh request is made to a DRAM state machine. The DRAM state machine performs a DRAM refresh responsive to the refresh request. The refresh is performed by manipulating the RAS and CAS signal while showing a master of the transaction a series of wait states.The suspend signal from the master is received by a DRAM state machine. The DRAM state machine will loop within its then current state as long as the suspend signal is asserted. The RAS, CAS and other control signals are maintained in the states existing when the suspend signal was asserted unless external signals (e.g., a refresh request) force a change in state of the control signals. At least one CAS state machine handles the assertion of CAS.

Abstract: A disc storage apparatus includes at least one disc having at least one recording surface, a disc control unit for receiving a first number of write data, and outputting, through a plurality of lines, a second number of write data selected from the first number of write data, where the first number of write data and the second number of write data are each at least two write data, an encoder circuit coupled to the disc control unit through the plurality of lines for receiving the second number of write data from the disc control unit through the plurality of lines, encoding the second number of write data in parallel to produce coded data, and outputting the coded data for recording on the at least one recording surface, and a microprocessor for designating the second number of write data to be selected from the first number of write data, outputted by the disc control unit through the plurality of lines, and received by the encoder circuit from the disc control unit through the plurality of lines.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first device when it is determined that the first device should release the bus.

Abstract: Data transfer methods and systems are described. The methods and systems permit the transferring of data which is organized into a plurality of records from a readable data storage medium to a host system with reductions in overhead and processing complexity. In a preferred embodiment, the readable data storage medium comprises a tape drive and the records have variable lengths. A data transfer processor is provided and is operably configured for coupling between the host system and the tape drive. A first record length parameter value is defined and describes a length of at least one record which is to be transferred from the tape drive to the host system. A first record having a length corresponding to the first record length parameter value is read from the tape drive and into a temporary record-holding location. Reading of additional records from the tape drive continues until a record is read having a length which is different from the length of the first-defined record length parameter value.

Abstract: System and method transfer information from a primary processor to a co-processor. The primary processor includes an encoder, and the co-processor includes a decoder. To transfer information from the primary processor to the co-processor according to one embodiment of the present invention, the encoder in the primary processor creates an information word. An information word includes a plurality of bits, where each bit corresponds to a different type of information. The encoder sets the state of each bit to indicate whether information corresponding to that bit will be sent. The encoder then sends the information word, followed by the actual information. The decoder decodes the information word to determine what information will be arriving from the co-processor. The decoder identifies the information by the order in which it is received. Each different type of information is pre-assigned to a different register address in the co-processor.

Abstract: In a relaxed bus protocol for transferring bursts of data from a slow device to another device, a predictor generates an advance signal. The advance signal is used to load next data into an output register of the slow device, the next data can then be transferred to the other device. A validator/corrector receiving a ready signal from the second device, the validator/corrector determines that the advance signal is correctly generated by the predictor. Heuristics and a higher level protocol adjust the size and frequency of the bursts of data to achieve optimal performance, and maintain correctness of transmitted data.

Abstract: Burst-mode data transfers between a SCSI host bus adapter and at least one SCSI bus device interface adapter are implemented by hardware. For a first embodiment of the invention, the device interface adapter is equipped with a first, second and third data registers, a comparator, a subtractor, and control logic in the form of an application specific integrated circuit. When a burst-mode transfer is requested, the first register is programmed with a value corresponding to the length of the transfer in bytes, and the second register is programmed with the maximum possible number of bytes in a burst. The comparator then compares the value in stored in the first register with the value stored in the second register and determines which is the smaller. The smaller of the two values is written to the third register. The subtractor then subtracts said third value from said first value to obtain a remainder value. The first value is then replaced with a new first value equal to said remainder value.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: A method and apparatus for transferring data between devices on a bus is described, the apparatus comprising a producer device having an output, and a first data management device having an input and a bus interface. An the output of the producer device is coupled to an input of the data management device. An output of the data management device is coupled to the bus. The preferred method of the present invention includes the steps of causing the data management device to receive data packets from the producer device in single address-data phases, grouping at least two data packets destined for consecutive memory addresses, reorganizing the data within the first-in, first-out memory so that the at least two data packets destined for consecutive memory addresses are consecutive in the first-in, first-out memory, and transferring the data group over the bus using a single arbitration phase, a single address phase,. and a number of data phases corresponding to the number of data phases in said group.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.