Abstract: A sink apparatus receives stream data outputted from a source apparatus connected to a predetermined network. When the source apparatus or an other apparatus connected to the network transmits a command to configure a data input section of the sink apparatus to input data outputted from the source apparatus, data are prepared to indicate that a configuration of the data input section is at least temporarily disabled as a response from the sink apparatus. When the apparatus that transmitted the command receives the data indicating that the configuration is at least temporarily disabled corresponding processing may be executed. When stream data are transmitted through a network it can be easily determined by an other apparatus on the network whether the sink apparatus is ready to input data.

Abstract: A mechanism for servicing connections by disassociating processing resources from idle connections and monitoring the idle connections for activity is described. In one embodiment, a connection that is being serviced by a processing resource is disassociated from the processing resource when the connection is idle. The connection is handed to a poll manager for placement into one of several poll subsets. A poll thread associated with each poll subset is sends the poll subsets and poll requests to a poll adapter. The poll adapter uses the features of the operating system to monitor the connection for activity, such as by polling the connections to identify any pending events. The approach may be implemented on different operating systems by changing the poll adapter. The poll manager passes active connections to a work queue to wait for servicing. The present invention avoids wasting resources on connections that are idle.

Abstract: A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a hardware-based semaphore (status bit) to allow either the SMI or the driver to claim ownership of the Bus host controller for an arbitrary period of time. While either the SMI or the driver may own the status bit, the other party must poll the bit until ownership is achieved. For the SMI, this involves scheduling a periodic SMI interrupt. The driver performs self arbitration of claiming the status bit to provide the periodic SMI interrupt the opportunity to claim the bit. The mechanism allows the SMI access to the Bus host controller in a “timely” manner, while minimizing impact to driver access to the Bus host controller, which could impact driver Bus transaction throughput.

Abstract: Methods, systems, and articles of manufacture for communicating with an I/O processor (IOP) are provided. Polling of message queue pointers is utilized to detect the occurrence of certain message queue related events, rather than rely on interrupts generated by the IOP. The polling may decrease the disruptive effects of IOP generated interrupts. In an effort to minimize the latency associated with detecting IOP related events, the polling may be initiated frequently by an operating system task dispatcher. In an effort to minimize context switches, the task dispatcher may schedule the processing of upstream messages detected while polling to coincide with naturally occurring task swaps.

Abstract: A mobile station establishes a schedule by which data is exchanged with an access point. The schedule allows the mobile station to use a low power mode at times outside of the scheduled service periods. However, the mobile station may occasionally need to retrieve additional data from the access point, or transmit additional data to the access point, and so initiates an unscheduled service period to do so.

Abstract: An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.

Abstract: A head unit outputs a control bus command in response to an input operation by a user. A conversion unit converts the control bus command into a USB data frame and outputs the USB data frame to a notebook personal computer. Based on the USB data frame, and notebook personal computer reads music data stored in a hard disk drive, and outputs the music data to the head unit via the conversion unit. If the music data is compressed, the music data is decoded at the notebook personal computer. Thus, a dedicated decoding LSI need not be provided in the head unit.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: An interface implements a file system for supporting Java record and resource management between an operating system using a first programming language other than Java and a suite of Java applications. The interface provides a method for maintaining any number of files to be open in a manner transparent to the Java applications. Location information of a file is put in storage allocated for usage by Java code when a maximum number of open files is exceeded. A table is used to translate between file names of differing length and to identify directories in a manner to provide a hierarchical file system. An identifier is associated with a shortened Java file name in the table to quickly identify an operating system file with a shortened file name.

Abstract: A hand-held communication control device which, when coupled to a process control system communication bus, controls communication occurring on the bus using a communication schedule that dictates when each of the devices coupled to the bus will be permitted to communicate on the bus. The hand-held communication control device further uses a probing algorithm to detect devices, including other communication control devices, that are coupled to the bus. The probing algorithm causes the hand-held communication control device to select an address from one of a set of three address lists to which a probe node message is then transmitted to detect the presence of a device at that address. One of the address lists is reserved for communication control devices and uses only a limited number of maximum possible addresses.

Abstract: A computer system comprises a host computer coupled to a wireless module via a digital interface. The wireless module permits the computer system to communicate with a wireless network. The host computer repeatedly polls the wireless module to determine whether it has received any incoming data from the wireless network, but preferably does not poll the wireless module all of the time. Periodic cessation of polling advantageously helps to extend battery life in the case of a host computer that operates off battery power. This concept, however, can be applied and is useful in the context of desktop electronic systems that operate from AC power.

Abstract: Transmission/reception of each request is carried out through one and the same port. When requests are concentrated on one port, the port has to process all the requests. The processing load on the port increases correspondingly. A table in which request processing and its control information are recorded and a table in which ports that can be requested are recorded are prepared in a shared area inside a disk subsystem. Processing is requested with reference to those tables. The load on the port on which requests are concentrated is distributed, and the throughput to request sources is improved.

Abstract: The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module including a single chip multi-layer PHY having one or more shadow registers. The transceiver module includes one or more storage modules adapted to store transceiver module local data. The shadow registers are adapted to facilitate collection of the local data from the storage modules and communicate the collected data to another portion of the transceiver module and/or to the upper lever system using at least one interface communicating with the shadow register.

Abstract: A process and system is provided for setting up a polling interval for a device that sends a not acknowledged (NAK) signal. The process determines the number of times the device sends a NAK signal before a successful data transfer; and also determines a statistical parameter based on the number of times the NAK signal is received before a successful data transfer; and sets a polling interval for the device based on the statistical parameter. The statistical parameter may be an average, median, maximum or minimum number of times the NAK signal is received before successful data transfer. A polling interval may also be set based upon the number times the NAK signal is received, wherein the polling interval increases with the number of NAK signals. The polling interval may double after every NAK signal.

Abstract: A polling method, apparatus, and system to detect the attachment and detachment of Universal Serial Bus devices in a wireless system. A hub provides a wired connection to the host and wireless attachment points for its devices. The host periodically queries the hub for changes in the hub's status register by sending a polling message through each of its wireless ports, and awaits a response. A peripheral device that wishes to attach to the system responds by sending its unique peripheral address. If a device currently occupies the port, the hub sends out the device's unique address in the polling message. If the device is still present, it responds by sending its unique peripheral address. If a response is not received after multiple retries, the device is considered detached. The hub thus determines the status of the ports and updates the status register, which is queried by the host.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: An apparatus, method and program product for controlling the transfer of data in a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by the processor for storing data, and one or more I/O devices for sending data to or receiving data from said main storage. The apparatus includes a vector mechanism operable to register I/O requests by the devices to send or receive data from said main storage. A dispatcher is included which is operable to poll the vector mechanism to determine if there is an outstanding I/O request. An override bit has a first condition when an immediate interrupt is to be sent to the processor for handling an I/O request from the I/O device(s), and a second condition when the dispatcher is to poll the vector mechanism to determine if there is an outstanding I/O request. The override bit is set to its first condition or reset to its second condition by the processor.

Abstract: A method and system for executing one or more remote procedure calls. In one embodiment, a method comprises the step of a processing unit issuing a plurality of commands to a corresponding DMA controller. One or more commands of the plurality of commands issued by the processing unit are to copy attached processing unit instructions associated with one or more Attached Processing Unit's (APU's) and data associated with the attached processing unit instructions from the shared memory to one or more APU's. The attached processing unit instructions may include instructions that enable the associated one or more APU's to perform one or more particular operations on the data. The method further comprises the DMA controller issuing an indication to the one or more APU's to perform the one or more operations on the data associated with the attached processing unit instructions.

Abstract: Disclosed is device and method for improved burst communication on a USB bus. In one embodiment, a USB Ethernet adapter device uses the USB Interrupt Channel to send a message to an Ethernet class driver, via the host USB stack, that the Ethernet adapter device has data to transmit on the USB. The interrupt message preferably includes the size of the data packet to be transmitted or the number of packets to send. The class driver responds by instructing the USB stack to configure a new Transfer Descriptor having buffer pointers of sufficient size for the data packet. The USB Host Controller then processes the Transfer Descriptor, thereby inviting the Ethernet adapter device to transmit its data and responsively storing the data in the predetermined buffer.

Abstract: A TAP linking module provides for control and access of plural TAPs on an IC through one set of JTAG signal pins. The IC includes plural circuit modules, each with its own TAP, and boundary scan registers connected to an additional TAP. All the TAPs and the linking module have their TDI, TMS and TCK inputs connected to one set of input pins on the integrated circuit. The TDO outputs of all the TAPs and linking module are connected to the TDO pin through a multiplexer. A special instruction scanned into an enabled TAP produces a select signal to the linking module. This disables the enabled TAP and causes the linking module to be the scan path between the TDI and TDO pins. Selection data scanned into the linking module disables the linking module and enables a TAP to be connected between the TDI and TDO pins.

Abstract: An apparatus, method and program product for use with a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by said processor for storing data, one or more I/O devices for sending data to or receiving data from said main storage in the I/O operation, and a summary register for registering I/O requests by any one or more of said devices. The apparatus includes a dispatcher for polling said summary register to determine if an I/O request is outstanding. A program in the dispatcher calculates a delay value responsive to the workload of the processor in handling I/O requests. An adapter between the device and the processor drives an interrupt of the processor if the calculated time delay is exceeded between completing I/O requests.

Abstract: Techniques are disclosed for efficiently updating rendered content (such as content of a Web page) using a “slow-loading” content element, such as a slow-loading image. A reference is embedded within the markup language notation for the content to be rendered, where this reference identifies the source of the slow-loading content element. Delivery of the slow-loading content therefore begins automatically, when the content is rendered. Event handling attributes are specified with the reference, where values of these attributes identify client-side logic to be invoked when the associated event occurs. If the server determines that the rendered content, or some portion thereof, should be asynchronously updated, it abruptly terminates delivery of the slow-loading content. This termination triggers an event handler, which operates to automatically request reloading of the content.

Abstract: A control facility that allows a non-programmer to use and manipulate replicated data without disrupting replication of the data itself. The control facility can be used and customized for a variety of software applications and storage platforms to perform off-host processing of the replicated data. In response to a single user command during replication of data from a primary node to a secondary node, a control message is obtained from the primary node and a control command associated with the control message is automatically executed on the secondary node. A portion of the data is diverted from first storage at the secondary node to second storage in response to obtaining the control message, the portion of the data is copied to the first storage in response to completing the execution of the control command, and the data is automatically re-directed to the first storage in response to completing the copying.

Abstract: An apparatus, method and program product for sending data to or receiving data from one or more I/O devices in an I/O operation with a main storage controlled by a processor in a data processing system. The apparatus includes a time-of-day (TOD) register for containing a TOD value, a clock for containing a current TOD value, and a summary register having a first condition when any one of said devices requests an I/O operation and a second condition when no devices have an outstanding I/O request, each device having an outstanding I/O request sets the summary register to its first condition only when the summary register is in its second condition, and further places the current TOD value in the TOD register. A checking program determines if a specified time delay has been exceeded between the value in said TOD register and the current TOD for each requested I/O operation. The checking program drives an interrupt to the processor when the specified time delay has been exceeded.

Abstract: A method and apparatus for allowing memory, cache and/or a processor to remain powered down while repetitive transactions are carried out on an I/O bus and actions are taken in response to feedback received from I/O devices coupled to the I/O bus.

Abstract: An apparatus and method for communicating between a controller and a message processing device over a universal serial bus (USB). The apparatus may comprise an interface having a bulk data-out endpoint for receiving a data-out packet from the controller that requests data from the device. The interface also has an interrupt-in endpoint for receiving interrupt-in packets from the controller requesting a status of the requested data from the device. When the requested data becomes available, logic at the interface transmits the status from the interrupt-in endpoint to the controller. In addition, when USB bandwidth so permits, logic at the interface also transmits the data with the status from the interrupt-in endpoint to the controller. Alternatively, where the data is not transmitted with the status, upon receiving the status the controller queries the interface at a bulk data-in endpoint for the requested data.

Abstract: Control signals of an I/O or peripheral bus are sensed during cycles of the bus and information describing bus phases of the signals is derived by sensing the control signals and is stored in a register. During a sampling time period, a processor reads the bus phase information from the register and computes bus activity information by using the bus phase information. The computed bus information is continuously updated and displayed to reflect actual communication activity on the bus occurring substantially in real-time.

Abstract: An apparatus and method for efficient input/output processing without the use of interrupts is described. The apparatus includes a plurality of descriptors where each descriptor includes a completion indicator and data associated with an input/output request. The plurality of descriptors includes a head descriptor and a tail descriptor. The apparatus further include a plurality of address holders associated with an input/output processor, and each the plurality of address holders is uniquely affiliated with one of the plurality of descriptors. The apparatus further include a polling mechanism for evaluating the completion indicator of the head descriptor and a completion processor for interfacing with the head descriptor. Finally, the apparatus includes connectors between the tail descriptor and address holder and between the input/output processor and the head descriptor.

Abstract: In a system in which a polling devices polls one or more devices, a method and apparatus are described that allows the polling device to adjust the polling rate of all polled devices with which it is communicating based upon the activity level of each polled device. This dynamic polling scheme permits a much more efficient allocation of bandwidth than is available with static or fixed polling schemes.

Abstract: A system and method for GPIB autopolling of GPIB devices. A computer is coupled to one or more GPIB instruments through a GPIB to analyze, measure or control a process or unit under test. The computer includes a GPIB controller which monitors activity of the GPIB devices on the bus and produces heuristic information regarding the past behavior of the GPIB devices, such as a queue of one or more GPIB device IDs sorted by how recently each device was accessed. The heuristic information produced is stored on a memory and/or hard drive of the computer. A service request (SRQ) line assertion triggered by one or more GPIB devices may be received. The GPIB controller performs autopolling on the GPIB devices as ordered in the queue to determine which of the devices asserted the SRQ. If no queued devices asserted, the remainder of the devices are polled in arbitrary order.

Abstract: The present invention provides a method and apparatus for adjusting an interval of polling a peripheral device (e.g., printer) for status information, as based on the presence of a predetermined condition. In one embodiment of the present invention, short polling intervals are used to poll a peripheral device when a station (e.g., computer system) is not receiving adequate and/or reliable notification of interrupts/alerts that occur at the peripheral device. Long polling intervals are used to poll the peripheral device when the station is receiving adequate and/or reliable notification of interrupts that occur at the peripheral device.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: High-speed data streams are exchanged between two digital computing devices one or both of which lacks DMA. Data transfers are performed by the devices using High-Level Datalink Control (HDLC) frames. An initiating device indicates that it wishes to exchange data with the other device by sending an HDLC frame with data stream indentification and other information. The initial HDLC-frame is sufficiently short that at least an essential portion of the frame can be stored in a receive buffer of the interface circuitry. Although the receiving device may not receive the entire HDLC frame correctly because of the possibility of an overrun condition, enough information is preserved in the interface circuitry to complete the transaction. The responding device then proceeds to read or write data at high speed using a series of exchanges with the initiating device.

Abstract: A system and method of decoupling timing in a high speed bus system. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master to believe its communications with the slave device are occurring under the first protocol.

Abstract: The present invention is a system and method that facilitates extendible identification of various peripheral devices coupled to a hand held computer. In one embodiment of a present invention peripheral device identification system and method, an initial pulse of an interrupt signal received by the hand held computer initiates an interrupt routine that continues to monitor the interrupt signal for additional pulses within a predetermined time. A hand held computer peripheral device identification system and method of the present invention correlates the number of received pulses with the type of peripheral device coupled to the serial port. In one exemplary implementation of the present invention, a hand held computer peripheral device identification detection system and method utilizes a hash table to map the number of pulses to a type of peripheral device.

Abstract: A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.

Abstract: A method for the identification of electronic cards within an investigation zone includes encoding an identification number on M bits distributed into P blocks of Q bits assigned to each electronic card. Reconstruction of the block-by-block identification numbers is performed according to a tree-like iterative algorithm. In this iterative algorithm, each iteration includes a step for transmitting an interrogation message intended for certain electronic cards. Each iteration also includes a step for transmitting, by each of the electronic cards, a response message having a service bit in a narrow time window whose positioning in a sequence of 2Q successive identical windows indicates the value of an as yet unidentified block of bits of its identification number.

Abstract: A method and apparatus for adjusting an interval of polling a peripheral device (e.g., a printer) based on a change in the working status of the peripheral device. In one embodiment of the present invention, if the peripheral device being monitored is in the process of performing a job or has experienced an interrupt/alert, the length of the polling intervals may be shortened to provide increased monitoring of the peripheral device. If the peripheral device is idle, the length of the polling intervals may be longer to provide less monitoring of the peripheral device.

Abstract: An input/output (I/O) controller in an I/O system processes I/O requests from a host computer to a plurality of I/O devices. The I/O controller generates an interrupt to the host computer and reports a plurality of completed I/O requests from the I/O devices when at least one condition of the I/O system is met. A first condition of the I/O system comprises a predetermined ratio between the total number of unreported I/O completions by the I/O devices and the total number of remaining I/O requests from the host computer. A second condition comprises the expiration of a timer, which starts when the number of remaining I/O requests left to process for any individual I/O device reaches a predetermined minimum limit.

Abstract: A method and apparatus for facilitating AC-link communications between a controller and a slow peripheral of a codec is disclosed. In one embodiment, the GPIO_INT bit (i.e. bit 0 in slot 12 in the AC-link's SDATA_IN line) is utilized as an interrupt flag to indicate when data requested by the controller from the slow peripheral is returned and is available to be read by the controller. The GPIO_INT bit can also be used to indicate when a write into the slow peripheral is completed. In this embodiment, a “peripheral ready bit” or a “peripheral ready signal” originated from the slow peripheral is used to set the GPIO_INT bit. Another embodiment is directed to controllers which ignore the GPIO_INT bit as a source of interrupt. To accommodate these controllers, one of the GPIO bits is used to send the value of the “peripheral ready bit” to the controller.

Abstract: The present invention is a system and method that minimizes discarding of a pending read transaction in a peripheral component interconnect (PCI) bus architecture due to an arrival of a write request while maintaining appropriate transaction ordering. The read/write optimizing system and method of the present invention optimizes read performance by continuing to process a pending read transaction under appropriate conditions while partially performing the write request and inhibiting its completion. In one embodiment of the read/write optimizing system and method of the present invention, a write transaction is inhibited by tracking or storing an inhibited write transaction target address if a pending read transaction address is not within a range of an inhibited write transaction address. For example, a target address associated with an inhibited write transaction is temporarily latched in a write address register until a pending read transaction is completed or terminated.

Abstract: A data carrier (1) having an electrical circuit (2) includes receiving means (6) adapted to supply input data (ID) including option control commands (O1, O2, O3, O4), and includes option control command processing means (11) adapted to process at least one pair of mutually complementary option control commands (O1, O2), (O3, O4) and to generate at least one pair of mutually complementary port control commands (GA, GB), (GC, GD), and further includes port means (12) to which the port control commands (GA, GB, GC, GD) can be applied and which are adapted to be controlled reversibly as regards their port states in dependence on the two mutually complementary port control commands (GA, GB), (GC, GD), and further includes at least one option means (13, 14, 15, 16) which is optionally accessible with the aid of the port means (12).

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A method of configuring peer devices without the unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after a predetermined duration when the intended device fails to respond to the configuration cycle. A bit corresponding to the particular device is set in a scorecard register. The compatibility bridge responds to the configuration cycle after the watchdog time-out period.

Abstract: In a write process of compressed data #1, data transfer for one sector from a CPU to an HDD, and a local write for one sector by the HDD repeat themselves for 256 sectors. During the write process period, the system BIOS compresses data of the next data block by utilizing the period in which a local write is made by the HDD. That is, upon completion of data transfer for one sector, the system BIOS waits for completion of the local write for one sector by the HDD, and then transfers the next data for one sector. During that local write completion wait period, the system BIOS compresses the next data.

Abstract: A method for determining a position of a joystick in data communication with a processor and having an initial state that includes steps of varying the initial state in response to a signal from the processor; returning the joystick to the initial state after a duration of time, with the duration of time being dependent upon the position amongst a plurality of positions. A plurality of poll operations of the joystick are executed to sense the returning step. Each of the polling operations results in a data signal being transferred from the joystick indicating the state of the same, with consecutive poll operations being separated by a predetermined segment of time, defining a first interval and consecutive data signals operations being separated by a time period, defining a second interval. The second interval is increased to be greater than the first interval, the duration of time is measured by determining a number of data signals received by the processor between the varying step and the returning step.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: A method without the Host systems intervention to automatically select Devices on an ATA Cable and determine if they require to be serviced. Upon detection to the indicate to the Host that service is required. This method greatly reduces the Host system's processor overhead associated with Polling the Devices for status.

Abstract: A method and apparatus for detecting the link status of a network device in a computer system. An automatic link status detection mechanism allows a system to operate intelligently in a normal operation mode if the link status is on, or a suspend mode if the link state is down. The mechanism includes an auto link poll controller and a polling cycle generator for generating a sequence of polling cycles to query the link status of the network device. A media independent interface management frame having a preamble field is generated in a polling cycle. Because of the improved preamble field, it is to assure that an exact polling cycle is complete when a polling cycle is issued to the physical layer of the network device.