Abstract: A robot controller includes a memory unit that stores an address table that contains a plurality of start addresses for additional system software files each used to add a function to system software for the robot controller, and a function addition portion that adds a function to the system software based on an additional function file stored in an external memory device. The function addition portion uses an index value with respect to the address table to acquire one of the start addresses for the additional system software files. Programs contained in the system software and the additional system software files each use a position-independent code based on relative addressing.

Abstract: An apparatus, comprising a system management bus configured to communicate with a USB PDC, and a processor coupled to the system management bus and configured to send a power delivery configuration to the PDC, wherein the power delivery configuration comprises voltage and current settings, and receive a power delivery status from the PDC. Also disclosed is an apparatus comprising a power bus interface configured to communicate with a USB port partner, a system management bus interface configured to communicate with a host, and a processor coupled to the power bus interface and the system management bus interface, wherein the processor is configured to receive, via the system management bus interface, a power delivery configuration from the host, generate a power capability message based on the power delivery configuration, and send, via the power bus interface, the power capability message to the USB port partner.

Abstract: A method of testing a data storage system includes maintaining libraries of test routines, a first library including a set of normal-functional tests each operable to test corresponding normal functionality of the data storage system, a second library including a set of fault inserters each being independently operable to induce a corresponding fault condition into the data storage system. Normal-functional tests are executed concurrently with one or more of the fault inserters to cause the normal-functional tests to encounter the corresponding fault conditions during execution and thereby test a response of the normal functionality of the data storage system to the occurrence of the fault conditions.

Abstract: A voltage regulation system has a voltage regulator, a current-limiting circuit, and a feed-forward circuit. The voltage regulator regulates an output voltage to a desired voltage level. The current-limiting circuit controls an output current of the voltage regulator to a desired current level. The feed-forward circuit, which has a fast response time, controls an inrush current in the output current caused by a decrease in an output voltage.

Abstract: A sorter receives a list of elements to be sorted. The elements are supplied to a communication bus. A plurality of processing modules are coupled to the communication bus and examine each list element supplied on the bus to see if the list element has a value that is within a range of values processed by the list element. The range of values of the list are subdivided to ranges allocated to the processing modules. When a processing modules determines an element in the bus is within its range, it stores the value and sorts the value in storage dedicated to storing a sorted list of values with the allocated range.

Abstract: Examples of the disclosure provide a datacenter configured for operation while submerged in water. The datacenter includes one or more physically separable modules. The datacenter also includes an intrusion detection system that has one or more intrusion detection modules.

Abstract: According to one embodiment, a code optimizer is configured to receive first code having a program loop implemented with scalar instructions to store values of a first array to a second array based on values of a third array and to generate second code representing the program loop using at least one vector instruction. The second code include a shuffle instruction to shuffle elements of the first array based on the third array using a shuffle table in a vector manner and a store instruction to store the shuffled elements of the first array in the second array.

Abstract: The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: Methods and apparatus are provided for allowing a component such as a processor on a programmable chip efficient access to properly transformed data an embedded memory. Circuitry is provided with the read data port associated with an embedded memory. The circuitry can be used to perform both static bit width configuration of an embedded memory as well as perform data transformation or data alignment of embedded memory read data. The circuitry can allow efficient data transformations including selection of half words and bytes as well as perform sign extension and zero extension of memory read data.

Abstract: A device and a method for testing a DMA controller. The device includes: (i) a DMA controller that includes a first data transfer path and a second data transfer path, wherein the first data transfer path and the second data transfer path are mutually independent; (ii) a test unit, connected to the first and second data transfer paths, that is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: Disclosed is a transmission apparatus in which a plurality of elements implement virtually one apparatus. Each element includes at least one main signal package and a monitor control package that is connected to the main signal package via an intra-apparatus bus 40 and connected to another monitor control package via an inter-apparatus communication bus. The monitor control package in one element, on occurrence of a malfunction in the main signal package being monitored, collects an alert from the main signal package being monitored, and transmits an alert masking control signal, using the inter-apparatus bus, to the monitor control package of another element to which belong the main signal package of a masking target. The main signal package of the masking target suppresses alerting of a second-order malfunction in case of detection of the second-order malfunction on receipt of the alert masking control signal.

Abstract: A data communication apparatus 1 has a processing section (CPU) 10 that executes at least a part of communication processing of a communication controller 2 and that executes processing other than the communication processing, wherein The data communication apparatus 1 has an interrupt request blocking section 20 that blocks, during execution of a processing relevant to information exchange concerning a communication condition for the communication controller 2 to carry out a communication processing, an interrupt request to the processing section 10 with priority over the processing relevant to information exchange. With this arrangement, even when additional operation is carried out to execute an interrupt processing during execution of a processing concerning a communication condition such as a modulation system of a modem and a communication speed, the processing can be executed securely and a stable connection of a communication line can be maintained.

Abstract: A shadow hardware system and method is provided. The shadow hardware system provides an interface between an access device and shadowed devices. Shadowed devices are devices that the shadow hardware system provides an interface to the access device although the shadowed device may not actually be present or available to the access device, such as implementing a disk drive as flash memory. The access device, such as a host processor, issues requests to a disk drive and the shadow hardware system converts the requests to requests suitable for the flash memory. A shadow remapper redirects the requests to shadow registers and notifies the shadow controller of the pending request. The shadow controller accesses the shadow registers and modifies the registers (if necessary) before forwarding the registers to the actual hardware devices. Any suitable device may be shadowed.

Abstract: A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.

Abstract: Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.

Abstract: An image processing apparatus includes a signal input mechanism, a signal output mechanism and a control device. The control device controls a writing of data received from the signal input mechanism and outputs the data to a plurality of digital signal processors for image processing through the signal output mechanism. The control device includes a decision mechanism and a write administration mechanism. The decision mechanism is configured to decide data to be written to the plurality of digital signal processors. The write administration mechanism is configured to administrate writing operations of the data decided by the decision mechanism to be written relative to the plurality of digital signal processors.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array.

Abstract: High-speed data streams are exchanged between two digital computing devices one or both of which lacks DMA. Data transfers are performed by the devices using High-Level Datalink Control (HDLC) frames. An initiating device indicates that it wishes to exchange data with the other device by sending an HDLC frame with data stream indentification and other information. The initial HDLC frame is sufficiently short that at least an essential portion of the frame can be stored in a receive buffer of the interface circuitry. Although the receiving device may not receive the entire HDLC frame correctly because of the possibility of an overrun condition, enough information is preserved in the interface circuitry to complete the transaction. The responding device then proceeds to read or write data at high speed using a series of exchanges with the initiating device.

Abstract: An extension to the Universal Serial Bus (USB) protocol that utilizes reserved bits in the OHCI Endpoint Descriptors to signal which root hub port(s) should transmit the data. Typically, all ports transmit (broadcast) data. The present invention encodes transmission information that can be used by the hardware to effectively control which port(s) need to be tri-stated. However, by setting, the “on” bits for all the ports, the present invention retains standard USB functionality. Also provided is a method to increase the bandwidth of low speed devices connected to the USB bus by increasing the data payload for such devices.

Abstract: Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.

Abstract: Enumerating an expanded bus system in a system. The expanded bus system may include a first bus, a bridge coupled to the first bus, and a second bus coupled to the bridge, where the second bus includes one or more downstream bus ports. One or more of the downstream bus ports may initially be masked. An initial bus enumeration may be performed during system boot, which may not include enumerating the masked bus ports. After the initial bus enumeration, the masked bus ports may be unmasked. An operating system may re-enumerate the bus system, which may include enumerating the no-longer-masked bus ports.

Abstract: Embodiments of the present invention may provide for architectural and compiler approaches to optimizing processors by packing instructions into instruction register files. The approaches may include providing at least one instruction register file, identifying a plurality of frequently-used instructions, and storing at least a portion of the identified frequently-used instructions in the instruction register file. The approaches may further include specifying a first identifier for identifying each of instructions stored within the instruction register file, and retrieving at least one packed instruction from an instruction cache, wherein each packed instruction includes at least one first identifier. The packed instructions may be tightly packed or loosely packed in accordance with embodiments of the present invention. Packed instructions may also be executed alongside traditional non-packed instructions.

Abstract: In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus.

Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.

Abstract: Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.

Abstract: A signal processing device includes a start time obtaining part that obtains a start time when a predetermined process is started in response to an interrupt request associated with a valid edge of a pulse input signal, an edge occurrence time obtaining part that obtains a time of occurrence of the valid edge of the pulse input signal after the start time of the predetermined process is obtained, and a processing part that selectively performs a process based on a time relationship between the start time of the predetermined process and the time of occurrence of the valid edge.

Abstract: Provided is an address validating data structure used for validating addresses. A data structure comprising a plurality of arrays is buffered. Each array includes a plurality of words, wherein one word in each array indicates address words in the array having valid addresses. At least one mask word provides mask information for at least one address word having a valid address, wherein the mask information for one address word indicates bits in the address word. The data structure is used to validate an address received from a transmitting node.

Abstract: One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.

Abstract: Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.

Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.

Abstract: A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

Abstract: An apparatus and method for dynamic suppression of spurious interrupts in a computer system. More specifically, there is provided a method that comprises providing a look-up table comprising source IDs and corresponding time delays for each of a plurality of interrupt lines, monitoring each of the plurality of interrupt lines, and updating the time delays in the look-up table based on the monitoring of the interrupt lines, and a system for implementing the method.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-OR information. In a primary searching operation, the associative memory (1) is supplied with the search data (12) to provide the matched data logical-OR information on matched data logical-OR lines. Then, the associative memory (1) carries out a secondary searching operation supplied as search data with the matched data logical-OR information obtained by all of storage data coincident upon the primary searching operation. Only a match line (5) coincident with the matched data logical-OR information is selected as the secondary search result. The associative memory is used in a network router to calculate an optimum memory address signal (403) by encoding the selected match line (5).

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O processor performs I/O forcing utilizing the I/O force data stored in the cache memory. The invention further provides for the processor to notify the I/O processor in the event that I/O force data is altered during control program execution. The invention further provides for the I/O processor to refresh the cache memory (e.g., via a blocked write) after receipt of alteration of the I/O force data from the processor.

Abstract: A switch is presented including a host input/output (I/O) port adapted for coupling to a controller, multiple device I/O ports each adapted for coupling to at least one device, and logic coupled between the host I/O port and the device I/O ports configured to selectively form a communication channel between the host I/O port and one of the device I/O ports. The switch may operate in a connected mode and a disconnected mode. When in the switch is in the disconnected mode, the logic may not form a communication channel between the host I/O port and any of the device I/O ports. In an ATA embodiment, the switch may comply with an AT attachment (ATA) standard, and thus be an ATA switch. The host I/O port may be adapted for coupling to an ATA controller, the device I/O ports may be adapted for coupling to at least one ATA device, and the logic may selectively form an ATA communication channel between the host I/O port and one of the device I/O ports.

Abstract: There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asserted, a timer portion 201 is activated. When the timer portion 201 detects that the wait signal is kept asserted for more than a predetermined period of time, it asserts a wait mask signal. Upon assertion of the wait mask signal, a mask portion 202 masks the wait signal from the PC card so that the wait signal to the CPU is negated even when the wait signal is kept asserted. Further, when the timer portion 201 asserts the wait mask signal, an interrupt control block/card status register 210 asserts an interrupt signal to the CPU.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem.

Abstract: A method to enable unique identification of serial devices having a common bus for communication with a bus master includes the step of serially clocking a mask value through a plurality of serial devices until each serial device stores a corresponding portion of the mask value. Each serial device responds to a subsequent command only if enabled by the corresponding portion of the mask value. Another method includes the step of initializing a plurality of serial devices to one of a first mode and a second mode. If the plurality of devices are in the second mode, a mask value is serially clocked through the plurality of serial devices until each serial device stores a corresponding portion of the mask value. When in the first mode every serial device responds to a subsequent command. When in the second mode, only serial devices enabled by the corresponding portion of the mask value respond to the command. An apparatus includes a plurality of serial devices coupled to a bus master by a bus.

Abstract: A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.