Abstract: A method for managing a chassis includes obtaining, by an enclosure controller of the chassis, a power supply application to the chassis using a power supply interface, wherein the power supply interface is operatively connected to a plurality of power supplies, initiating a boot-up of a kernel of the chassis in response to the power supply application, initiating a parallel boot task using the power supply management temporary namespace to identify a power supply of the plurality of power supplies, initiating a mounting of a boot-up file system, and initiating a user space boot-up using the boot-up file system, wherein the user space boot-up and the parallel boot task are initiated in parallel.

Abstract: Example storage systems, storage devices, and methods provide management of idle time compute tasks from host systems. Storage devices may receive host storage commands for reading and writing host data and host compute commands for executing host compute tasks. Some host compute commands may include a scheduling tag. The storage device may operate in a storage processing state and an idle state and may selectively execute delayed host compute tasks during the idle state.

Abstract: An adaptive hybrid polling technique combines an interrupt mode with a polling mode, and is based on outstanding input/output (OIO) determination to improve I/O performance and to save processor cycles. The OIO includes two types of I/O commands: (1) I/O commands submitted to storage devices for processing, and (2) I/O commands completed by the storage devices but not yet acknowledged by host software. The adaptive hybrid polling technique involves two phases to determine when to poll based on current OIO commands. In the first phase, a determination is made whether there is an adequate number of the first type of OIO commands to prepare for polling. In the second phase, a determination is made whether there is an adequate number of the second type of OIS commands to activate polling.

Abstract: A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

Abstract: A serial interrupt method includes receiving a blank serial interrupt request signal (SerIRQ) and a level signal of a peripheral, based on the blank SerIRQ, generating an indication SerIRQ including an indication interrupt bit (IRQ_n) according to the level signal, and sending the instruction SerIRQ to a processor. The indication IRQ_n identifies the peripheral based on a binary code represented by a first level and a second level.

Abstract: A programmable circuit that is configured to control a target memory is used to detect a number and types of a plurality of target events in real time. In the event a trigger condition associated with a triggered preset state in a plurality of preset states is satisfied by the detected number and types of the plurality of target events, an action execution circuit module corresponding to the triggered preset state is selected to run, where the trigger condition is based on at least one of the plurality of target events. Using the action execution circuit module corresponding to the triggered preset state, one or more actions corresponding to the triggered preset state are executed, where at least one of the one or more actions corresponding to the triggered preset state is associated with controlling the target memory.

Abstract: Managing alert messages and access permissions for applications. In one embodiment, a method is provided. The method includes determining that one or more errors have occurred in a set of applications executing in a set of containers. The method also includes identifying a set of users in view of one or more of the set of containers and a set of files for the set of applications. The method further includes sending, via a set of messaging systems, a set of messages to the set of users to indicate that the one or more errors have occurred in the set of applications.

Abstract: The invention relates to a method of assigning addresses to bus participants connected to a data bus, in which the bus participants are electrically and in particular also mechanically coupled to a respective base plate, with the base plates each comprising an electrical test element; the base plates are electrically connected along a row to adjacent base plates in each case, with the base plates forming a test circuit in which the test elements are preferably connected in series; a central unit is connected to the test circuit; a test current is impressed into the test circuit; at least one bus participant, in particular a bus participant without a bus address, makes a change to the test circuit; the change of the test circuit is measured by means of the central unit; and based on the change of the test circuit, a position of the bus participant making the change or of the bus participant without a bus address is determined and a bus address is assigned to the bus participant making the change or to the b

Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.

Abstract: Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.

Abstract: The present disclosure describes apparatuses and methods for automatically mapping virtual functions to storage media to enable single root input output virtualization. A storage media switch manages access to virtual functions that execute behind a storage media interface managed by the switch. The switch includes a host interface through which the switch receives host commands. The switch determines virtual function identifiers associated with the host commands and automatically selects the virtual functions of the storage media based on the virtual function identifiers. The switch executes the host commands over the storage media interface using the virtual functions, and after execution, responds via the host interface to each of the host commands. By automatically mapping virtual functions in this way, the switch automatically enables single root input output virtualization of storage media, including storage media that is without native support for input output virtualization.

Abstract: A device for contactless communication with a terminal, comprising: an antenna for communication with the terminal; an embedded chip configured to communicate with the terminal in accordance with a contactless transmission protocol whereby a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip to maintain a connection with the terminal, the embedded chip being configured to communicate requests to the terminal to extend the waiting time for response; and a module configured to perform processing formed of a plurality of discrete operations, the module being configured to, in response to completing a subset of one or more discrete operations within a waiting time interval set by the terminal, send a first type of command to the embedded chip if the processing is not complete; wherein the embedded chip is further configured to, in response to receiving the first type of command, communicate a request to the terminal to extend the waiting time for response.

Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

Abstract: A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.

Abstract: A card-type storage device includes a processing chip and a memory module. The processing chip is selectively operated in a data accessing mode or a data uploading mode. The memory module is electrically connected with the processing chip. A first data set generated by the medical device at a first time point and a second data set generated by the medical device at a second time point are stored in the memory module. In the data accessing mode, a first storage list is established by the processing chip according to the first data set, and the first storage list is updated as a second storage list according to the second data set. If the processing chip judges that the second data set satisfies a predetermined condition, the processing chip enters the data uploading mode.

Abstract: Techniques for detecting a loss of a received frame are provided. The communication apparatus 101 includes a receiving unit 813 for receiving a frame including a plurality of data, a first memory 806 for temporarily storing a plurality of data, a second memory 811 for storing a transfer rule of each data, a plurality of third memories 809 to which each data is allocated, a processor 810 associated with each third memory 809, and a memory control unit 805 for controlling transfer of each data. The memory control unit 805 outputs an error when the first data is not the last data of the frame or the size of the first data is larger than the size defined by the second data in the case where the second data includes the last data flag.

Abstract: Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.

Abstract: Techniques are disclosed relating to address mapping for message signaled interrupts. In some embodiments, an apparatus includes interrupt control circuitry configured to process, from multiple client circuits, message signaled interrupts that include addresses in an interrupt controller address space. First and second interface controller circuitry may control respective peripheral interfaces for multiple devices. Remap control circuitry may be configured to access a first table based on at least a portion of virtual addresses of a first message signaled interrupt from the first interface controller circuit and generate a first address in the interrupt controller address space based on an accessed entry in the first table and access a second table based on at least a portion of virtual addresses of a second message signaled interrupt from the second interface controller circuit and generate a second address in the interrupt controller address space based on an accessed entry in the second table.

Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.

Abstract: Circuits and techniques are described for high-speed transceivers (e.g., repeaters such as re-drivers or re-timers) that ensure that the instantaneous voltage at an input or output of a connected device remains within a desired or specified voltage range.

Abstract: An apparatus, method, system, and computer-readable medium are provided for maintaining contact information associated with a contact. In some embodiments a request associated with a contact may be received. Contact information may be obtained from one or more external or internal sources. One or more confidence scores may be generated for the obtained contact information and for one or more values received with the request. Based on the confidence score(s), one or more values associated with the contact may be incorporated in one or more data stores. In some embodiments, suggestions for contact related information may be generated. Responses to the suggestions may be used to update the generated confidence score(s).

Abstract: A method for access to the shared resources of a computer platform including a multicore processor, shared resources between first partitions according to which requests to access the shared resources emitted by the first partitions are sent to a second partition that, during its execution on the processor, performs said accesses; multiple cores are reserved synchronously for the execution of the second access partition during a predetermined time; the separate accesses to separate shared resources done by the second partition having to be done by separate reserved cores; and all of the accesses to a shared resource done by the second access partition having to be executed, during said predetermined time, by a single core among the reserved cores.

Abstract: The update progress of a basic input/output system (BIOS) is displayed on a display screen. A first chipset lock is applied to a first region of a shared serial peripheral interface (SPI) chip of the BIOS of a computer system containing a first program of instructions. A system management memory mode lock is applied to a second and a third region of the shared SPI chip containing a second and third programs of instructions respectively. The second program of instructions is updated, and control of the BIOS is transferred to the updated second program of instructions. The updated second program of instructions updates the first program of instructions. The BIOS update progress visual is displayed on the display screen of the computer system while updating the first program of instructions.

Abstract: A data storage device, such as a solid state drives (SSD), includes command completion interrupt coalescing. A controller of the data storage device includes one or more completion queues, each including interrupt coalescing protection logic. The interrupt coalescing protection logic detects that a head pointer or a tail pointer in a completion queue has not changed for a predetermined period of time. When the head and tail pointers have not changed for the predetermined period of time, the controller posts an interrupt to a host device.

Abstract: A processing unit for a multiprocessor data processing system includes a processor core having an upper level cache and a lower level cache coupled to the processor core. The processor core is configured to, based on receipt of an interrupt, generate and issue a synchronization request prior to executing an interrupt handler and is configured to, based on receipt of a synchronization acknowledgment for the synchronization request, execute the interrupt handler. The lower level cache is configured to, based on receipt of the synchronization request, record which of its state machines are active processing a prior snooped request that can invalidate a cache line in the upper level cache, and is configured to, based on determining that each such state machine has completed processing of its respective prior snooped request, issue the synchronization acknowledgment to the processor core.

Abstract: A parallel processing apparatus includes: nodes that execute information processing; and a control device, wherein the control device includes processing units provided corresponding to the nodes and configured to process a command received from the corresponding node and a data string, each of the processing units includes a reception data register in which data pieces in a reception data string are stored, a reception data buffer to which the data piece is transferred from the reception data register, a reception completion detector that detects completion of transfer of the reception data string, a fault detector that detects whether the received command is a fault command, and an interrupt issuer that issues an interrupt based on detection of the fault command, and issues an interrupt based on detection of the completion of the transfer of the reception data string when the fault detector does not detect the fault command.

Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

Abstract: The subject matter of this specification can be implemented in, among other things, a method that includes establishing connections between a host server and client devices associated with one or more local devices, receiving from the client devices configuration requests to configure, on the host server, drivers for the local devices to convert data between a data format accessible to the local devices and a data format accessible to applications provided to the client devices by the host server, identifying execution priority of the client devices, identifying a first group of configuration requests and a second group of configuration requests, executing, in order of decreased priority of client devices, the first group of configuration requests until an occurrence of a restart condition, and responsive to the occurrence of the restart condition, executing the second group of configuration requests.

Abstract: A robotic process automation (RPA) system receives task prioritization inputs that specify prioritization for processing of a set of RPA tasks. The tasks are performed in accordance with the specified priorities. The RPA system also receives queue orchestration commands that specify conditions under which tasks processed from a first queue are sent to another queue for subsequent processing. The RPA system also provides service level automation in accordance with specified parameters. Further task prioritization may be specified to provide quality of service performance.

Abstract: In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken.

Abstract: A data storage device with interruption optimization having a non-volatile memory and a controller is shown. The controller operates the non-volatile memory in response to a host. The controller has a buffer which is filled with an interrupt delay that is evaluated by the host according to the status of the central processing unit of the host. The controller delays sending an interrupt request to the host according to the interrupt delay.

Abstract: A method and an apparatus for invoking a fingerprint identification device are provided. The method includes the following. When a request of a current application to invoke a fingerprint identification device is detected, whether the fingerprint identification device is occupied by a historical application is determined. When the fingerprint identification device is occupied by the historical application, whether the current application meets a preset invoking condition is determined, and then the fingerprint identification device is controlled to process the request of the current application according to the determination result.

Abstract: A method, an apparatus, and a system for analyzing traffic through obtaining flow data of a flow from a switch or a router of a network, calculating an average byte per packet rate (BPR) and a TCP flag ratio (TCPFR) for all flows included in a session including the flow using the flow data, and comparing the average BPR and the TCPFR with an average BPR and a TCPFR of previously-known traffic and determining whether the traffic including the flow is normal traffic or abnormal traffic based on the comparison result are provided.

Abstract: Methods and systems for generating interrupts are provided. One method includes maintaining an in-pointer array by a response direct memory access (DMA) module of an adapter indicating that a message has been posted at a host memory of a host system coupled to the adapter for sending and receiving data using a network; updating an out-pointer array at the response DMA module by a host system processor, after the host system processor reads the message posted at the host memory; receiving event information by a hardware based, interrupt module of the response DMA module, the interrupt module using the event information and information stored at an interrupt array to determine that an interrupt is to be generated for the host processor; and generating the interrupt for the host processor by the interrupt module, without using an adapter processor.

Abstract: An electronic device includes a CPU that executes the process execution program to function as a plurality of process execution units as threads and an execution control unit. The plurality of process execution units use the CPU to execute a process. The execution control unit controls executing of the process by the plurality of process execution units. The execution control unit sets a CPU usage priority level for each of the plurality of process execution units. The execution control unit changes the CPU usage priority level of the job of a type other than a specific type to a priority level that is equal to or less than a specific priority level, when the job of the specific type and the job of the type other than the specific type are simultaneously executed.

Abstract: In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

Abstract: Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process.

Abstract: A mechanism for patching functions in use on a running computer system. A method includes modifying an original function to call a hot patch function. The hot patch function transfers execution control from the original function to a replacement function.

Abstract: A system (211) and method (300) for reliable monitoring of secure application execution events is provided. The system can include a Near Field Communication (NFC) modem (140) for communicating transaction events of a secure contactless transaction (358) with a NFC reader (170), a secure controller (200) for monitoring state transitions caused by the transaction events, and a mobile host communicatively coupled to the secure controller for receiving hardware event notifications of the state transitions. The secure controller can generate message using a hardware interrupt to a mobile host based on secure applet state transition monitoring by setting up the events flag such as a Transaction Completion Flag (TCF) (372) into an Events Status Register (232) to identify a status of a secure contactless transactions.

Abstract: Technical solutions are described for determining and analyzing timing parameters to prognosticate a failure of one or more RTOS tasks. An example method includes dequeing a buffer queue entry from a buffer queue. In response to determining that a first task-id from the buffer queue entry does not match a second task-id from a topmost entry of a stack comprising buffer queue entries, the method includes pushing the buffer queue entry as a top-entry in a stack, updating a previous time sample value as the timestamp of the buffer queue entry, and accumulating a temporary execution time value for the second task-id from the stack. Further, in response to the first task-id matching the second task-id, computing an execution time value for the second task-id, updating the previous time sample value as the timestamp of the buffer queue entry, and popping the topmost entry from the stack.

Abstract: A print device has a port, a print engine, a processing device and a memory. The print device is configured to detect that a portable memory device has become communicatively connected to the port, retrieve a digital document file to be printed and a print instruction from the portable memory device, determine that a first print job is being performed in the print device, suspend the first print job, determine a second print job derived from the digital document file, and automatically perform the second print job based on the print instruction. The print device further detects that the second print job has been completed or interrupted, and automatically resumes the first print job. If the second print job is directed to the same output tray as the first print job, the print device may also print a separator sheet to the output tray before performing the second print job.

Abstract: A print device that has a port, a print engine, a processing device and a memory. The print device is configured to detect that a portable memory device has become communicatively connected to the port, retrieve a digital document file to be printed and a print instruction from the portable memory device, determine that a first print job is being performed in the print device, determine a priority for the first print job and a priority for a second print job derived from the digital document file, and determine that the priority of the first print job is lower than that of the second print job. The print device is also configured to suspend performance of the first print job, automatically perform the second print job based on the print instruction, detect that the second print job has been completed or interrupted, and automatically resume the first print job.

Abstract: Remotely debugging a non-responsive operating system (OS) of a computer system. Central processing units (CPUs) in a computer system are bound to receive queues of a network adapter. Interrupts for a CPU is disabled, wherein the CPU is not available to process hardware interrupt requests queued in the bound receive queues. A debugging message including debugging commands is received by the network adapter, wherein the debugging message is stored in a first receive queue of the network adapter bound to a first CPU. If the first CPU is available, the debugging commands in the debugging message stored in the first of the one or more receive queues of the network adapter are identified by a debugger of the computer system. The identified debugging commands are executed by the CPU to debug the non-responsive OS of the computer system.

Abstract: The embodiments are directed to methods and systems for sending and receiving signals between one or more peripheral devices connected to a dongle system and an operating system. The methods and systems can detect when a dongle system has been connected to a mobile computing device. The methods and systems can receive an input to use the dongle system with a local operating system or a remote operating system. The methods and systems can also establish a communication channel between the local operating system and the remote operating system, and exchange signals between the dongle system and the remote operating system using one or more virtual filters.

Abstract: An information handling system is provided. The information handling system includes an information handling device having one or more processors in communication with a network interface card. The network interface card includes one or more interfaces for receiving frames the information handling device is coupled to an external network device. The device also includes a memory that is in communication with the one or more processors and stores a classification matrix. The classification matrix is used to generate a current interrupt throttling rate from a plurality of candidate interrupt throttling rates that are applied to the received frames according to at least two properties of each frame of the received frames. A method for providing adaptive interrupt coalescing is also provided.

Abstract: A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU.

Abstract: In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

Abstract: The present disclosure provides methods and apparatus for rapid interrupt look-ups for interrupts stored in memory. One embodiment relates to a method for providing interrupt lookups for a plurality of interrupt status vectors stored in random access memory on an integrated circuit. The plurality of interrupt status vectors in the random access memory are scanned to find activated interrupt status vectors that changed from null to non-null and dismissed interrupt status vectors that changed from non-null to null. A linked search list is maintained in the random access memory by inserting memory addresses of the activated interrupt status vectors into the linked search list and removing memory addresses of the dismissed interrupt status vectors from the linked search list. Interrupt status vectors for currently active interrupts are looked-up by transversing the linked search list in the random access memory. Other embodiments, aspects and features are also disclosed herein.