Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: A storage processor for a block storage RAID array services disk storage block requests from one or more hosts. At its heart, a application specific integrated chip (ASIC) supports a store and forward data transfer regime in that host to disk transfers are made by placing data in storage processor memory under control of the storage processor, operated on by the ASIC, and sent to the disk array. Efficient handling of ordering is, preferably, provided by hardware logic-based masking of interrupts and by other mechanisms. Embodiments help to insure that shared data paths are flushed of non-critical data quickly to sustain more critical data, for example, that required to sustain high throughput.

Abstract: Provided are a method, system, and program for handling interrupts. A request is received as to whether a device transmitted an interrupt and a determination is made as to whether the device transmitted the interrupt. If the device transmitted the interrupt, then indication is made that the device did not transmit the interrupt and work from the device related to the interrupt is processed.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: A system and method are described to programmatically manage access between one or more nodes and a plurality of associated devices, such as shared storage units. Each node is programmed to include a data structure, which identifies whether an associated device is to be within the scope of the respective node. The data structure and may include persistent and/or temporary lists. Each device may be programmatically masked relative to the node by dynamically modifying the data structure of the node, such as by employing a predetermined interface.

Abstract: The invention relates to a method of executing a real-time task by a digital signal processor using a cache memory, an overall duration being allocated for executing said task and any interrupts coming from peripherals associated with the processor, wherein the overall duration is subdivided into a plurality of time intervals comprising at least one masked period during which said task is executed and interrupts are made to wait and are grouped together, and at least one non-masked period during which said task is suspended and the group of interrupts is executed. The masked periods and the non-masked periods are defined by a hardware mechanism including a timer.

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: High-speed data streams are exchanged between two digital computing devices one or both of which lacks DMA. Data transfers are performed by the devices using High-Level Datalink Control (HDLC) frames. An initiating device indicates that it wishes to exchange data with the other device by sending an HDLC frame with data stream indentification and other information. The initial HDLC-frame is sufficiently short that at least an essential portion of the frame can be stored in a receive buffer of the interface circuitry. Although the receiving device may not receive the entire HDLC frame correctly because of the possibility of an overrun condition, enough information is preserved in the interface circuitry to complete the transaction. The responding device then proceeds to read or write data at high speed using a series of exchanges with the initiating device.

Abstract: A method and apparatus for initializing a computer system, which includes a lockable nonvolatile memory coupled to a processor having maskable address lines and a cache, when a nonvolatile memory update is in process. When an update is in process, the nonvolatile memory is unlocked in response to the initialization event only if address line masking is disabled, and at least a portion of the processor cache is invalidated to ensure the processor will fetch the first instruction from the nonvolatile memory.

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.

Abstract: Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a J-bit source string and an N-bit destination string. The source address points to the memory location of the J-bit source string. The destination address points to the memory location of the N-bit destination string. The shift number indicates the number of bits the J-bit source string is to be shifted to generate a shifted bit string. The combination of the shifted bit string with the N-bit destination string is conducted under the control of the K-bit mask string. The invention is useful for high speed digital data processing, such as that performed by devices operating under the IEEE 1394 protocol.

Abstract: A method and apparatus for determining a longest prefix match in a segmented content addressable memory (CAM) device. The CAM device includes multiple CAM array blocks that each may be arbitrarily loaded with CIDR addresses. For one embodiment, each CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), and prefix logic circuits for comparing the logical state of the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix in each CAM array block from among CAM entries that match the search key. The longest prefixes from each block are provided to compare circuitry that determines which of the longest prefixes is the longest for the entire CAM device.

Abstract: A method and apparatus for selectively writing data elements from packed data based upon a mask using predication. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in parallel processing units: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.

Abstract: A method of securing a boot process for a computer system enables a processor to boot from a location identified by a boot vector. The method includes the step of disabling masking of a maskable address line in response to a processor initialization event. In one embodiment, an apparatus includes a processor coupled to a memory by at least one maskable address line wherein the memory is storing a first initialization instruction. The apparatus includes a mask control wherein the mask control disables masking of the maskable address line before the processor attempts to access the first initialization instruction in response to an initialization event. In one embodiment a processor chipset gates a first address mask control with an inhibit bit to generate a second address mask control. The second address mask control is independent of the first address mask control when the inhibit bit is set to a first value.

Abstract: A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU.

Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

Abstract: An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.

Abstract: In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special consideration to the interrupt of the microinstructions translated from a macroinstruction using two control bit data, accelerate the reaction time to interrupts, and expand the time frame within which to process interrupts while maintaining a precise interrupt. When a macroinstruction is decoded into microinstructions at the decoder stage in a pipelined data processor, a control bit called the atomic bit provides the system with the information about the boundary of the precise interrupt, and another control bit called the LOCK bit decides when an external interrupt can be processed and masks an interrupt when the system state does not allow any interrupt to be processed.

Abstract: A computer system is provided that has an input-output processor having a non-masking interrupt. In addition to the central processing unit, the computer system has a host bus, a host operating system, at least one input-output bus connected to the host bus. At least one input-output device is connected to the input-output bus with facilities for connecting many more. In addition to the above-mentioned components, the computer system also includes a mask register. The mask register is capable of receiving input-output related messages from the host or from a local input-output device. The mask register is able to write a MASK signal based upon the received signals. Along with the mask register, the computer system is provided with a status register. The status register is capable of receiving input-output write messages from the host or from a local input-output device. The status register is used to write an INT signal based upon the message it receives.

Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: A SCSI system including a SCSI controller, daisy-chained SCSI connectors to which SCSI devices are to be connected, and a SCSI cable interconnecting the SCSI connectors. The SCSI controller includes a circuit for controlling a REQ signal that is allowed to flow through two lines in the SCSI cable, and for controlling an ACK signal that is also allowed to flow through another two lines in the SCSI cable. One of the two lines for conveying the REQ signal alternately connects an unused pin and a REC pin of two successive SCSI connectors, and the other of the two lines alternately connects a REQ pin and an unused pin of the two successive controllers. The two lines for conveying the ACK signal interconnect the SCSI connectors in a similar manner. This enables the load capacitance of the REQ and ACK control signal lines to be reduced, thereby ensuring normal operation of up to seven high speed SCSI devices, that is, the maximum number of devices connectable to the SCSI system.

Abstract: A system, device, and method allowing a host device to communicate with, and initialize, an uninitialized peripheral device includes, on the peripheral device, logic for storing a separate mask corresponding to each of a plurality of memory locations, and logic, responsive to a request for reading a memory location, for outputting a bit-wise exclusive-OR of data stored in the memory location and the corresponding mask. The mask is equal to a bit-wise exclusive-OR of a predetermined configuration value and a preset value. Thus, if the memory location is not pre-programmed with configuration information, the bit-wise exclusive-OR of the data stored in the memory location and the corresponding mask results in a valid default configuration value. Once the host device is able to communicate with the peripheral device, the host device programs the peripheral device by storing in the memory location a new data value equal to the bit-wise exclusive-OR of a new configuration value and the corresponding mask.

Abstract: A method and apparatus for enabling a computer user to implement intelligent input/output processing involves a connector adapted to receive interrupt request signals from input/output devices in a plurality of slots contained on an input/output bus. When an intelligent input/output card is inserted into the connector, the card can process certain of the interrupt requests from devices contained in slots connected to the input/output bus. This augments the processing of input/output device interrupt requests without burdening the host processor. Thus, a computer system arranged in a peer architecture may be subsequently enhanced with a intelligent input/output card, without burdening all purchasers with the cost of expensive hardware to enable the subsequent upgrade.

Abstract: An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request signal is asserted in response to each interrupt event. In the batch mode, an interrupt request signal is delayed until a predetermined number of interrupt events is detected, or until a predetermined time interval has elapsed since the last interrupt event is captured. In response to an interrupt event, the corresponding bit in an interrupt register is set to an active state. A control interrupt bit is provided in an interrupt control register for each interrupt to enable the activation of an interrupt request pin in response to the interrupt event. A batch enable bit is provided in a batch register for each interrupt event to enable the batching of the interrupt event.

Abstract: A computer processor that allows the execution of the IBM ESA/390 STOSM and STNSM instructions, in an overlapped fashion, contains an apparatus that allows the STOSM and STNSM instructions to be executed without serializing the processor, or otherwise delaying subsequent instructions, after the STOSM or STNSM instruction, in most cases, thereby improving performance. It contains a mechanism that counts cycles after their execution and prohibits asynchronous interrupts during that time. The invention also contains an efficient mechanism for handling the execution of the STOSM and STNSM instructions when the processor is executing in the SIE environment.

Abstract: An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops.

Abstract: A method and apparatus for processing interrupts for a plurality of components connected to and sharing an interrupt line in a data processing system in which interrupts are level sensitive interrupts. The components are connected to the interrupt line by interrupt connections, such as a pin. An interrupt is detected when the interrupt line is in a first state, while an interrupt is absent when the interrupt line is in a second state. Other interrupts cannot be processed while the interrupt line is in a first state. In response to detecting one or more interrupts, the connection associated with the component, for which one or more interrupts are generated, is disabled until all of the interrupts are processed. Disabling the interrupt connection allows the interrupt line to return to the first state and for additional interrupts for other components connected to the interrupt line to be detected and processed.

Abstract: A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.

Abstract: Strings, such as Web pages or other documents, are fingerprinted in order to detect substantially similar strings, so as to avoid processing duplicate strings. At the same time determine a computerized method estimates the probability that a collision among fingerprints of dissimilar strings. As fingerprints are generated for strings presented for processing, when the fingerprint of a string is determined not to be identical to any fingerprint in a set of stored fingerprints, the new fingerprint is masked and the unmasked portion of the fingerprint is compared with a corresponding portion of the fingerprints in the stored set. Information is recorded regarding the number of matching masked fingerprints.

Abstract: A controller handles host commands from a host processor and also interfaces the host processor to a serial device. Storage circuitry (e.g., a shift register) of the controller holds a predetermined plurality of data bits. State machine circuitry controls the storage circuitry for serial bit-level communication (e.g., using a PS/2 protocol) between the storage circuitry and the serial device. A processor executes code from a program memory. In particular, the program code causes the processor to detect that a host command has been received by the controller from the host processor and causes an action corresponding to the host command received. Because the processor is not involved with the serial bit-level communication between the storage circuitry and the serial device, the processor executing the software can handle host commands without affecting the serial bit-level communication.

Abstract: The apparatus and method for high speed data and command transfer over an interface (202), such as an ISA or PCMCIA bus or interface, includes a transceiver (206) and a processor (210) having a direct memory access (DMA) controller (240), a memory (211) for storage of data, and a channel interface (218) for connection to a communications channel. The processor (210) is responsive through a set of program instructions, such as software or firmware, to receive an interrupt signal (310, 315) and, when the interrupt signal indicates a write command (320, 330), to transfer data via the transceiver from the interface to the memory for transmission over the communications channel (335), and when the interrupt signal indicates data received from the communications channel (350), the processor further responsive to generate a read command and transfer data from the memory to the interface via the transceiver (355).