Abstract: Memory systems and method of operating the same enable debugging of a memory system with vendor unique (VU) commands without using a physical cable connection to a debugging port on the memory system. In one aspect, a Universal Asynchronous Receiver-Transmitter (UART) protocol is serialized over a VU host protocol. In another aspect, Joint Test Action Group (JTAG) may be performed over UART or serial advanced technology attachment (SATA).

Abstract: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI #) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU cores continue operating in normal mode. Further, a multi-threaded SMM environment and mutual exclusion objects (mutexes) may allow guarding of key hardware resources and software data structures to enable individual CPU cores among the remaining CPU cores to subsequently also enter SMM in response to a different SMI while the originally selected CPU core is still in SMM.

Abstract: Systems, apparatuses, and methods for utilizing efficient vectorization techniques for operands in non-sequential memory locations are disclosed. A system includes a vector processing unit (VPU) and one or more memory devices. In response to determining that a plurality of vector operands are stored in non-sequential memory locations, the VPU performs a plurality of vector load operations to load the plurality of vector operands into a plurality of vector registers. Next, the VPU performs a shuffle operation to consolidate the plurality of vector operands from the plurality of vector registers into a single vector register. Then, the VPU performs a vector operation on the vector operands stored in the single vector register. The VPU can also perform a vector store operation by permuting and storing a plurality of vector operands in appropriate locations within multiple vector registers and then storing the vector registers to locations in memory using a mask.

Abstract: A data storage device may include non-volatile storage media that includes a long-term storage region divided into a plurality of physical regions and a temporary storage region that includes at least two first tier bins. Each logical block address (LBA) span of a plurality of LBA spans may be associated with at least one physical region. Each first tier bin may be associated with a respective LBA subset of the plurality of LBA spans that includes at least two LBA spans and less than all LBA spans. The data storage device may also include a processor configured to receive first data having an LBA from a first LBA subset and second data having an LBA from a second LBA subset, and writing the first data to a first bin associated with the first LBA subset and writing the second data to a second bin associated with the second LBA subset.

Abstract: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

Abstract: Systems and methods are disclosed for processing a queue associated with a request. An example system includes an input/output (I/O) interface that receives a request associated with a channel. The example system also includes an association module that determines whether a condition is satisfied. When the condition is determined to not be satisfied, the association module, after a hardware device completes processing the request, decrements an in-flight counter that represents a first amount of data in the channel. When the condition is determined to be satisfied, the association module, before the hardware device completes processing the request, decrements the in-flight counter.

Abstract: Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: Files on a secondary storage are accessed using alternative IO subroutines that buffer IO requests made by a user and mimic the IO subroutines provided by an operating system. The buffer used by the alternative IO subroutines is maintained by the user and not the operating system. User applications are not recompiled or relinked when using the alternative subroutines because the library that provides these subroutines intercepts requests for buffered IO made by user applications to the operating system's IO subroutines and replaces the requests with calls to the alternative IO subroutines that utilize the buffer maintained by the user.

Abstract: Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction.

Abstract: An input/output interface unit includes a plurality of ports connected to different external units, and adds predetermined identification information unique to each of the ports to an interrupt request received from each of the external units via the ports. An interrupt control unit stores information on the interrupt request received by the input/output interface unit in a vector storage unit based on the identification information. Each of cores executes a process corresponding to the interrupt request stored in the vector storage unit based on the identification information.

Abstract: Techniques for adaptive data transfer are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for adaptive data transfer comprising receiving a write request at an application protocol layer, buffering the write request, transferring to electronic storage a first portion of data of the buffered write request using a first setting value in a range, measuring, a transfer rate of the first portion of transferred data, varying the first setting value by a small amount in a first direction to identify a second setting value, transferring to electronic storage a second portion of data of the buffered write request using the second setting value, measuring a transfer rate of the second portion of transferred data, and replacing the first setting value with the second setting value if the transfer rate of the second portion of transferred data is greater than the first transfer rate.

Abstract: A method and apparatus for efficient interrupt event notification for a scalable input/output device in a network system. A network interface unit is operably connected to a plurality of processing entities and associated memory units. At least one status register in the network interface unit contains information relating to a process to be performed by at least one processing entity communicated to the processing entity by an interrupt event notification. Shared memory space comprises a mailbox storage register operable to store an image of the interrupt information stored in the status register of the network interface unit. A processing entity can directly access the process information stored in the mailbox status register thereby reducing system latency associated with reading information in the status register. Updated process status information in the network interface status register may be read by the processing entity on an interleaved basis while executing a process.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: A method and system for processing an input/output request on a multiprocessor computer system comprises pinning a process down to a processor issuing the input/output request. An identity of the processor is passed to a device driver which selects a device adapter request queue whose interrupt is bound to the identified processor and issues the request on that queue. The device accepts the request from the device adapter, processes the request and raises a completion interrupt to the identified processor. On completion of the input/output request the process is un-pinned from the processor. In an embodiment the device driver associates a vector of the identified processor with the request and the device, on completion of the request, interrupts the processor indicated by the vector.

Abstract: A universal plug and play (UPnP)-based network system and a method of controlling the same. A UPnP device can operate according to a description of each control point (CP) when performing a command, by including the description, which is inherent information of each CP, in a command message transmitted from each CP to the UPnP device and allowing the UPnP device to analyze the command message to obtain the description of the CP. The UPnP-based network system includes a plurality of CPs, each of which stores a CP description, which is inherent characteristic information of each CP, and generates and transmits a command message including the CP description, and a UPnP device which is connected to the plurality of CPs over a network, analyzes the command message received from each CP to perform an operation according to the command message, and analyzes the CP description included in the command message to recognize each CP which transmits the command message.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: A computer system for software development and debugging for an embedded system includes a Universal Serial Bus (USB), a host computer comprising a USB driver interfaced with the USB, wherein the USB driver can multiplex application data and debug data to and from the USB, and an embedded system comprising a USB module interfaced with the USB. The USB module can multiplex the application data and the debug data to and from the host computer via the USB.

Abstract: A universal plug and play (UPnP)-based network system and a method of controlling the same. A UPnP device can operate according to a description of each control point (CP) when performing a command, by including the description, which is inherent information of each CP, in a command message transmitted from each CP to the UPnP device and allowing the UPnP device to analyze the command message to obtain the description of the CP. The UPnP-based network system includes a plurality of CPs, each of which stores a CP description, which is inherent characteristic information of each CP, and generates and transmits a command message including the CP description, and a UPnP device which is connected to the plurality of CPs over a network, analyzes the command message received from each CP to perform an operation according to the command message, and analyzes the CP description included in the command message to recognize each CP which transmits the command message.

Abstract: Method and system for latency-independent peripheral device identification. The computer system receives an interrupt from a peripheral device via a communications port. In response, an interrupt notification message is posted to alert a notification handler, and compliant peripheral class is determined. The voltage on a device may sense pin of the communications port for this determination. If the interrupt is indicative of the compliant peripheral class and the communications port is inactive, the port is opened, and an inquiry is sent and a response is received. If a response is received within a predetermined time period, an identification notification message is posted based on the response including information for classifying the peripheral device, so that a software handler registered with the operating system can handle the identification notification message when the software handler receives it. Thus, no time-critical interrupt response requirement is imposed for its successful operation.

Abstract: Support for virtualization in a storage area networks may be provided using a variety of techniques. In one embodiment of the present invention, exchange level load balancing may be provided by determining if input/outputs (IOs) received by a device are new. If a particular IO is new, the IO may be assigned to a particular data path processor and an context may be created corresponding to the IO and to the processor. Then, when an event corresponding to the IO is received, the event may be forwarded to the processor assigned to the IO.

Abstract: Methods and systems for coordinating the handling of information are disclosed herein and may include scheduling multiple processing tasks for processing multimedia data by a processor. A portion of the scheduled multiple processing tasks may be preprocessed and the preprocessed portion may be buffered within a modifiable buffer that handles overflow and underflow. A portion of the buffered preprocessed portion of the scheduled multiple processing tasks may be executed. The scheduling may utilize a non-preemptive scheduling algorithm, such as an earliest deadline first (EDF) scheduling algorithm and/or a rate monotonic (RM) scheduling algorithm. The scheduled multiple processing tasks may include at least one maximum real deadline. The preprocessed portion of the scheduled multiple processing tasks may be outputted during processing of the blocking task, if a current task of the scheduled multiple processing tasks comprises a blocking task.

Abstract: An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a plurality communication channels. The integrated circuit may be is capable of communicating with at least one remote node external to the integrated circuit, via at least one of the communication channels, in accordance with at least one communication protocol. Each of said plurality of communication channels may provide a communication path between a host system and at least one remote node. The integrated circuit may be further capable of operating each communication channel independently of each other and independently of the host system. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination of command speculation correctness is made after receipt of the full command. If the full command received is not the speculated non-memory read command, the prepared data is discarded. Earlier prepared data is produced as the subsystem response if the full command matches the speculative non-memory read command. For incoming commands with operands, such as an address, the same speculative determination based on high-order operand bits is performed.

Abstract: Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The wakeup event identifies the individual event queue. The host subsystem, in response to retrieval of the wakeup event from the intermediary event queue, activates an individual event handler to consume events from the individual event queue.

Abstract: Method and system for latency-independent peripheral device identification. In one embodiment, a computer system receives an interrupt from a peripheral device coupled to a computer system communications port. In response, an interrupt notification message is posted alerting a notification handler running on the system. It is determined whether the interrupt is indicates peripheral class compliance. In one embodiment, communications port device sense pin voltage is determinative. If the interrupt indicates peripheral class compliance and the communications port is inactive, the port is opened, and inquiry sent to the peripheral device via the open port. The computer system then waits for response from the peripheral device. If response is received within a predetermined time, identification is posted based on the response, including peripheral device classification information, so that a software handler registered with the operating system can handle the identification message when received.

Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.

Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.

Abstract: Embodiments of the invention improve the efficiency of communication processing between a host and a storage device. In one embodiment, a data processing system includes a storage device and a host. The host gives the storage device an instruction to perform specified processing, and an instruction as to whether or not a completion notification of the instructed processing is to be transmitted to the host. If the host instructs the storage device to transmit a processing completion notification, the storage device transmits the completion notification to the host. On the other hand, if the host instructs the storage device not to transmit a processing completion notification, the storage device does not transmit the completion notification to the host.

Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes.

Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.

Abstract: Provided are a method, system, and article of manufacture for using operation codes to control a decoder's use of a buffer to generate data from an input data stream into an output data stream. An encoder generates an input data stream for a decoder comprising at least one operation code and compressed data for an output device. The at least one operation code instructs the decoder on how to use a buffer when processing the input data stream. The decoder receives the input data stream, processes the data in the input data stream to perform an operation with respect to the buffer according to the at least one operation code, and decodes the compressed data into decompressed data to send to an output data stream to the output device.

Abstract: An apparatus for executing user commands in digital equipment operating in a USB mass storage (UMS) mode is configured in such a manner that a USB connecting unit transmits and receives commands and data to and from a PC serving as a host through a universal serial bus (USB) port. A USB control unit controls the USB connecting unit. A storage unit stores an access command table including access commands allocated respectively to address shift values, by which addresses contained in one or more user commands received from the PC deviate from a valid address range. A microcomputer determines whether the command received through the USB connecting unit is a user command. If it is determined that the received command is a user command, the microcomputer controls executing the access commands allocated respectively to the address shift values based on the access command table.

Abstract: A method and system for tracking the type and amount of data processed by a computer system. In one embodiment, a logging system tracks data processed by a conversion system so that differential billing of customers can be performed based on the type of data and the quality of service required to provide that data. The logging system is integrated as part of the conversion system that converts the data from a source format into a target format. As the data is converted by the conversion routines, the logging system logs the amount of data that is converted by the conversion routines. Thus, the logging system is able to track the data at each conversion routine, such as each level of a communications protocol.

Abstract: In a computer-implemented method for filtering input/output operations of a flash drive, an input/output request directed toward a flash drive is received. It is determined whether the input/output request is associated with a high volume write operation. If the input/output request is associated with the high volume write operation, a flash drive input/output management action to perform is selected. If the input/output request is not associated with the high volume write operation, the input/output request is forwarded to the flash drive.

Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.

Abstract: Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer. A DMA controller may claim the interrupt and may prevent a processor from receiving and/or servicing the claimed interrupt. The DMA controller may further transfer a data block in response to the claimed interrupt.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system.

Abstract: A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on a structure basis, and thus, a coupling facility may include duplexed structures, as well as non-duplexed or simplexed structures.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet of data and am ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: In a multi-modal user interface, user inputs may be made in various different ways. For instance, the user might use a keyboard, a speech system, a vision system, a mouse or pen. Different inputs made by the user may be related and may have different significance. A processing system detects and resolves ambiguities and/or conflicts in inputs made by the user using the different input modes available.

Abstract: Apparatus, method and program product for use in passing initiative to a processor for handling an I/O request for an I/O operation for sending data between a main storage and one or more devices. A hierarchy of vectors registers I/O requests by the devices to send or receive data from the main storage. The hierarchy of vectors has one or more lower levels and a highest level. Each device sets a vector in the lowest level of the hierarchy for registering an I/O request, the setting of a vector in the lowest level being reflected up the hierarchy to the highest level, thereby registering I/O requests on any lower level of the hierarchy in the highest level. A dispatcher polls the hierarchy in high to low order with the dispatcher passing initiative to the processor to handle I/O requests registered in said hierarchy responsive to registering of an I/O request on the lowest level as reflected to the highest level of said hierarchy.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set.

Abstract: Apparatus, method and program product for use in passing initiative to a processor for handling an I/O request for an I/O operation for sending data between a main storage and one or more devices. A hierarchy of vectors registers I/O requests by the devices to send or receive data from the main storage. The hierarchy of vectors has one or more lower levels and a highest level. Each device sets a vector in the lowest level of the hierarchy for registering an I/O request, the setting of a vector in the lowest level being reflected up the hierarchy to the highest level, thereby registering I/O requests on any lower level of the hierarchy in the highest level. A dispatcher polls the hierarchy in high to low order with the dispatcher passing initiative to the processor to handle I/O requests registered in said hierarchy responsive to registering of an I/O request on the lowest level as reflected to the highest level of said hierarchy.