Abstract: A method and system for tracking the type and amount of data processed by a computer system. In one embodiment, a logging system tracks data processed by a conversion system so that differential billing of customers can be performed based on the type of data and the quality of service required to provide that data. The logging system is integrated as part of the conversion system that converts the data from a source format into a target format. As the data is converted by the conversion routines, the logging system logs the amount of data that is converted by the conversion routines. Thus, the logging system is able to track the data at each conversion routine, such as each level of a communications protocol.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: In a system having an DSP, an ASIC and a memory, in which the ASIC generates a number of different competing interrupts for the DSP to service, the ASIC has an interrupt request control module which automatically provides the DSP with a vector pointing to the memory location of the interrupt service routine for the currently pending interrupt request having the highest priority of all pending requests. The DSP reads this vector and uses it to access the interrupt service routine in the memory. Reading of this vector causes the interrupt request to be de-asserted, which causes the next highest priority pending interrupt request to become the highest priority pending interrupt request. As a result, a new vector is presented for the next read by the DSP.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing mechanism having a plurality of queues capable of being shared between a plurality of independent processes running on at least one host and at least one I/O adapter. A finite-state machine (FSM) is provided in the main memory and the FSM is divided into two disjoint sets of states, one of which represents state-values processed by the host and set by the adapter, and said other set represents state-values processed by the adapter and set by said host. Using each of these set of states free-running, non-deadlocking processes are provided within the host and the adapter so that the processes sequence circularly and continuously through a vector related to the FSMs.

Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than or equal to the write address. When the write address for the FIFO queue is less than the read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than the write address plus a maximum depth of the FIFO queue. A first read transaction of the first transaction size from the FIFO queue is performed only when the first condition flag is true.

Abstract: The invention discloses a communication system for exchanging data between a bus and at least one coupled data processing arrangement via a serial interface which is coupled to a microprocessor by a control line via a DMA unit. For effecting an efficient data exchange between a bus and a serial interface by means of a DMA unit while the controlling microprocessor is slightly loaded, the DMA unit, while in an active state featuring an interrupt mode, is provided for transferring an interface control signal to the microprocessor by the control line and, while in an inactive state featuring a DMA mode, is provided for forming at least one DMA control signal from the interface control signal and for transferring the formed DMA control signals to the microprocessor by the control line. For utilizing a serial interface for a data exchange both in the interrupt mode and in the DMA mode, the control line is looped through by the DMA unit.

Abstract: A data processor, includes a central processing unit, an interrupt handler for selectingly signalling a single interrupt vector to the central processing unit, and multiple interrupt sources that are daisy-chained to the interrupt handler, for therewith exchanging interrupt request signals and interrupt acknowledge signals. A Bus (or buses) interconnects all above subsystems. The interrupt handler communicates a read vector command to all interrupt sources in parallel and thereupon allows transmitting an actual interrupt address vector on the bus.

Abstract: An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur when the microprocessor is performing a task switch. The task switch may be performed by hardware included within the microprocessor or, alternatively, by software executing upon the microprocessor.

Abstract: The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt blocks. The interrupt blocks are used for coupling to a corresponding plurality of peripheral devices. Each of the interrupt blocks are coupled to a data bus included within the interrupt controller. The interrupt controller also includes an interrupt control register. The interrupt control register is coupled to each of the interrupt blocks, and upon receiving an internal interrupt request from any of the interrupt blocks, asserts a processor interrupt request responsive to the internal interrupt request. The interrupt controller includes a processor interrupt request line adapted to couple to a programmable digital processor.