Abstract: An apparatus for extracting data from a database for object initialization, and apparatus for writing object data to a database, and corresponding methods are provided. A data extraction kernel on the native-side reads database data from a plurality of locations in the database using a database interface and writes the database data to a buffer using a native-side buffer API (application programming interface). An object initialization kernel on the virtual machine (VM-) side reads the database data from the buffer using a native-side buffer API and initializes a plurality of objects. Information indicating one of the plural memory regions in the buffer where the data extraction kernel writes the database data is known to the native-side buffer API and to the VM-side buffer API. According to the application, fast and memory efficient data exchange between a native side and VM side is achieved.

Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.

Abstract: Disclosed are methods, systems and non-transitory computer readable mediums for estimating bandwidth over packet data networks, for example, 5G networks. The methods, systems and non-transitory computer readable mediums can include modifying a buffer status report (e.g., via application programming interface) and reporting, to an eNodeB, the modified buffer status report. The methods, systems and non-transitory computer readable mediums can also include calculating the required throughput to satisfying transmitting a data amount stored at a regular buffer, receiving, from the eNodeB, uplink grants and transmitting, data from the regular buffer.

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

Abstract: A memory allocation device on an originating node requests an allocation of memory from a remote node. In response, the memory allocation device on the remote node returns a global system address that can be used to access the remote allocation from the originating node. Concurrent with the memory allocation device assigning (associating) a local (to its node) physical address to be used to access the remote allocation, the remote node allocates local physical memory to fulfill the remote allocation request. In this manner, the remote node has already completed the overhead operations associated with the remote allocation requested by the time the remote allocation is accessed by the originating node.

Abstract: Embodiments include systems and methods for communicating information in a physical uplink control channel (PUCCH) message. A processor of a wireless device may configure a PUCCH message to include an uplink message in a short data field. The processor may send the PUCCH message including the short data field to convey the uplink message to a communication network. In some embodiments, the processor may receive data from a second wireless device in a downlink channel, and may generate an acknowledgement message responsive to the received data. The processor may configure the short data field to include the acknowledgement message, and may send the PUCCH message including the short data field that includes the acknowledgement message to acknowledge the received data.

Abstract: A method may be provided to operate a wireless terminal in a Radio Access Network RAN. A plurality of Logical Channel Groups LCGs may be configured for the wireless terminal, and data may be buffered for more than one of the plurality of LCGs for the wireless terminal. A buffer status report BSR may be transmitted to a base station of the RAN, wherein the BSR indicates a size of an aggregation of data buffered for at least two of the plurality of LCGs for the wireless terminal. Related wireless terminals are also discussed.

Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The communication method and system may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method of a user equipment (UE) for receiving data is provided. The method includes receiving, from a base station, information on radio resources allocated to the UE, and receiving, from the base station, data based on the information on the radio resources. The radio resources are associated with a plurality of symbols in a time domain and a plurality of resource block groups in a frequency domain.

Abstract: Embodiments of the present invention relate to a memory system, a memory device, a memory controller and an operating method thereof. A partial mapping table including some of plural pieces of mapping information between physical addresses and logical addresses, which are included in a mapping table stored in the memory device, is cached, a piece of mapping information corresponding to data indicated by a command is referred to in the partial mapping table, and whether to perform an update for a reference-related parameter of the piece of mapping information is controlled depending on a size of the data, thereby improving cache efficiency for mapping informations for processing a request from a host and through this, increasing the success rate of a cache hit.

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

Abstract: An imaging apparatus includes a storing unit configured to, when recording pieces of image data obtained by an imaging unit on a plurality of recording media, respectively temporarily store the pieces of image data obtained by the imaging unit in a plurality of storage regions corresponding to the plurality of recording media, a recording control unit configured to perform control to respectively record the pieces of image data temporarily stored in the plurality of storage regions on the plurality of recording media corresponding to the plurality of storage regions, and a display control unit configured to perform control to display information indicating a use status of a storage region on a display unit, wherein the display control unit performs control to display information indicating the use status only with respect to one storage region out of the plurality of storage regions.

Abstract: Provided is a non-volatile memory including a conductor layer, a memory device, and a selector. The selector is located between and electrically connected to the memory device and the conductive layer. The selector includes a metal filling layer, a barrier layer, and a rectify layer. The metal filling layer is electrically connected to the memory device. The barrier layer is located on the sidewall and the bottom surface of the metal filling layer. The rectify layer is wrapped around the barrier layer. The rectify layer includes a first portion and a second portion. The first portion is located between the barrier layer on the bottom surface of the metal filling layer and the conductive layer. The second portion and the metal filling layer sandwich the barrier layer on the sidewall of the metal filling layer. The first portion has more diffusion paths of metal ions than the second portion.

Abstract: A method, system and product, configured to perform: during an execution of a program, obtaining boundaries of a stack frame of a function that is currently present in a stack, wherein said obtaining the boundaries comprises: obtaining a return address of the function in the stack; determining a length of the function using a mapping of return addresses of one or more functions in the program and corresponding lengths of the one or more functions; and determining the boundaries of the stack frame of the function based on a value of a stack pointer of the stack and based on the length of the function; based on the boundaries of the stack frame of the function, determining that the stack frame is overflown; and in response to said determining that the stack frame is overflown, performing a responsive action.

Abstract: A method for performing uplink transmission in a wireless LAN system according to an embodiment of the present specification may comprise the steps of: receiving, by an AP, a buffer state report frame from a reception STA coupled to the AP, wherein the buffer state report frame is a frame in which a first frame and a second frame are aggregated, the first frame including a first traffic identifier indicating a transmission priority of a first traffic buffered in the reception STA and first queue size information indicating the amount of the buffered first traffic, and the second frame including a second traffic identifier indicating a transmission priority of a second traffic buffered in the reception STA and second queue size information indicating the amount of the buffered second traffic; and transmitting, by the AP, a trigger frame for a plurality of user STAs participating in UL MU transmission on the basis of a buffer state report frame.

Abstract: Methods, systems, and devices for methods for supporting mismatched transaction granularities are described. A memory system may include a host device the performs data transactions according to a first code word size that is different than a second code word size associated with a storage component within the memory system. A cache may be configured to receive, from the host device, a first code word associated of the first code word size and associated with a first address of the storage component. The cache may store the first code word. When the first code word is evicted from the cache, the memory system may generate a third code word of the second size based on the first code word and a second code word stored in the first address of the storage component and store the third code word at the first address of the storage component.

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Abstract: A processor includes a plurality of processing cores; a frequency divider; and a synchronous first in first out (FIFO) buffer. The frequency divider frequency divides a first clock signal that is associated with a first clock domain to provide a second clock signal that is associated with a second clock domain. The synchronous FIFO buffer has a write port that is associated with the first clock domain and a read port that is associated with the second clock domain. The synchronous FIFO communicates the data between the first and second clock domains.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

Abstract: A data transfer apparatus capable of effectively performing image transfer in a simple manner is provided. The data transfer apparatus that transfers image data in an image buffer memory to a display includes: a packet generation section that generates a transfer packet included of valid data and dummy data, the valid data being the image data, and transfers the transfer packet to the display; and a packet generation section that adjusts a ratio between the valid data and the dummy data in the transfer packet based on a data storage amount in the image buffer memory.

Abstract: Systems and methods of compensating for the delay asymmetry of coherent optical modems in a packet optical network include measuring fill levels of one or more queues each including an elastic First-In-First-Out (FIFO) circuit used in a transport mapping scheme, wherein the transport mapping scheme is one or more of client mapping to Optical Transport Unit (OTU) and OTU mapping to Flexible OTN (FlexO); and performing adjustments in a clock based in part on the measured fill levels, wherein the adjustments are configured to reduce a Time Error (TE) in the packet network based on delay asymmetry between two nodes.

Abstract: A method may include operating a program using an input that causes buffer overflow and determining minimum input length that causes buffer overflow and maximum input length that does not cause buffer overflow. The method may include operating program using first input that includes the maximum input length and second input that includes the minimum input length. The method may include collecting call/return pairs for each function of the program using the first and second input and determining, based on a difference between call/return pairs, a function that causes buffer overflow. The method may include determining whether a number of calls exceeds a threshold. In response to the number of calls exceeding the threshold, the method may include inserting a patch configured to prevent buffer overflow in a calling function.

Abstract: A ribbon transition tool modifies a 200 ?m ribbon for splicing to a 250 ?m ribbon. A spreader comb is fixedly mounted at the front end of the base of the tool. A straight comb is slidably mounted to the base behind the spreader comb. The combs each have a plurality of fiber channels corresponding to the fibers in the fiber ribbon. At the front end of the spreader comb, the channels have a spacing matching the initial spacing of the fiber ribbon. At the rear end of the spreader comb and throughout the straight comb, the channels have a spacing matching the modified spacing. An anvil is mounted into the base so as to be movable between a lowered position, in which the anvil lies underneath the straight comb, and a raised position, in which the anvil fills the gap between the combs when they are separated.

Abstract: In one embodiment, a next set of packets in a first flow may be identified. A counter may be incremented, where the counter indicates a first number of initial sets of packets in first flow that have been identified. The identified next set of packets may be prioritized such that the first number of initial sets of packets in the first flow are prioritized and a sequential order of all packets in the first flow is maintained. The identifying, incrementing, and prioritizing may be repeated until no further sets of packets in the first flow remain to be identified or the first number of initial sets of packets is equal to a first predefined number.

Abstract: An adaptive self-configuring sensor node is disclosed herein. The node is associated with one or more sensor, and can include a microcontroller unit (MCU), sensors and a wired/wireless communication module (e.g., transceiver) to communicate the data collected by the sensors. Sensor node software running on the CPU can be adaptively reconfigured based on the sensors connected with the node, and using configuration data that is read from a non-volatile memory (NVM). The NVM can further store loadable sensor device specific data acquisition and processing (DAP) routines corresponding to one or more of the sensors, which can be executed to configure a sensor or cause collection or processing of sensor data.

Abstract: Emulating a NIC for packet transmission on hardware RSS unaware NICs in a multi-core system enables each of a plurality of slave packet engines to emulate a NIC for packet transmissions locally even though the actual NIC transmissions from the queue are handled by a master packet engine only. Each slave packet engine treats a local software-implemented transmission queue as a device queue and uses the local queue to keep track of status of data from the packet engine in the device output queue, handled by the master packet engine on behalf of the slave packet engines. As the master packet engine transmits the data from the queue and the status of the queue changes, the master packet engine and the slave packet engines may use pointers to keep track of which data packets are transmitted, which data packets are drained and which data packets are still in the queue.

Abstract: The present disclosure generally discloses a data plane configured for processing function scalability. The processing functions for which scalability is supported may include charging functions, monitoring functions, security functions, or the like.

Abstract: Embodiments herein relate to method in a wireless device (10) for handling data transmissions in a radio communications network (1). The wireless device (10) is served by a first radio base station (12) and a second radio base station (13) providing dual connectivity to the wireless device (10) in the radio communications network (1). The wireless device (10) evaluates whether a trigger condition for buffer status reporting is fulfilled. When the trigger condition is fulfilled, the wireless device (10) transmits a buffer status report to the first radio base station and/or the second radio base station.

Abstract: Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).

Abstract: Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.

Abstract: A method for making available measuring data of a value-document processing apparatus for processing value documents includes feeding individual value documents in real time, measuring data for the value documents are captured by means of a sensor device and stored in an intermediate memory, such that feeding of individual value documents and/or the capturing of measuring data the current utilization of the intermediate memory is compared to a predetermined limit utilization, dependent on the comparison. The feeding of value documents is interrupted and measuring data from the intermediate memory are permanently stored in a permanent memory, and during the permanent storing and/or after the permanent storing of the measuring data in the permanent memory the intermediate memory is released again. After release of the intermediate memory the feeding of individual value documents and capturing and storing of measuring data for the fed value documents in the intermediate memory is restarted.

Abstract: Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.

Abstract: In response to receiving a write request directed to a particular logical block of a storage object, a page of free space (sufficient to accommodate the payload of the write request, but smaller in size than the logical block) of a particular extent that has been selected to store contents of the logical block is allocated. The current size of the extent is smaller than the combined sizes of logical blocks that are mapped to the extent. The page is modified in accordance with a payload indicated in the write request. In response to a subsequent write request directed to the particular extent, a determination is made that the particular extent would violate a free space threshold criterion if the payload of the write request were accommodated, and an extent expansion operation is initiated.

Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Abstract: According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.

Abstract: A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.

Abstract: According to one embodiment, a method for dynamically changing a buffer threshold in a tape drive includes determining that a drive buffer is emptied of data, calculating a write size indicating an amount of data from a transaction size left to be written to a tape prior to a next anticipated sync command, setting a buffer threshold that triggers a back hitch to a smaller value when the transaction size is less than a buffer size, setting the buffer threshold to the smaller value when an absolute difference between the transaction size and the write size is greater than or equal to the buffer size, and setting the buffer threshold to a larger value when the transaction size is not less than the buffer size and/or the absolute difference between the transaction size and the write size is less than the buffer size.

Abstract: A program trace data compression mechanism in which execution of a variable length execution set (VLES) including multiple non-branch conditional instructions are traced in real-time in a manner that allows the instruction execution to be reconstructed completely by correlating the trace data with the traced binary code.

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array and a control circuit. The configurable storage block may receive a mode selection command. The control circuit may determine to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order based on the mode selection command. Thus, the configurable storage block may implement first-in first-cut modules or last-in first-out modules and variations thereof in addition to implementing memory modules with random access.

Abstract: A data storage device includes a plurality of flash memory devices. A memory controller is configured to receive a request from a host computing device to write a first logical block of application data to the data storage device, write the first logical block to a data buffer, wherein a size of the data buffer is larger than the logical block and may store multiple logical blocks, write one or more logical blocks of garbage-collected data to the data buffer, and write the logical blocks in the data buffer to the data storage device when the data buffer becomes full. The data buffer written to the data storage device includes at least one logical block of application data and at least one logical block of garbage-collected data. In an alternative implementation, garbage-collected data may be written to the data buffer upon expiration of a timer.

Abstract: Provided are a storage device, method, and program for controlling a tape speed to manage a tape drive buffer. A tape speed is increased from a current tape speed to a target tape speed on a predetermined speed-change timing to control the reading or writing of data between the buffer and the tape medium.

Abstract: A processor has access to processing units for performing data processing and to libraries. Functions in the libraries are implementable to perform parallel processing and graphics processing. The processor may be configured to acquire (e.g., to download from a web server) a download script, possibly with extensions specifying bindings to library functions. Running the script may cause the processor to create, for each processing unit, contexts in which functions may be run, and to run, on the processing units and within a respective context, a portion of the download script. Running the script may also cause the processor to create, for a processing unit, a memory object, transfer data into that memory object, and transfer data back to the processor in such a way that a memory address of the data in the memory object is not returned to the processor.

Abstract: A system and method for routing data is provided. The system includes a communication interface, a FIFO and a processor module. The communication interface may transmit or receive data. The FIFO is operable to buffer data that has been received by the communication interface. The FIFO is also operable to buffer data that will be transmitted from the communication interface. The processor module is connected to the FIFO and is operable to monitor for data, decode a route according to the data, and move data according to the route and the amount of data in the FIFO.

Abstract: A distance calculating unit calculates a distance from a current position on a tape to the end of the tape. A command processing unit receives a write command. If the distance is small, a determining unit sets a usable capacity of a buffer to be equal to a maximum capacity of the buffer. If the distance is large, the determining unit sets the usable capacity of the buffer according to the distance. If a capacity for data indicated by the write command is less than or equal to a difference between the usable capacity and current usage of the buffer, a buffer managing unit stores the data in the buffer. When the command processing unit receives a write FM command, the buffer managing unit reads the data from the buffer, updates the current usage, and a channel input/output unit writes the data to the tape.

Abstract: The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network.

Abstract: Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored in a cache line. If the field indicating the size of the usable data in the cache line indicates a size less than the maximum storage size, a value may be assigned to a field in the cache line indicating which subset of the data in the field to store data is usable data. A cache request may determine whether the size of the usable data in a cache line is equal to the maximum data storage size. If the size of the usable data in the cache line is equal to the maximum data storage size the entire stored data in the cache line may be returned.

Abstract: The invention is a method of analyzing the wear of a non volatile memory embedded in a secure electronic token. A set of events are intended to generate writing and/or erasing operations in said memory. The token comprises a buffer. The method comprises the following steps: each time an event belonging to said set occurs, generating a data which reflects the event and storing said data in the buffer, sending the buffer to a remote machine, analyzing the buffer to determine the wear of the memory.

Abstract: The invention relates to an access controller which comprises a module (24) for managing writing in a circular buffer (16), means (38) for storing a first read pointer (PL) and a second write pointer (PE), a module (30) for managing reading in the circular buffer (16), means (24, 30, 40) for blocking reading, respectively writing, means (38) for storing a read or write work pointer (PT) which is different from the first and second pointers (PL; PE), and means (24, 30, 40) for updating the wo: pointer (PT) according to a predetermined update logic. The predetermined update logic comprises forward or backward movements of the work pointer (PT) inside the circular buffer (16), and the controller includes means for blocking the read or write work pointer if the read work pointer (PT) points outside a memory space reserved for reading or, respectively, if the write work pointer (PT) points outside a free memory space for writing.

Abstract: The present invention includes a network telephone having a microphone coupled to provide voice data to a network, a speaker coupled to facilitate listening to voice data from the network, a dialing device coupled to facilitate routing of voice data upon the network, a first port configured to facilitate communication with a first network device, a second port configured to facilitate communication with a second network device and a prioritization circuit coupled to apply prioritization to voice data provided by the microphone.

Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.