Fullness Indication Patents (Class 710/57)
  • Patent number: 10444435
    Abstract: A ribbon transition tool modifies a 200 ?m ribbon for splicing to a 250 ?m ribbon. A spreader comb is fixedly mounted at the front end of the base of the tool. A straight comb is slidably mounted to the base behind the spreader comb. The combs each have a plurality of fiber channels corresponding to the fibers in the fiber ribbon. At the front end of the spreader comb, the channels have a spacing matching the initial spacing of the fiber ribbon. At the rear end of the spreader comb and throughout the straight comb, the channels have a spacing matching the modified spacing. An anvil is mounted into the base so as to be movable between a lowered position, in which the anvil lies underneath the straight comb, and a raised position, in which the anvil fills the gap between the combs when they are separated.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: October 15, 2019
    Assignee: OFS FITEL, LLC
    Inventors: Denis Edward Burek, Yue Liang
  • Patent number: 10382345
    Abstract: In one embodiment, a next set of packets in a first flow may be identified. A counter may be incremented, where the counter indicates a first number of initial sets of packets in first flow that have been identified. The identified next set of packets may be prioritized such that the first number of initial sets of packets in the first flow are prioritized and a sequential order of all packets in the first flow is maintained. The identifying, incrementing, and prioritizing may be repeated until no further sets of packets in the first flow remain to be identified or the first number of initial sets of packets is equal to a first predefined number.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 13, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Mohammadreza Alizadeh Attar, Thomas James Edsall, Sarang Dharmapurikar
  • Patent number: 10157058
    Abstract: An adaptive self-configuring sensor node is disclosed herein. The node is associated with one or more sensor, and can include a microcontroller unit (MCU), sensors and a wired/wireless communication module (e.g., transceiver) to communicate the data collected by the sensors. Sensor node software running on the CPU can be adaptively reconfigured based on the sensors connected with the node, and using configuration data that is read from a non-volatile memory (NVM). The NVM can further store loadable sensor device specific data acquisition and processing (DAP) routines corresponding to one or more of the sensors, which can be executed to configure a sensor or cause collection or processing of sensor data.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 18, 2018
    Assignee: Analog Devices Global
    Inventors: Shankar S. Malladi, Nagarjuna Gandrothu, Subbarao Chennu
  • Patent number: 10110493
    Abstract: Emulating a NIC for packet transmission on hardware RSS unaware NICs in a multi-core system enables each of a plurality of slave packet engines to emulate a NIC for packet transmissions locally even though the actual NIC transmissions from the queue are handled by a master packet engine only. Each slave packet engine treats a local software-implemented transmission queue as a device queue and uses the local queue to keep track of status of data from the packet engine in the device output queue, handled by the master packet engine on behalf of the slave packet engines. As the master packet engine transmits the data from the queue and the status of the queue changes, the master packet engine and the slave packet engines may use pointers to keep track of which data packets are transmitted, which data packets are drained and which data packets are still in the queue.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 23, 2018
    Assignee: CITRIX SYSTEMS, INC.
    Inventors: Ramanjaneyulu Talla, Narendra Kumar Kataria
  • Patent number: 9906460
    Abstract: The present disclosure generally discloses a data plane configured for processing function scalability. The processing functions for which scalability is supported may include charging functions, monitoring functions, security functions, or the like.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Randeep S. Bhatia, Fang Hao, Tirunell V. Lakshman, Harish Viswanathan
  • Patent number: 9900902
    Abstract: Embodiments herein relate to method in a wireless device (10) for handling data transmissions in a radio communications network (1). The wireless device (10) is served by a first radio base station (12) and a second radio base station (13) providing dual connectivity to the wireless device (10) in the radio communications network (1). The wireless device (10) evaluates whether a trigger condition for buffer status reporting is fulfilled. When the trigger condition is fulfilled, the wireless device (10) transmits a buffer status report to the first radio base station and/or the second radio base station.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 20, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Riikka Susitaival, Fredrik Gunnarsson, Niklas Johansson, Magnus Stattin, Stefan Wager
  • Patent number: 9871674
    Abstract: Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew R. Ranck, Mushfiq U. Saleheen, Jie Zheng
  • Patent number: 9864604
    Abstract: Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 9, 2018
    Assignee: Oracle International Corporation
    Inventor: Ali Vahidsafa
  • Patent number: 9804666
    Abstract: Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yang Jiao
  • Patent number: 9805259
    Abstract: A method for making available measuring data of a value-document processing apparatus for processing value documents includes feeding individual value documents in real time, measuring data for the value documents are captured by means of a sensor device and stored in an intermediate memory, such that feeding of individual value documents and/or the capturing of measuring data the current utilization of the intermediate memory is compared to a predetermined limit utilization, dependent on the comparison. The feeding of value documents is interrupted and measuring data from the intermediate memory are permanently stored in a permanent memory, and during the permanent storing and/or after the permanent storing of the measuring data in the permanent memory the intermediate memory is released again. After release of the intermediate memory the feeding of individual value documents and capturing and storing of measuring data for the fed value documents in the intermediate memory is restarted.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 31, 2017
    Assignee: GIESECKE+DEVRIENT CURRENCY TECHNOLOGY GMBH
    Inventors: Matthias Hecht, Klaus Vrana, Karl-Dieter Forster
  • Patent number: 9779015
    Abstract: In response to receiving a write request directed to a particular logical block of a storage object, a page of free space (sufficient to accommodate the payload of the write request, but smaller in size than the logical block) of a particular extent that has been selected to store contents of the logical block is allocated. The current size of the extent is smaller than the combined sizes of logical blocks that are mapped to the extent. The page is modified in accordance with a payload indicated in the write request. In response to a subsequent write request directed to the particular extent, a determination is made that the particular extent would violate a free space threshold criterion if the payload of the write request were accommodated, and an extent expansion operation is initiated.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 3, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Matti Juhani Oikarinen, Pradeep Vincent, Matteo Frigo
  • Patent number: 9684460
    Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 20, 2017
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Feng Wang, Ethan Miller, Craig Harmer
  • Patent number: 9684459
    Abstract: According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Kondo, Yu Nakanishi, Akihiko Fukui
  • Patent number: 9594396
    Abstract: A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: March 14, 2017
    Assignee: Cray UK Limited
    Inventors: Edward James Turner, Jon Beecroft
  • Patent number: 9501221
    Abstract: According to one embodiment, a method for dynamically changing a buffer threshold in a tape drive includes determining that a drive buffer is emptied of data, calculating a write size indicating an amount of data from a transaction size left to be written to a tape prior to a next anticipated sync command, setting a buffer threshold that triggers a back hitch to a smaller value when the transaction size is less than a buffer size, setting the buffer threshold to the smaller value when an absolute difference between the transaction size and the write size is greater than or equal to the buffer size, and setting the buffer threshold to a larger value when the transaction size is not less than the buffer size and/or the absolute difference between the transaction size and the write size is less than the buffer size.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Fry, James M. Karp, Takashi Katagiri
  • Patent number: 9495169
    Abstract: A program trace data compression mechanism in which execution of a variable length execution set (VLES) including multiple non-branch conditional instructions are traced in real-time in a manner that allows the instruction execution to be reconstructed completely by correlating the trace data with the traced binary code.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 15, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Robert N. Ehrlich, Petru Lauric, Robert A. McGowan
  • Patent number: 9478272
    Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array and a control circuit. The configurable storage block may receive a mode selection command. The control circuit may determine to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order based on the mode selection command. Thus, the configurable storage block may implement first-in first-cut modules or last-in first-out modules and variations thereof in addition to implementing memory modules with random access.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 25, 2016
    Assignee: Altera Corporation
    Inventors: Richard Arthur Grenier, Michael David Hutton
  • Patent number: 9436595
    Abstract: A data storage device includes a plurality of flash memory devices. A memory controller is configured to receive a request from a host computing device to write a first logical block of application data to the data storage device, write the first logical block to a data buffer, wherein a size of the data buffer is larger than the logical block and may store multiple logical blocks, write one or more logical blocks of garbage-collected data to the data buffer, and write the logical blocks in the data buffer to the data storage device when the data buffer becomes full. The data buffer written to the data storage device includes at least one logical block of application data and at least one logical block of garbage-collected data. In an alternative implementation, garbage-collected data may be written to the data buffer upon expiration of a timer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 6, 2016
    Assignee: Google Inc.
    Inventors: Manuel Enrique Benitez, Monish Shah
  • Patent number: 9412409
    Abstract: Provided are a storage device, method, and program for controlling a tape speed to manage a tape drive buffer. A tape speed is increased from a current tape speed to a target tape speed on a predetermined speed-change timing to control the reading or writing of data between the buffer and the tape medium.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Atsush Abe, Takashi Katagiri, Hironobu Nagura, Yutaka Oishi
  • Patent number: 9348676
    Abstract: A processor has access to processing units for performing data processing and to libraries. Functions in the libraries are implementable to perform parallel processing and graphics processing. The processor may be configured to acquire (e.g., to download from a web server) a download script, possibly with extensions specifying bindings to library functions. Running the script may cause the processor to create, for each processing unit, contexts in which functions may be run, and to run, on the processing units and within a respective context, a portion of the download script. Running the script may also cause the processor to create, for a processing unit, a memory object, transfer data into that memory object, and transfer data back to the processor in such a way that a memory address of the data in the memory object is not returned to the processor.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: May 24, 2016
    Assignee: Google Technology Holdings LLC
    Inventor: Mikael L. Bourges-Sevenier
  • Patent number: 9137149
    Abstract: A system and method for routing data is provided. The system includes a communication interface, a FIFO and a processor module. The communication interface may transmit or receive data. The FIFO is operable to buffer data that has been received by the communication interface. The FIFO is also operable to buffer data that will be transmitted from the communication interface. The processor module is connected to the FIFO and is operable to monitor for data, decode a route according to the data, and move data according to the route and the amount of data in the FIFO.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: September 15, 2015
    Assignee: EMULEX CORPORATION
    Inventor: Stuart B. Berman
  • Patent number: 9122425
    Abstract: A distance calculating unit calculates a distance from a current position on a tape to the end of the tape. A command processing unit receives a write command. If the distance is small, a determining unit sets a usable capacity of a buffer to be equal to a maximum capacity of the buffer. If the distance is large, the determining unit sets the usable capacity of the buffer according to the distance. If a capacity for data indicated by the write command is less than or equal to a difference between the usable capacity and current usage of the buffer, a buffer managing unit stores the data in the buffer. When the command processing unit receives a write FM command, the buffer managing unit reads the data from the buffer, updates the current usage, and a channel input/output unit writes the data to the tape.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventor: Yutaka Oishi
  • Patent number: 9111039
    Abstract: The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 18, 2015
    Assignee: APPLE II 'C.
    Inventor: Michael W. Murphy
  • Patent number: 9037804
    Abstract: Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored in a cache line. If the field indicating the size of the usable data in the cache line indicates a size less than the maximum storage size, a value may be assigned to a field in the cache line indicating which subset of the data in the field to store data is usable data. A cache request may determine whether the size of the usable data in a cache line is equal to the maximum data storage size. If the size of the usable data in the cache line is equal to the maximum data storage size the entire stored data in the cache line may be returned.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Simon C. Steely, Jr., William C. Hasenplaugh, Joel S. Emer
  • Patent number: 9032114
    Abstract: The invention relates to an access controller which comprises a module (24) for managing writing in a circular buffer (16), means (38) for storing a first read pointer (PL) and a second write pointer (PE), a module (30) for managing reading in the circular buffer (16), means (24, 30, 40) for blocking reading, respectively writing, means (38) for storing a read or write work pointer (PT) which is different from the first and second pointers (PL; PE), and means (24, 30, 40) for updating the wo: pointer (PT) according to a predetermined update logic. The predetermined update logic comprises forward or backward movements of the work pointer (PT) inside the circular buffer (16), and the controller includes means for blocking the read or write work pointer if the read work pointer (PT) points outside a memory space reserved for reading or, respectively, if the write work pointer (PT) points outside a free memory space for writing.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: May 12, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Yves Durand, Christian Bernard
  • Patent number: 9032121
    Abstract: The invention is a method of analyzing the wear of a non volatile memory embedded in a secure electronic token. A set of events are intended to generate writing and/or erasing operations in said memory. The token comprises a buffer. The method comprises the following steps: each time an event belonging to said set occurs, generating a data which reflects the event and storing said data in the buffer, sending the buffer to a remote machine, analyzing the buffer to determine the wear of the memory.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: May 12, 2015
    Assignee: Gemalto SA
    Inventors: Frédéric Dao, Thierry Silvestre, Frédéric Faure
  • Patent number: 9019957
    Abstract: The present invention includes a network telephone having a microphone coupled to provide voice data to a network, a speaker coupled to facilitate listening to voice data from the network, a dialing device coupled to facilitate routing of voice data upon the network, a first port configured to facilitate communication with a first network device, a second port configured to facilitate communication with a second network device and a prioritization circuit coupled to apply prioritization to voice data provided by the microphone.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: April 28, 2015
    Assignee: Broadcom Corporation
    Inventors: Theodore F. Rabenko, Ian Crayford, David L. Hartman, Jr.
  • Patent number: 9015375
    Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 21, 2015
    Assignee: SIGMATEL, Inc.
    Inventors: Roderick Holley, II, Raymond L. Vargas, John Gregory Ferrara
  • Patent number: 9009363
    Abstract: A method for indicating an overload condition of a data storage system, comprises the steps of: defining one or more load indexes, wherein each of the load indexes has an overload threshold; and if one of the load indexes has met its respective overload threshold, providing an indicator of the overload condition of the storage system, else, monitoring the load indexes.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: April 14, 2015
    Assignee: Rasilient Systems, Inc.
    Inventors: Yee-Hsiang Sean Chang, Yiqiang Ding, John S. Hoch
  • Patent number: 8995509
    Abstract: Systems and methods are provided to enable a near-end receiver to control the far-end transmitter's data transmission such that the near-end receiver's TC data buffers do not overflow. In an embodiment, a high waterline and low waterline implemented into a near-end receiver are used to determine when the near-end receiver's TC data buffers are near maximum capacity. In an embodiment, the near-end receiver transmits a Packet Transfer Mode (PTM) All Idle Out Of Sync (AIOOS) codeword to the far-end transmitter when the high waterline is reached, and the near-end receiver stops transmitting the AIOOS codeword when the low waterline is reached.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 31, 2015
    Assignee: Broadcom Corporation
    Inventor: Philip Desjardins
  • Patent number: 8990439
    Abstract: A computer program product is provided for performing an input/output (I/O) operation at a host computer system configured for communication with a control unit. The computer program product is configured to perform: sending a transport mode command message from a channel subsystem to the control unit, the command message including a command for data to be transferred to an I/O device controlled by the control unit; and sending a data transfer message to the control unit, the data transfer message having an amount of the data to be transferred, the amount of the data being less than or equal to a maximum amount of data, the maximum amount of data corresponding to a number of buffers associated with the control unit and a size of each of the number of buffers, the number and the size indicated by a value maintained in the host computer system.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Carlson, Daniel F. Casper, John R. Flanagan, Roger G. Hathorn, Matthew J. Kalos, Louis W. Ricci, Gustav E. Sittman, III
  • Patent number: 8972630
    Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 3, 2015
    Assignee: Netronome Systems, Incorporated
    Inventor: Gavin J. Stark
  • Patent number: 8966168
    Abstract: An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro Hanafusa
  • Patent number: 8959266
    Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant V. Nori
  • Publication number: 20150039790
    Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Inventors: Nadav Bonen, Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant V. Nori
  • Patent number: 8949491
    Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Gary Lin, Robert Jackson, Yoav Weinberg, William L. Guthrie, Girish B. Desai
  • Patent number: 8930664
    Abstract: Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Ari Tapani Kulmala, Jaakko Illmari Sertamo
  • Publication number: 20150006770
    Abstract: Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 1, 2015
    Inventors: Evgeny Shumsky, Jonathan Kushnir
  • Patent number: 8924596
    Abstract: A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more processing elements. When a processing element reads the “reservation” register, the hardware automatically decrements the available free space by a preconfigured amount (e.g., 1) and returns the value of the free space immediately prior to the read/reservation. If the read returns 0 (or a number less than the preconfigured amount), there was insufficient free space to satisfy the request. In the event there was insufficient space to satisfy the request the reservation register may be configured to reserve however much space was available or to not reserve any space at all. Any number of processing elements may read these registers and various scenarios are described where the input and output queues are accessible via various processing elements.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: December 30, 2014
    Assignee: Concurrent Ventures, LLC
    Inventors: Jesse D. Beeson, Jesse B. Yates
  • Patent number: 8918563
    Abstract: A technique for uplink data throttling includes buffer status report (BSR) scaling. A target data flow rate may be determined based on at least on condition of a wireless device. The buffer status report may be adjusted to cause the target flow rate and transmitted by the wireless device. The wireless device may then receive a flow control command based on the buffer status report.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: December 23, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Navid Ehsan, Thomas Klingenbrunn, Shailesh Maheshwari, Bao Vinh Nguyen, Gang Andy Xiao, Jon J. Anderson
  • Patent number: 8914562
    Abstract: A method, apparatus and computer program product are provided herein to enable buffer initialization and/or clearance to occur on, for example, a mobile terminal. In some example embodiments, a method is provided that comprises receiving an indication that a buffer has been initialized by a host. The method of this embodiment may also include receiving source code from the host. In some example embodiments, the source code is received from a program running on the host and is configured to cause the buffer that has been initialized by the host to be cleared. The method of this embodiment may also include executing the source code such that the buffer that has been initialized by the host is cleared.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: December 16, 2014
    Assignee: Nokia Corporation
    Inventors: Eero Aho, Tomi Aarnio, Kimmo Kuusilinna
  • Patent number: 8904069
    Abstract: A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: December 2, 2014
    Assignee: Olympus Corporation
    Inventors: Yoshinobu Tanaka, Keisuke Nakazono, Akira Ueno, Hideaki Furukawa
  • Patent number: 8904068
    Abstract: One embodiment sets forth a technique for dynamically allocating memory during multi-threaded program execution for a coprocessor that does not support dynamic memory allocation, memory paging, or memory swapping. The coprocessor allocates an amount of memory to a program as a put buffer before execution of the program begins. If, during execution of the program by the coprocessor, a request presented by a thread to store data in the put buffer cannot be satisfied because the put buffer is full, the thread notifies a worker thread. The worker thread processes a notification generated by the thread by dynamically allocating a swap buffer within a memory that cannot be accessed by the coprocessor. The worker thread then pages the put buffer into the swap buffer during execution of the program to empty the put buffer, thereby enabling threads executing on the coprocessor to dynamically receive memory allocations during execution of the program.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 2, 2014
    Assignee: NVIDIA Corporation
    Inventors: Luke Durant, Ze Long
  • Patent number: 8904067
    Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Microsoft Corporation
    Inventor: Erwien Saputra
  • Patent number: 8893146
    Abstract: A method and system of a host device hosting multiple workloads for controlling flows of I/O requests directed to a storage device is disclosed. In one embodiment, a type of a response from the storage device reacting to an I/O request issued by an I/O stack layer of the host device is determined. Then, a workload associated with the I/O request is identified among the multiple workloads based on the response to the I/O request. Further, a maximum queue depth assigned to the workload is adjusted based on the type of the response, where the maximum queue depth is a maximum number of I/O requests from the workload which are concurrently issuable by the I/O stack layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kishore Kumar Muppirala, Narayanan Ananthakrishnan Nellayi, Sumanesh Samanta
  • Patent number: 8886845
    Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 11, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Michel F. Fisher, Humberto Rodriguez
  • Patent number: 8874809
    Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 28, 2014
    Assignee: Napatech A/S
    Inventor: Peter Korger
  • Patent number: 8862796
    Abstract: Configurations providing a configurable buffer for storing incoming event tracking data communications in a lossy manner are described. In one aspect, a server can utilize the configurable buffer for storing the incoming event tracking data communications. When the buffer becomes full, the server can transmit the accumulated tracking data communications in the configuration buffer as a batch transmission. The server can discard any new incoming requests once the buffer becomes full. Further, the server can replace data in the buffer with new incoming requests based on one or more criterion if the buffer is full. In some implementations, the server transmits the batch of the accumulated tracking data communications in the configurable buffer after a predetermined time has elapsed.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: October 14, 2014
    Assignee: Google Inc.
    Inventors: James Lee Wogulis, Mayur Venktesh Deshpande, Jacob Burton Matthews, Kasem Marifet
  • Patent number: 8862904
    Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology using distributed management and wherein the network adapter is configured to share a plurality of shared hardware components by automatically turning all other comms to OFF when one comm is turned to ON.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Boris Ginzburg, Sharon Ben-Porath, Oren Kaidar, Shlomo Avital, Avishay Sharaga, Max Fudim, Eran Friedlander
  • Patent number: 8862797
    Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: October 14, 2014
    Assignee: Cortina Systems, Inc.
    Inventors: Dennis Albert Doidge, Juan-Carlos Calderon, Jean-Michel Caia