Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.

Abstract: A content reproduction method is provided, which acquires, from a data transmission apparatus, first streaming data that is used to play a content at a first speed, and records the first streaming data on a storage medium. The content reproduction method plays the content at the first speed, based on the stored first streaming data. The content reproduction method also starts acquisition of second streaming data in response to a varied-speed reproduction request for the content, wherein the second streaming data is used to play the content at a second speed, and plays the content at a transition speed based on the stored first streaming data, in response to the varied-speed reproduction request. The content reproduction method plays the content at the second speed based on the second streaming data, after the acquisition of the second streaming data progresses to a reproduction preparation complete state.

Abstract: A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.

Abstract: Described are techniques for managing a wait queue in a system. A plurality of buckets associated with the wait queue are defined. Each of the plurality of buckets is associated with one of more queue depth values and one or more counters. For each received request for service, a current depth of the wait queue indicating a number of other requests included in the wait queue waiting to be serviced is determined, a bucket in accordance with the current depth of the wait queue is selected and information is recorded by updating said one or more counters of the bucket selected. The received request is placed in the wait queue if there is another request currently being serviced or if there is at least one other request currently in the wait queue.

Abstract: In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first predefined threshold, then the read request is temporarily restricted from being forwarded upstream.

Abstract: Systems and methods for intermediate buffering of data for the purpose of controlling its delivery to the consumer. The systems and methods for buffering data can arbitrate between the incoming data flow from the generating component and the outgoing data flow to the consumer. In doing so, the systems and methods for buffering of data seek to honor the delivery demands and/or constraints of the consumer, while avoiding the loss of the data generated by the producer. The delivery demands of the consumer may include requirements pertaining to maximum acceptable incoming data rate, the desired incoming data rate, incoming data aggregation, the desired freshness of the data, and tolerance for event loss. The generation component constraints may include the space limitations on buffering data within the data buffer.

Abstract: A method for operating a storage system, including storing data redundantly in the system and measuring respective queue lengths of input/output requests to operational elements of the system. The queue lengths are compared to an average queue length to determine respective performances of the operational elements of the storage system. In response to the average queue lengths and a permitted deviation from the average an under-performing operational element among the operational elements is identified. An indication of the under-performing operational element is provided to host interfaces in the storage system. One of the host interfaces receives requests for specified items of the data directed to the under-performing element, and in response to the indication, some of the requests are diverted from the under-performing operational element to one or more other operational elements of the storage system that are configured to provide the specified items of the data.

Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction timing component including code to implement an eviction timing method, and the eviction timing method to trigger eviction of an object from the region of cache. The sorting component includes code to implement a sorting method to identify an object that is eligible for eviction from said region of cache. The sorting method includes identifying an object for eviction that is cached in the region of cache and that has been used least recently compared to other objects that are cached in the region of cache.

Abstract: Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed.

Abstract: A remote copy method for copying data within a first storage apparatus to a second storage apparatus via a network, includes transmitting data from the first storage apparatus in units of first buffer sets each formed by a plurality of first recording exclusive buffers within the first storage apparatus, and receiving the data by the second storage apparatus in units of second buffer sets each formed by a plurality of second recording exclusive buffers within the second storage apparatus, so as to maintain a sequence guarantee with respect to the data that is copied.

Abstract: A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.

Abstract: A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to extract the packet from the data frame. A buffer has a plurality of memory locations to store the packet in a FIFO configuration. A buffer manager, in response to detecting a buffer low packet condition, stalls reads of the packet from the buffer.

Abstract: Resources allocated to a group of ports include a plurality of storage regions. Each storage region includes a committed area and a shared area. A destination storage region is identified for a packet. A packet queuing engine stores the packet in the committed area of the determined destination storage region if it has a first drop precedence value, and if available storage space in the committed area exceeds a first threshold. The packet queuing engine stores the packet in the shared area of the determined destination storage region if the packet is not stored in the committed area, and if available storage space exceeds a second threshold defined by the packet's drop precedence value. If the packet is not stored either in the committed or shared area, it may be dropped.

Abstract: A recording device is connectable to a host computer and performs recording on the basis of received data including commands, received from the host computer. A receiving buffer stores therein the received data received from the host computer. A command detection section reads the received data stored in the receiving buffer while scanning the receiving buffer with a first read pointer to detect the commands included in the received data. A command execution section processes the commands detected by the command detection section in a stored order of the commands in the receiving buffer. An immediate processing command detection section reads the received data stored in the receiving buffer while scanning the receiving buffer with a second read pointer which is provided separately from the first read pointer to detect an immediate processing command included in the received data.

Abstract: In one embodiment a storage controller comprises a processor, a computer readable storage medium coupled to the processor, and logic instructions in the memory module which, when executed by the processor, configure the processor to receive, in a quality of service module, a first command request from a host initiator port, associate a time-out threshold with the first command request, determine, in the quality of service module, whether an available priority queue can release the first command request for execution by a scheduling module within the time-out threshold; and in response to a determination that an available priority queue can release the first command request for execution within the time-out threshold, assign the first command request to the available priority queue.

Abstract: A method of encoding a digital image signal comprising a plurality of samples. The method comprises the following steps, applied during the encoding of each sample with a view to its storage in a buffer. The level of occupancy of the buffer is determined, and the level of occupancy is compared with a predetermined threshold. An encoding mode is determined from among a plurality of encoding modes when the level of occupancy is above the predetermined threshold, and encoding the sample according to the determined encoding mode, and the sample is encoded according to a default encoding mode when the level of occupancy is below the predetermined threshold.

Abstract: Visualization for active execution tracing pertains to one or more tools used to capture and analyze events leading to a point-of-failure during execution of a function or at least a portion of an application, program, process, or other assemblage of programmable and executable code.

Abstract: Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base address, at least one address pointer and a size to define a corresponding one of the plurality of buffers. Transferring data in any one of the plurality of buffers by using a control function within an accessing module to generate a buffer address by accessing and updating the address pointer in the corresponding descriptor. In a processor that accesses the circular buffers, the control function is one or more complex instructions tailored for computing read and write addresses to access the circular buffer using fields within the corresponding descriptor. In a DMA module that accesses the circular buffers, the control function is a hardware controller that computes read and write addresses using the fields within the corresponding descriptor to access the circular buffer.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: An application may issue write operations intended for a SAN via a server cache. Monitoring of the SAN (e.g., the autonomous persistent cache of the storage arrays of the SAN), allows caching performance to be controlled by a write caching policy. The server cache memory may be increased, decreased or eliminated according to the write caching policy. In one embodiment, a storage volume manager may adjust the latency of write operations in the server cache. In some embodiments, the write caching policy may adapt and learn characteristics of the storage environment, which may include calibrated values for messaging timestamps.

Abstract: The present invention discloses a method of editing a multi-media playing schedule for a digital photo frame, a system and a computer readable storage medium thereof, which are characterized in that users can edit a multi-media playing schedule on the data processing apparatus when the digital photo frame is electrically connected to the data processing apparatus, and after editing of the multi-media playing schedule is finished, the multi-media playing schedule is transmitted to the digital photo frame and stored in the digital photo frame. Therefore, the problem of being unable to edit complicated multi-media playing schedules due to simple operation interface of digital photo frames can be solved.

Abstract: In one embodiment, a method of managing critical resource usage in a storage network comprises receiving, in a storage controller, an input/output operation from a host, wherein the input/output operation identifies a storage unit, placing the input/output operation in a waiting queue, determining a maximum queue depth for at least one critical resource in the storage network required to execute the input/output command against the storage unit, and blocking one or more subsequent input/output commands from the host for the storage unit when the wait queue for the critical resource exceeds the maximum queue depth.

Abstract: In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to track the total number of transmission words in the FIFO array. A dynamic threshold controller tracks transmission word insertions and deletions in the FIFO array for a predetermined period of time and provides a threshold level adjustment signal based on the tracked transmission word insertions and deletions and a transmission word threshold level. A FIFO level adjuster provides transmission word insert and delete commands and adjusts the threshold level of the FIFO array in response to the threshold level adjustment signal.

Abstract: A multimedia data processing apparatus with reduced buffer size includes an accessing unit and a data processing module. The accessing unit has a plurality of buffers therein. The data processing module includes a processing unit and a real-time buffer. The processing unit processes the data temporarily stored in the accessing unit and the real-time buffer. By adding the real-time buffer, the size of the buffer in the accessing unit and the maximum bandwidth requirement can be reduced thereby increasing the system performance.

Abstract: A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: Disclosed is a method of processing a read/write request conforming to the PLB bus protocol and a bus bridge from PLB bus to AXI bus, the method comprising: receiving the read/write request conforming to the PLB bus protocol without waiting for an acknowledgement of successful execution of a previous read/write request conforming to the PLB bus protocol; buffering the read/write request conforming to the PLB bus protocol; mapping the buffered read/write request conforming to the PLB bus protocol to a read/write request conforming to a AXI bus protocol; and outputting the mapped read/write request conforming to the AXI bus protocol. The method and the bus bridge enable IP modules conforming to PLB bus protocol and AXI bus protocol to communicate and perform transaction mapping during communication, to guarantee that all the transactions are performed in an order desired by the PLB device, and improve communication efficiency of the SoC.

Abstract: The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memory for storing m input valid bits corresponding to the m data elements. Input control logic circuitry generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.

Abstract: An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.

Abstract: A system for providing dynamic queue splitting to maximize throughput of queue entry processing while maintaining the order of queued operations on a per-destination basis. Multiple queues are dynamically created by splitting heavily loaded queues in two. As queues become dormant, they are re-combined. Queue splitting is initiated in response to a trigger condition, such as a queue exceeding a threshold length. When multiple queues are used, the queue in which to place a given operation is determined based on the destination for that operation. Each queue in the queue tree created by the disclosed system can store entries containing operations for multiple destinations, but the operations for a given destination are all always stored within the same queue. The queue into which an operation is to be stored may be determined as a function of the name of the operation destination.

Abstract: The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Abstract: A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of a certain information frame from a certain buffer occurs; if an under-run occurs, requesting a certain information frame transmitter to transmit predefined packets while ignoring packets that are retrieved from the certain buffer, until a last packet of the information frame is retrieved from the certain buffer; and notifying a processor that an under-run occurred after at least one predefined packet was transmitted; wherein each buffer out of the multiple buffers is adapted to store a fraction of a maximal sized information frame.

Abstract: A system manages a buffer having a group of entries. The system receives information relating to a read request for a memory. The system determines whether an entry in the buffer contains valid information. If the entry is determined to contain valid information, the system transmits the information in the entry in an error message. The system may then store the received information in the entry. In another implementation, the system stores data in one of the entries of the buffer, removes an address corresponding to the one entry from an address list, and starts a timer associated with the one entry. The system also determines whether the timer has exceeded a predetermined value, transferring the data from the one entry when the timer has exceeded the predetermined value, and adds the address back to the address list.

Abstract: Expedited digital signal decoding. A multicast or unicast data stream is sent from a headend to a set-top box at a natural rate. A decoder buffer in the set-top box begins to fill. Once the buffer is partially full, a decoder begins to decode the data at a rate lower than the natural rate. Images are displayed to the user before the buffer is full, allowing for a faster channel change.

Abstract: Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed.

Abstract: There is provided a system and method of controlling transaction flow in a communications interface. An exemplary system comprises a first buffer configured to hold packets of a first packet type, and a second buffer configured to hold packets of a second packet type. An exemplary system also comprises a counter configured to track a delay-reference of packets held in the second buffer. An exemplary system also comprises a controller configured to receive packets from a host and send packets of the first packet type to the first buffer and to send packets of the second packet type to the second buffer, the controller being further configured to stop receiving packets if the delay-reference meets or exceeds a specified threshold.

Abstract: A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

Abstract: An information processing apparatus includes a processing unit and a control unit connected with the processing unit through a transmission line. The processing unit has multiple devices including a predetermined low-speed device. The control unit has a processing circuit that issues access to the multiple devices of the processing unit, and the processing unit has a communication circuit that receives the access to the multiple devices through the transmission line and a queue that buffers the access, when the received access is to the predetermined low-speed device.

Abstract: The invention relates to packet tracing in computer networks. Data packets are captured when entering or exiting the network or at any point within the network protocol stack. Buffers in computer kernel space memory store the packets until the contents of the buffers are written to persistent memory. Each buffer holds one or more data packets and the contents of a buffer are written to persistent memory when a status flag associated with the buffer indicates that it may hold no further packets. Data packets may be continuously captured, or capture may be initiated and/or terminated in response to a special event.

Abstract: Management of requests from a host to an external storage medium. An execution queue stores commands to be executed, and each command corresponds to a request from the host for data. A holding queue stores executed commands until receipt of an acknowledgment from the host that the host has, e.g., received the data corresponding to the command from the external storage medium. An outgoing queue stores acknowledged commands and has a maximum storage limit. A counter is provided, and a separate logic block increments the counter when a command is stored in the execution queue and decrements the counter when an acknowledged command is deleted from the outgoing queue. The separate logic disables execution of commands stored in the execution queue when the value of the counter equals the maximum storage limit of the outgoing queue.

Abstract: A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of the data region is updated. Finally, the count value and a value of maximum data length are compared to determine whether to increase the number of the packets that can be stored in the buffer.

Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

Abstract: Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.

Abstract: A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the flush request and outputs a flush acknowledgement signal to the first master device in response of that a buffer read pointer of the buffering unit is identical to the recorded buffer write pointer.

Abstract: A bridge capable of preventing data inconsistency without degrading system performance is provided, in which a buffering unit comprises a plurality of buffers, a first master device outputs a flush request to flush the buffering unit, and a flush request control circuit records the flushed buffer(s) in the buffering unit when receiving the flush request and outputs a flush acknowledge signal to indicate to the first master device that the buffering unit has been flushed when all the plurality of buffers have been flushed once after the flush request has been received.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of non-contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of non-contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: A transmission systems suitable for video.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity.