Abstract: A data input/output device includes a buffer that accumulates data, and a data receiver that receives data input in synchronization with a first clock in accordance with a second clock whose generation source is different from a generation source of the first clock. The data input/output device further includes a data input part that accumulates data received by the data receiver in the buffer, and a data output part that sequentially outputs data accumulated in the buffer at an output interval depending on the amount of data accumulated in the buffer in such a manner that a predetermined data amount is the unit of the output.

Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.

Abstract: An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses counted by the hardware counter with at least one predetermined threshold value, the hardware comparator further to generate a control signal, the control signal being dependent on a result of a comparison of a number of write accesses counted by the hardware counter with at least one predetermined threshold value performed by the hardware comparator, and a clock frequency setting circuit to set a clock frequency of a processor depending on the control signal.

Abstract: The disclosed embodiments provide a synchronization circuit that supports multiple parallel reads and writes. This synchronization circuit includes multiple coupled data storage locations that synchronize data and control signals between two time domains and control logic that facilitates simultaneously accessing a variable number of such data storage locations in the same clock cycle. During operation, the synchronization circuit receives a request to simultaneously access (e.g., read and/or write) two or more synchronized data storage locations. In response to the request, the control logic in the synchronization circuit determines whether the present state of the synchronization circuit can accommodate the request, and if so, simultaneously accesses two or more synchronized data storage locations.

Abstract: A method, computer program product, and computing system for receiving, on a cache system, a plurality of data write requests, wherein each data write request identifies a data portion to be written to a data array associated with the cache system. The data portions associated with the data write requests are written to the cache system. The data portions associated with the data write requests are queued until the occurrence of a commit event. Upon the occurrence of the commit event, a consolidated write operation is performed to write the data portions associated with the data write requests to the data array.

Abstract: A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

Abstract: A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

Abstract: Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.

Abstract: In an image processing apparatus, an image memory handler (IMH) sets an engine descriptor for an engine unit and a virtual descriptor for a virtual video input driver, thereby controlling moving of image data from a local memory (MEM) to a hard disk drive (HDD). In a process in which the engine unit writes the image data into the MEM in such a manner defined by settings described in the engine descriptor, the virtual video input driver handles occurrence of an interrupt to a PCI direct access in such a manner that the image data is moved from the MEM to the HDD properly.

Abstract: A data communication control device. The data communication control device includes, a controller comprising a first data storing part, the first data storing part including multiple channels, each channel being applied to store a command for data transfer based on a destination of data, the controller executing the command stored in the channel from the head to transfer data and, an overall controller storing the command in the channel of the first data storing part when the number of commands in a certain channel is not over a upper limit, and stopping to store the command in the channel of the first data storing part and creating a second data storing part and storing the command in the second data storing part when the number of commands in a certain channel is over the upper limit.

Abstract: Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

Abstract: A recording device is connectable to a host computer and performs recording on the basis of received data including commands, received from the host computer. A receiving buffer stores therein the received data received from the host computer. A command detection section reads the received data stored in the receiving buffer while scanning the receiving buffer with a first read pointer to detect the commands included in the received data. A command execution section processes the commands detected by the command detection section in a stored order of the commands in the receiving buffer. An immediate processing command detection section reads the received data stored in the receiving buffer while scanning the receiving buffer with a second read pointer which is provided separately from the first read pointer to detect an immediate processing command included in the received data.

Abstract: Systems and methods are provided to enable a near-end receiver to control the far-end transmitter's data transmission such that the near-end receiver's TC data buffers do not overflow. In an embodiment, a high waterline and low waterline implemented into a near-end receiver are used to determine when the near-end receiver's TC data buffers are near maximum capacity. In an embodiment, the near-end receiver transmits a Packet Transfer Mode (PTM) All Idle Out Of Sync (AIOOS) codeword to the far-end transmitter when the high waterline is reached, and the near-end receiver stops transmitting the AIOOS codeword when the low waterline is reached.

Abstract: A method for dynamic buffering of disk I/O command chains for a computer system. The method includes receiving a plurality of disk I/O command chains from at least one thread executing on a processor of the computer system. A respective plurality of pointers for the disk I/O command chains are stored in a buffer of a disk controller. The disk I/O command chains are accessed for execution by the disk controller by serially accessing the pointers in the buffer.

Abstract: A data writing apparatus includes a tape drive, a buffer and non-volatile memory. When a synchronization request is received from a device sending data to be written to a tape, the apparatus is operable to copy data corresponding to the synchronization request from the buffer to the non-volatile memory. The data may be stored in the non-volatile memory until at least the time when the data which it is a copy of is written to the tape from the buffer.

Abstract: A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries.

Abstract: Disclosed herein is a method of accessing a slave device from a circuit including a central processing unit, a data transfer engine, and an interface to the slave device. In one embodiment, the method includes: executing code on the central processing unit to set up the data transfer engine to access the slave device; and based on the set-up, operating the data transfer engine to supply a read request word to a transmit buffer of the interface for transmission to the slave device, and, after return of a corresponding response word to a first-in-first-out receive buffer of the interface, to disable the first-in-first-out receive buffer from receiving any further data such that the last word therein is assured to be the response word. The method further includes using an underflow mechanism of the first-in-first-out receive buffer to determine the last word therein and hence determine the response word.

Abstract: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: A queue overflow prevention method and apparatus for Hard Disk Drive (HDD) protection in a computer system is provided. The queue overflow prevention method includes measuring acceleration information of the system, determining if the system is in a stable status or an unstable status using the acceleration information, and, while the system is in the unstable status, restricting the generation of a disk Input/Output (I/O) request.

Abstract: Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: A system for managing time-stamped events with uncertain events-sequence signalling, including a list of variables of which a change of value must lead to the detection of an event to be time-stamped and to be saved; means, for each variable, for positioning a marker indicating the quality of the time-stamping of said event; a buffer for the storage, before they are read by client software, of said events to be time-stamped and to be saved, associated respectively with a time-stamping time, said time-stamped events read by the client software being erased from the buffer; means for enabling and for disabling means for saving in a history the values of the variables corresponding to said time-stamped events that have been read.

Abstract: A controller for a storage device is connected to a host system and the storage device. A buffer memory includes first and second storage areas. A timer counts a preset given time in response to an instruction to start counting and sends a deadline notification when A given time is elapsed. A command responding portion, when receiving a read command from the host system, instructs the timer to start counting and thereafter outputs a read instruction to read data from the storage system. A data processing portion, in response to the read instruction by the command responding portion, reads specified data from the storage device and holds the read data in the second storage area of the buffer memory. A read control portion sends the host system the data held in the second storage area of the buffer memory when the deadline notification is received from the timer.

Abstract: An image scanning device includes a scanning unit configured to execute image scanning of a document and thereby generate image data, at least one processing unit configured to successively process the image data outputted from the scanning unit, a transmission unit configured to transmit the image data outputted from the processing unit, a storage unit, in which multiple buffer areas to be used for transferring the image data among the scanning unit, the at least one processing unit and the transmission unit are allocated, an acquisition unit configured to acquire information on usage status of each of the buffer areas, and a changing unit configured to change storage area allocation at least between two of the buffer areas based on the usage status acquired by the acquisition unit.

Abstract: A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity.

Abstract: Embodiments of the present invention provide a buffer manager and a buffer management method based on an address pointer linked list. In the embodiments, address pointers of all buffer blocks in a buffer are divided into several groups, lower bits of address pointers in each group are used to record a linked list between the address pointers in the same group, and an address pointer which is pointed by one predetermined address pointer of each group and is in a different group is further recorded to upbuild a linked list between the groups. Thereby, an address linked list can still be stored without a RAM with a width equal to a pointer depth and with a depth equal to the total number of buffer blocks in the buffer as required by the conventional art, which greatly reduces hardware resources required.

Abstract: A method, apparatus and computer program product are provided herein to enable buffer initialization and/or clearance to occur on, for example, a mobile terminal. In some example embodiments, a method is provided that comprises receiving an indication that a buffer has been initialized by a host. The method of this embodiment may also include receiving source code from the host. In some example embodiments, the source code is received from a program running on the host and is configured to cause the buffer that has been initialized by the host to be cleared. The method of this embodiment may also include executing the source code such that the buffer that has been initialized by the host is cleared.

Abstract: The wireless communication device of the present invention is provided with a received data FIFO for temporarily storing received data, and a data reading section for reading received data from the received data FIFO. The data reading section, when received data to be read is stored in the received data FIFO, reads and outputs the stored received data. Meanwhile, when the received data to be read is not stored in the received data FIFO and a predetermined condition is fulfilled, the data reading section outputs dummy received data. Furthermore, when the received data to be read is not stored in the received data FIFO and the predetermined condition is not fulfilled, the data reading section outputs an error.

Abstract: The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

Abstract: Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is done, it can move on to the second buffer and process signals stored therein while the incoming data module stores signals in the first buffer. Also provided is a flagging scheme for allowing the processor and the incoming data module to control their respective access to the various buffers, so that only one of them accesses a single buffer at any time.

Abstract: Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.

Abstract: The present invention provides a device for indicating status of hard disk. The device includes a SGPIO (Serial General Purpose Input/Output) input terminal, a serial-parallel converting unit, a buffer unit, and a status indicating unit. The serial-parallel converting unit is connected with the SGPIO input terminal and converts the serial signals into parallel signals. The buffer unit is connected with the serial-parallel converting unit and stores the parallel signals temporally. The status indicating unit is connected with the buffer unit and indicates the status of the at least one hard disk according to the parallel signals from the buffer unit.

Abstract: A method and apparatus for detecting a queue depth of a memory queue in a memory system is described. The method includes estimating a start position of the queue by examining a portion of a queue start identifier of the memory queue, estimating an end position of the queue by examining a portion of a queue end identifier of the memory queue, and utilizing the start position and the end position to estimate the queue depth of the memory queue. The apparatus applies the method. One embodiment of the method and apparatus may be suitable for implementation on look-up tables of field general programmable gate arrays.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.

Abstract: In one embodiment, a data storage device comprises a buffer, a buffer manager, and a buffer client. The buffer client is configured to receive data to be stored in the buffer, to compute a difference between a bank boundary address of the buffer and a starting buffer address for the data, to generate a first data burst having a length equal to the computed difference and including a first portion of the data, and to send the first data burst to the buffer manager, wherein the buffer manager is configured to write the first data burst to the buffer.

Abstract: A communication system includes a first communication device that transmits transmission data containing user data and control data, and a second communication device that receives the transmission data from the first communication device. The second communication device includes a temporary storing unit that temporarily stores therein the received transmission data, and a space-insufficient-information transmitting unit that transmits, when an amount of the transmission data stored in the temporary storing unit exceeds a first threshold, space insufficient information indicating that available storage space of the temporary storing unit is insufficient to the first communication device.

Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract: A data transfer apparatus includes a virtual channel unit configured to time share a serial bus for a first virtual channel and a second virtual channel and include a buffering control unit configured to receive data via the first virtual channel and the second virtual channel, first and second receive buffers being configured to store the data received via the first virtual channel and the second virtual channel, respectively; and a switching unit configured to control storing the data received via the first virtual channel in the second receive buffer when the buffering control unit receives the data from another data transfer apparatus which is configured to use only the first virtual channel and the capacity of the first receive buffer is smaller than that of the second receive buffer.

Abstract: An apparatus and a method for intelligent analysis of device compatibility and adaptive processing of multimedia data are disclosed. By performing a unique intelligent analysis of device compatibility, the present invention provides a full application-level compatibility between the apparatus performing the intelligent analysis and an external device operatively connected to the apparatus even when device driver-level information of the external device is unavailable. Furthermore, a unique intelligent analysis for adaptive processing of multimedia data between the apparatus and the external devices enables an efficient and flexible usage of storage space in the external device for a multimedia data transfer from the apparatus to the external device.

Abstract: A method according to one embodiment includes the operations of assigning a network application to at least one first core processing unit, from among a plurality of core processing unit. The method of this embodiment also includes the operations of assigning a first receive queue to said first core processing unit, wherein the first receive queue is configured to receive packet flow associated with the network application; defining a high threshold for the first receive queue; and monitoring the packet flow in the first receive queue and comparing a packet flow level in the first receive queue to the high threshold; wherein if the packet flow level exceeds the threshold based on the comparing, generating a queue status message indicating that the packet flow level in the first queue has exceeded the queue high threshold.

Abstract: There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.

Abstract: A data reception system includes a data acquisition unit acquiring data from a predetermined transmission path, an access control unit storing the data acquired by the data acquisition unit in a predetermined storage area, and a plurality of storage areas. The plurality of storage areas includes a first storage area and a second storage area having a greater storable capacity and a lower storing speed compared to the first storage area. The access control unit further includes a transfer unit. The access control unit determines whether the total amount of data stored in the first storage area is in the excess of a predetermined threshold or not and causes a transfer unit to transfer the data acquired by the data acquisition unit to the second storage area to store the data in the second storage area when the total amount is in the excess of the threshold.

Abstract: The invention is a method of analyzing the wear of a non volatile memory embedded in a secure electronic token. A set of events are intended to generate writing and/or erasing operations in said memory. The token comprises a buffer. The method comprises the following steps: each time an event belonging to said set occurs, generating a data which reflects the event and storing said data in the buffer, sending the buffer to a remote machine, analyzing the buffer to determine the wear of the memory.

Abstract: An elastic expert system for allocating bits according to application domain requirements and network resources. The elastic expert system observes the network resources and determines a state for allocating bits, the state relating to the application domain requirements. The elastic expert system can then allocate bits to a region-of-interest based on the determined state. The elastic expert system also can allocate bits to a background region and an extended region of interest.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: A method for determining an aging period for retaining a write-back data in a cache memory prior to writing the write-back data to a storage media is determined through use of a write-back aging routine. The aging period is based on a proportional utilization level of the cache memory by the write-back data, the higher the memory utilization level, the shorter the period for aging the write-back data. The aging period takes a form of an aging threshold, which differs depending on the memory utilization level, i.e., the amount of cache memory utilized by the write-back data. The method includes, identifying the memory utilization level, selecting the data aging threshold based on the memory utilization level; and writing the data from the cache memory to the storage media when an age of the data in the memory exceeds the selected data aging threshold.