Abstract: A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

Abstract: A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to extract the packet from the data frame. A buffer has a plurality of memory locations to store the packet in a FIFO configuration. A buffer manager, in response to detecting a buffer low packet condition, stalls reads of the packet from the buffer.

Abstract: A method according to one embodiment may include determining, at least in part, by an intermediate device at least one communication protocol via which at least one storage device connected to the intermediate device is capable of communicating. In this embodiment, the intermediate device may be capable of controlling, at least in part, by the intermediate device, at least one data stream coming from the at least one storage device in accordance with at least one communication protocol. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives an interrupt signal from an expansion device on the expansion bus and generates an indicator of completion. The processor then inserts the indicator into a transaction queue after the set of data.

Abstract: A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer 13 coupled to the first component 11; a second buffer 14 coupled to the second component 12; and a copy/access controller 15, 16, 17 connected to the first buffer 13, the second buffer 14, and the second component 12. The copy/access controller 15, 16, 17 is operable to copy data from the first buffer 13 to the second buffer 14 when the first buffer 13 is substantially full. It is also operable to prompt the second component 12 to access the second buffer 14 when the data is copied from the first buffer 13. The buffers can be random access memories or shift registers, and can be integrated onto the same semiconductor die as either the first or second component.

Abstract: Processing which, in conventional data transfer processing, entails the use of the common bus when performing (1) processing to confirm the interrupt state, performed via the common bus employing an interrupt register and interrupt mask register, and (2) confirmation processing performed when new frames are transferred during processing, can be performed without using the common bus. By thus reducing the frequency of access via the common bus in data transfer processing, there is no reduction in the usage ratio of the common bus by other peripheral device connected to the same common bus as certain peripheral device. As a result, the performance of the information processing terminal as a whole is not degraded. Further, even if there is currently only a single peripheral device unit connected to the common bus, degradation of the performance of the information processing terminal upon future addition of other peripheral device can be avoided.

Abstract: A method for transferring data in a storage system is provided. The method includes setting a catch-up threshold for accepting data requests from a port where the queue value corresponds to a number of requests collected from an input queue for every CPU interrupt, and the input queue receives requests from the port and stores the requests to be collected by a CPU. The method also includes adjusting the catch-up threshold to reduce an imbalance between the number of requests made to the input queue and a number of requests made to an output queue in a particular period of time where the output queue receives requests from the CPU and stores the requests to be gathered by the port.

Abstract: A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the register with the processor if the data in the register is valid, enabling an identifier register with the processor if the data in the register is invalid, transmitting an interrupt signal to the processor, disabling the identifier register with the processor, and accessing the data from the register with the processor.

Abstract: A method for calculating flow control credits includes determining a number of entries added to each of a pair of storage devices, determining a number of entries removed from each of the storage devices, calculating a difference between available space in the storage devices, and calculating a number of credits to release based on the numbers of entries added to each of the storage devices, on the numbers of entries removed from each of the storage devices, and on the difference in available space. Entries removed from one storage device are treated as an entry added to the other storage device.

Abstract: A method, apparatus, and computer-readable media for sending a frame of data from a first channel to a second channel using at least one of m memory buffers for storing a frame, m being at least 2, in which n of the m buffers have an available status and p of the m buffers have an unavailable status, wherein m=n+p comprises reserving to the first channel one or more of the n buffers having the available status when a number q of the buffers reserved to the first channel is less than a capacity r, wherein q?r; when a frame is received from the first channel, storing the frame in i of the q buffers and changing the status of the i buffers to unavailable, wherein 1?i?q; selectively assigning the frame to the second channel based on a number s of the q buffers, wherein s?q; wherein if the frame is assigned to the second channel, the frame is sent to the second channel from the i buffers and the status of the i buffers is changed to available; wherein if the frame is not assigned to the second channel, the frame i

Abstract: A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the received data prior to being accessed by a network software application.

Abstract: In a method for operating a medical imaging installation, at least one sensor detects measured signals from an object and supplies them to a control device that buffer-stores the measured signals or raw signals ascertained therefrom online in the main memory. The buffer-stored signals contain components from a number of locations in space. Each component is dependent on a location-dependent influence factor that is determined by the object. The buffer-stored signal can be used to ascertain useful signals which respectively correspond to one of the influence factors, so that they form a three-dimensional reconstruction of the object. The control device permanently stores the buffer-stored signals online in the bulk memory.

Abstract: A method for determining a buffer size of devices in an embedded system is disclosed. A buffer fill time (BFT) and a request response time (RRT) are determined. Next, a media data rate (MDR) and a number of bus masters (NBM) are calculated. Finally, a lowest buffer size of a device is determined according to the BFT, the MDR and NBM of the system.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: A method, apparatus and article of manufacture, implementing the method, processes an error when a write fails in an application that has been ported from a first platform to a second platform. The second platform has a write-to-operator-with-reply call that is not available in the first operating system. The application issues a file write. The application receives an out-of-space error in response to the file write. The application issues a write-to-operator-with-reply call to send a message indicating the out-of-space error to a console.

Abstract: The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop large amounts of data, including graphical video data, from a communication bus. When snooping the communication bus for data, there is a risk that a storage device gathering the data will be overrun when the volume of relevant data snooped is high. The embodiments relate to a method and apparatus for passively throttling the communication bus to prevent overrun of devices storing snooped data.

Abstract: Subject matter to regulate real-time data capture rates to match processor-bounded data consumption operations is described. In one aspect, a computing device receives data from a data source at a real time rate. The data is associated with an object of a particular data size. A data transfer buffer of less capacity than the particular data size is filled with the data at the real-time rate. In parallel with filling the data transfer buffer, the data source is transitioned at one or more particular times, to send repeat data. This allows an application to continuously process all data associated with the object independent of a data transfer buffer overflow condition caused by removal of the data from the data transfer buffer at a processor-bounded rate less than the real-time rate.

Abstract: A system and method for operating on data within a network device is described. Between two data operations in a network device is a FIFO queue, which is used to separate the clock domains of the data operations. Data from the first operation is stored in the FIFO queue, which signals an indication to the second operation that there is data in the queue. When the second operation is signaled that there is data in the FIFO queue, it immediately begins reading data from the queue, and begins performing its prescribed operations on the data once it has read enough data from the queue for it to begin operating.

Abstract: Provided is a method, system, and article of manufacture for inbound packet placement in host memory. A first packet for a buffer in memory is received and a descriptor is generated indicating a length of the first packet and a buffer address of the buffer. At least one subsequent packet following the first packet capable of fitting in the buffer with the first packet is received and a descriptor is generated for each received subsequent packet. The first packet and the at least one subsequent packet capable of fitting into the buffer are transferred to the buffer. The descriptors of the first packet and the at least one subsequent packet written to the buffer are added to a descriptor array.

Abstract: A method and system for a PCI Express device is provided. The elastic buffer includes, a buffer control module that determines a difference between a write and read pointer value and compares the difference to a threshold value for inserting or deleting a standard symbol, wherein the threshold value is adjusted dynamically based on a slow or fast clock speed. The standard symbol is a PCI Express SKIP symbol. The method includes, determining if a clock speed is slow, wherein a monitoring register value indicates if a clock speed is slow; selecting a threshold value based on the monitoring register value; and inserting or deleting a standard symbol based on a comparison of a difference between a write and read pointer and the threshold value. The PCI Express device may be a host bus adapter operating in a storage area network or any other network.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described.

Abstract: A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M?(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.

Abstract: A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a second write port configured to receive the second flag value. A first stage storage element is configured to latch each of the flag values stored in the dual-port memory in response to a first clock signal, such that the flag values are synchronized on an active status bus and flag status bus.

Abstract: A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.

Abstract: A method and apparatus for directly connecting very large data streams from an archive command into a backup data system using an “intelligent process.” An output stream is piped into an intelligent pipe-reading process and distributed over a set of temporary data stores built from raw storage resources. A pipe interface process supervises backup of each filled data store, while the remaining output stream continues to be piped into another available data store. The backup system completes archiving of the datastream, keeping a catalog of the datastream storage locations. To retrieve the data, the intelligent process is run in reverse as a pipe-writing process, requesting data from the backup system. Retrieved data traverses the data stores from the backup system and are pumped into the pipe-writing process for delivery to the pipe output file identified by the retrieve or import command.

Abstract: A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: An upper-level host has a control unit and a host controller for controlling the operation of a device. The host controller includes a buffer memory that reads data from the device into the buffer memory. The control unit reads data from the buffer memory and handles interruptions from the device. Moreover, the host controller reads data for every unit amount from the device with a part of the data of predetermined capacity left in the device, and reads data corresponding to a part of the data of predetermined capacity from the device into the buffer memory if the buffer memory is empty as the data in the buffer memory is transferred to the control unit.

Abstract: An endpoint control apparatus for a device communicating between a host and plural endpoints by way of a universal serial bus includes pluralities of buffers corresponding to the plural endpoints, a first storage unit having data storage status information of the buffers, a controller allocating an empty one of the buffers to a selected one of the endpoints in response to the data storage status information, and a second storage unit having a result of the buffer allocation.

Abstract: A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Abstract: A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing the I2C destination port before the first I2C source port buffer has overflowed; and transmitting the data from the first I2C source port buffer to the I2C destination port while restricting transmission from the second I2C source port buffer to the I2C destination port.

Abstract: A method and an apparatus for power management in a computer system have been disclosed. One embodiment of the method includes monitoring transactions over an interconnect coupling a chipset device and a peripheral device in the system, the transactions being transmitted between the peripheral device and the chipset device according to a flow control protocol to allow the chipset device to keep track of the transactions, and causing a processor in the system to exit from a power state if a plurality of coherent transactions pending in a buffer of the chipset device exceeds a first threshold. Other embodiments are described and claimed.

Abstract: A method and apparatus are described for flow control for digital signal processing to support data stream operations. According to an embodiment of the invention, a method comprises setting a buffer number to an initial value; receiving a first data packet for processing during a first part of a first time frame, the data packet having a first data size; increasing the buffer number by an amount of data that can be passed to a coder; comparing the buffer number to a minimum amount of data for the coder; and setting a second data size to be received based on the comparison between the buffer number and the minimum amount of data for the coder.

Abstract: Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

Abstract: A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a response to the command is returned from the printer to the image providing device. Image data is sent from the image providing device to the printer based on information included in the response. The printer converts the image data outputted from the image providing device into print data. Thus, printing can be performed without a host computer by directly connecting the image providing device and the printer by the 1394 serial bus or the like.

Abstract: A method and apparatus for sending a frame of data from a first channel to a second channel a memory buffers m for storing a frame, in which n have an available status and p have an unavailable status, comprises reserving to the first channel the n buffers having the available status when q of the buffers reserved to the first channel is less than a capacity of reserve module buffers r, when a frame is received, storing the frame in i and changing the status to unavailable, selectively assigning the frame to the second channel based on s of the q buffers; if the frame is assigned to the second channel, the frame is sent to the second channel from the i buffers and the status of the i buffers is changed to available; if is not assigned to the second channel, the frame is discarded and the status of the i buffers is changed to available.

Abstract: FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operating modes including a first hybrid mode that supports a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode and a second hybrid mode that supports a write interface configured in FWFT mode and a read interface configured in standard mode.

Abstract: An extending circuit for memory includes an output data effective signal generator for, when a status signal from a next-stage FIFO circuit represents a data writable state, asserting a write enable signal from the next-stage FIFO circuit, and enabling data to be written into the next-stage FIFO circuit. The extending circuit for memory also includes an internal FIFO write enable generator for receiving a status signal from the next-stage FIFO circuit, asserting an internal FIFO write enable signal, and enabling data to be written into an internal FIFO circuit of the extending circuit for memory, when the next-stage FIFO circuit is in a data unwritable state.

Abstract: A data transmission method and a transmission/reception device are described, the data transmission taking place via intermediate memories without the transmitter receiving direct feedback from the receiver regarding the success of the data transmission. Furthermore, at least one transmission and/or reception device is described which forms an interface between at least two control units and has intermediate memories.

Abstract: An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses. Finally, the device also comprises control circuitry (14, 16), operable during an overflow condition of the memory structure, for writing each data word in successive ones of received data words across multiple ones of the memory word addresses.

Abstract: A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.

Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.

Abstract: The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

Abstract: Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system.

Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: In a transaction system, a dynamic batching process enables efficient flushing of data in a data buffer to a stable storage device. The transaction system uses constant values and dynamic values and a system performance history to adjust the rate of flushing data and also to adjust the amount of data flushed in each flush operation. The transaction system is able to respond to both spikes in rate of received transactions as well as more gradual changes in the rate of received transactions and to automatically adapt to stable storage device performance variations.

Abstract: According to some embodiments, systems an apparatuses may have a communication path to exchange information packets. A processor may process information packets. A buffer pool cache local to the processor may store free buffer handles for information packets when the buffer pool cache local to the processor is not full. A non-local memory may store the free buffer handles for information packets when the buffer pool cache local to the processor is full.

Abstract: A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32?) of its successor (30?) share a common capacitive node (33).

Abstract: A method, apparatus and computer program product are provided for implementing enhanced autonomic data backup using multiple backup devices. A media definition object is defined for saving predefined user selections including a default backup format to be used, an order to process the libraries, a library exception size, and a maximum number of backup devices to be used serially. A list of libraries is generated by either a user specified order of the libraries or a size order of the libraries from largest to smallest. Each library in the generated list of libraries is processed to form at least one library queue of a serial device wait queue and a parallel device wait queue. A process IO procedure is called until backup completes for each library from the at least one library queue.