Abstract: In a method for providing a video data streaming service, a server determines whether an occupancy is below a first threshold or is equal to or greater than a second threshold, the occupancy representing the amount of data occupying a queuing buffer of a terminal and the first threshold being less than the second threshold. If the occupancy is not below the first threshold, the server provides the data streaming service at a predetermined service bit rate which is less than the current service bit rate. If the occupancy is equal to or greater than a second threshold, the server provides the data streaming service at a predetermined service bit rate which is greater than the current service bit rate.

Abstract: An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

Abstract: A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request.

Abstract: Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notifications of queue and other conditions, selectivity in receiving and generating conditions, and the ability to combine data transfer and particular condition notifications in the same attention register.

Abstract: A method and system are described to compute a status for a circular queue within a memory device. A head pointer and a tail pointer are maintained to identify a head entry and a tail entry, respectively, within the queue. In response to an updating of at least one of the head pointer and the tail pointer, at least one of a near-full or a near-empty condition is detected. The detection is performed utilizing parallel operations. The detection of the near-empty and/or near-full conditions may be useful to avoid underflow and overflow errors.

Abstract: To efficiently transfer data from a host computer to a printer, a part of data developed in the first memory is outputted on the basis of a draw command to the printer, the data remaining in the first memory is stored in the second memory after the data was outputted, and a part of the data stored in the second memory is outputted to the printer when the data is being developed in the first memory on the basis of the draw command.

Abstract: The present invention is directed to a method and system for providing, a host input/output (I/O) module, a controller and application specific integrated circuit (ASIC) for utilization in transparent switched fabric data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization.

Abstract: A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing between different sources that transmit in distributed bursts). The transfer length requirements associated with the ongoing data transfers are tracked, along with the total available space in the FIFO memory. A programmable buffer zone also can be included in the FIFO memory for additional overflow protection and/or to enable dynamic sizing of FIFO depth.

Abstract: A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of a plurality of service queues. Each queue has an associated service thread or process that initiates upper layer protocol processing for queued packets. The ISR may select a particular service queue based on the packet's communication flow or connection. Alternatively, the ISR may use a processor identifier provided by the communication interface to select a queue (e.g., in a multi-processor computer system). Or, other information provided by the interface may be used.

Abstract: Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.

Abstract: A method of controlling a queue buffer (2), said queue buffer (2) being connected to a link (1) and being arranged to queue data units (30) that are to be sent over said link (1) in a queue (20), comprising: determining (S1) a value (QL; QL?av#191) of a length parameter related to the length of said queue (20), comparing (S2) said value (QL; QL?av#191) with a length threshold value (L?th#191; min?th#191; max?th#191) and performing (S3) a congestion notification procedure if said value (QL; QL?av#191) is equal to or greater than said length threshold value (L?th#191; min?th#191; max?th#191), and an automatic threshold adaptation procedure (S4, S7), where said automatic threshold adaptation procedure (S4, S7) is arranged to automatically adapt said length threshold value (L?th#191; min?th#191; max?th#191) on the basis of one or more characteristics of said link (1).

Abstract: Methods, system and computer program product are provided to improve the efficiency of data transfers in a PPRC environment. A block of data to be transferred is divided into tracks. Each track is allocated to a data mover task control block (TCB) with a master TCB being assigned to supervise the data mover TCBs. The tracks are then transferred from the primary storage controller to the secondary controller in a piped fashion over a link coupling the primary and secondary storage controllers. However, the usage of resources is monitored by a resource management algorithm and, if too many TCBs are being used for a transfer or if the supply of data mover TCBs is exhausted, the transfer is automatically switched to a serial, non-piped transfer with the master TCB serving as the data mover TCB for the remaining tracks. In addition, the various links coupling the primary and secondary storage controllers is monitored to determine which link will provide the fastest transfer.

Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.

Abstract: A microcontroller device for extending memory address space by inserting a waiting state and an operation method on the device. The device includes a CPU, a ROM, and a memory interface controller. In the device, the memory interface controller inserts a waiting state into the CPU when address of the information or the program to be fetched by the CPU is not located within a predetermined address range until the information or the program is completely fetched.

Abstract: An embedded system for receiving data packets from a communication network includes a plurality of buffers for storing data received from the communication network, and a pointer corresponding to each of the buffers. The embedded system also includes a device for determining whether data received from the communication network is a broadcast data, and a data controller for storing broadcast data in a predetermined number of buffers.

Abstract: A method includes storing data in one of a plurality of memory slots in a queue. Each memory slot is associated with a plurality of flags. The method also includes toggling a first of the flags associated with the slot. The method further includes retrieving the data from the memory slot. In addition, the method includes toggling a second of the flags associated with the slot.

Abstract: An LCD controller (10) has a DMA unit (18) and a FIFO memory (20) for storing display data. The LCD controller also has a display data generator (26) that generates display information using a line of the display data stored in the FIFO memory in accordance with a predefined algorithm. A holding register (28) is connected to the display data generator and stores the generated display information. A multiplexer (34) selects for display either the data stored in the FIFO memory or the generated display information. The generated display information is selected when there is a bus overload indicating that the data stored in the FIFO may be erroneous.

Abstract: The invention relates to a bus system comprising a first station (202) and a second station (203), (204), coupled by a bus for transferring messages, said bus being designed to operate in accordance with a protocol in which said first station (202) periodically sends messages in a predetermined order to the second station (203), (204), wherein said first station (202) comprises an interruptible processor (206), a memory element (208) comprising a buffer (501, 502), and a bus interface (207), wherein said interruptible processor (206) can be operated so as to generate a plurality of series of message properties; wherein said processor (206) can further be operated so as to issue a first series of message properties from among said plurality of series of message properties to said buffer (501, 503), and upon receipt of an interrupt signal from said bus interface issues a second series of message properties from among said plurality of series of message properties; wherein said buffer (501, 502) has a storage

Abstract: A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are designated cache only. Cache only commands are added to the queue only if they can be completed without accessing the disk I/O subsystem. If the disk I/O subsystem would be accessed in order to complete a cache only command, the command is returned to the operating system with an error. The operating system can then add the command to an operating system or back-up queue.

Abstract: A method and system for communicating to a sender an availability of receiving a new message includes providing buffers having at least one corresponding slot for storing a message and providing a credit signal that communicates to the sender only when all of the buffers have at least one of the corresponding slot available for storing a new message. Each of the buffers is monitored for whether at least one of the corresponding slots is available for storing the new message. A corresponding receiver counter is provided for each of the buffers. Each receiver counter is decremented when all of the buffers have at least one corresponding slot available for storing the new message. Each of the buffers is configured to receive a corresponding particular message type. The particular message type of the new message is determined. The new message is loaded into the corresponding slot of one of the buffers which is configured for receiving the particular message type of the new message.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in the buffer device a plurality of buffer segments. Respective ones of the buffer segments are filled with data from at least one data source device operating in a respective clock domain. Upon any respective buffer segment being filled up, the method allows to generate an indication of availability of the contents of the respective buffer segment to at least one data destination device operating in a respective clock domain. The clock domain of the at least one source device is distinct than the clock domain of the at least one destination device.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: At least one queue parameter for a first process running on a system is determined. A queue management process separate from the first process configures one or more queues on a storage device in accordance with the at least one queue parameter.

Abstract: In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.

Abstract: The data storage system 1 comprises tape drives 21 to 23 operable to read and write data transmitted via the SCSI bus 112 from and on a tape in parallel and a host PC 4 for controlling data transmission to the SCSI bus. The host PC 4 includes a data access control unit 41 operable to calculate a bus reconnect timing that makes it possible to avoid stopping tape writing or reading even when any one of the respective drive drives 21 to 23 waits for the time when the other tape drives finish data transmitting after it reaches a bus reconnect timing based on the tape drive information “(the number of drive units, a data transmission speed of the bus, either a data reading speeds of the respective drive units or a data writing speeds of the respective drive units)=(m, S and R)”.

Abstract: The present invention provides a method of transferring incoming multithreaded concurrent sets of data from a sending transport system to a requesting transport system which includes retrieving the sets of data from the sending transport system. A receiving queue is queried for a number of available data storage locations, and the sets of data being transferred to the receiving queue. The method further includes queuing the sets of data in the receiving queue, where each the set of data are divided into blocks of data. Then, determining a number of the data storage locations for storing the blocks of data. Next, the blocks of data are loaded into available data storage locations, and location indexes are provided for each of the blocks of data where the location indexes associate the block of data with a corresponding the storage location.

Abstract: The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as the PCI bus. Due to the PCI bus design, read requests from memories connected across the PCI bus take a significantly longer time to complete than performing a write operation under the same circumstances. The present invention uses the faster write operations across the PCI bus, and queue management techniques, to take advantage of the relative speed of writes in a PCI system. The overall result is significant performance enhancement, which is especially useful in service aware networks (SAN) where operation at wired-speed is of paramount importance.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: Subject matter to regulate real-time data capture rates to match processor-bounded data consumption operations is described. In one aspect, a first transition time for a data source to transition from a first mode to a second mode is determined. A second transition time for the data source to change from the second mode to the first mode is also identified. Based on the first and second transition times, the data source is directed to transition into respective ones of the first and second modes such that real-time capture of data from the data source is regulated by a computing device to match processor-bound data consumption rates of an application consuming the data.

Abstract: A system and method autonomically reallocate memory among buffer pools to permit quick access to data. A simulated buffer pool extension (SBPX) is created for each buffer pool in a set of buffer pools. Data victimized from a buffer pool is represented in the associated SBPX. Requests for data that is not resident in a buffer pool but is represented in the associated SBPX are tallied. Periodically, an expected efficiency benefit of increasing the capacity of each buffer pool is determined from the tallies. Memory is reallocated from the buffer pool with the lowest expected efficiency benefit having remaining reallocatable memory to the buffer pool with the highest expected efficiency benefit having remaining reallocatable memory, until either one or both of the buffer pools exhausts its reallocatable memory.

Abstract: A method and system for managing cache levels based on battery backup level are described. In one embodiment, the method comprises measuring the level of charge stored in an exhaustible power source. The method further comprises monitoring the level of charge stored in the exhaustible power source. The method further comprises adjusting the storage level of the cache in response to a detected change in the level of charge. In this way, the method ensures that adequate battery power is available to transfer the contents of the cache to a non-volatile data storage medium.

Abstract: Provided are a method, system, and article of manufacture for borrow processing in storage pools. A plurality of physical volumes are allocated to a first storage pool. A determination is made whether the first storage pool has less than a threshold number of empty physical volumes. If the first storage pool has less than the threshold number of empty physical volumes, then at least one empty physical volume is borrowed to the first storage pool from a second storage pool.

Abstract: Provided are a method, system, and article of manufacture for pooling of storage. Volume attributes are assigned to a plurality of physical volumes. Pool attributes are assigned to a plurality of storage pools, wherein the pool attributes include policies for borrowing and returning the plurality of physical volumes to and from the plurality of storage pools. One of the plurality of physical volumes is allocated to one of the plurality of storage pools based on the volume attributes of the one of the plurality of physical volumes and the pool attributes of the one of the plurality of storage pools.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: Methods for controlling and storing data in a cache buffer in a storage apparatus having a nonvolatile memory medium are disclosed. Memory cells are logically divided into a plurality of pages. An open status is registered in a counter for each page that has at least some (and usually all) memory cells available to store new data. A full status is registered in the counter for each page that does not have memory cells that are available to store new data. New data is stored in pages having the open status in the counter. The pages can be weighted according to the read command rate and prioritized for reading and writing purposes.

Abstract: An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.

Abstract: A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A system and method is disclosed for preventing the loss of event messages due to message buffer overruns. A fixed vendor-specific buffer pool is loaded with log messages by firmware in an adapter. A service application periodically polls a device driver for messages in the buffer pool. The device driver responds with the number of messages stored in the buffer pool and the total number of buffers in the buffer pool. The service application then issues “get next message” requests to receive the stored messages. Once the buffer pool has been emptied, the service application writes the messages to a disk file. The service application then computes a percent utilization of the buffer pool, and if the percent utilization exceeds a predetermined threshold, an algorithm is employed for increasing the polling frequency. If the percent utilization is below the threshold, an algorithm is employed for decreasing the polling frequency.

Abstract: A recording method for improving interrupted interferences, for use in a recording apparatus. First, a buffer is allocated, and then, the size of the buffer is checked. If the size of the buffer is smaller than a minimum recording segment, an alternative buffer is allocated; otherwise, data is recorded to the buffer. Then the data is recorded to the alternative buffer, the data in the alternative buffer is interpolated to the buffer.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: A method and apparatus are provided for caching free cell pointers pointing to memory buffers configured to store data traffic of network connections. In one example, the method stores free cell pointers into a pointer random access memory (RAM). At least one free cell pointer is temporarily stored into internal cache configured to assist in lowering a frequency of reads from and writes to the pointer RAM. A request is received from an external integrated circuit for free cell pointers. Free cell pointers are sent to queues of the external integrated circuit, wherein each free cell pointer in a queue is configured to become a write cell pointer. At least one write cell pointer and a corresponding cell descriptor is received from the external integrated circuit. Free cell pointer counter values are then calculated in order to keep track of the free cell pointers.

Abstract: A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and reads the data from the memory using the gapped clock signal. The read logic generates the gapped clock signal by turning on and off a constant local clock signal.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.

Abstract: A data storage device may be constructed with a disk array; an array controller for controlling the array; and a queue for queuing commands from a host system to the disk array. Programming installed on the array controller adjusts a logical size of the queue to optimize performance.

Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.