Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.

Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Abstract: A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.

Abstract: A memory system includes a memory device suitable for storing data and a controller suitable for determining an operation state of the memory device and carrying out garbage collection to the memory device in response to the operation state. The controller can ignore a first command entered from a host while performing the garbage collection.

Abstract: Embodiments of systems and methods for fast input/output (IO) on PCIE devices are described. Such methods include receiving an IO request from a user or application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device, analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system, defining a routing instruction in a transfer routing information transmitter in response to the selected communication path, communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

Abstract: A scheme for handling program errors is provided for a memory system which includes a memory device and a controller including firmware and a memory interface. The firmware issues commands for program operations to the memory interface. After detecting a failed program operation in a particular memory block, the firmware reroutes that program operation to a different location in a different memory block and takes further action to reduce the likelihood of a subsequent error occurring in the same memory block in which the failed program operation occurred.

Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory controller may include a storage area manager and a write operation controller. The storage area manager may allocate a plurality of memory devices to a first group and a second group in response to a storage area setting command. The write operation controller may control a group selected from the first group and the second group according to a type of a write request to store write data. At least one memory devices in the first group includes memory blocks storing n data bits. At least one memory devices in the second group includes memory blocks storing m data bits.

Abstract: A system includes a memory circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

Abstract: Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs via a memory interface.

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.

Abstract: An apparatus comprises a processing device. The processing device is configured to persistently store metadata pages on a plurality of storage devices. The metadata pages are organized into buckets. The processing device is configured to access a given metadata page based at least in part on a bucket identifier where the given metadata page corresponds to a given logical volume. The bucket identifier comprises a first portion comprising an indication of a given bucket range that corresponds to the given logical volume and a second portion comprising an indication of an offset into the given bucket range that corresponds to a grouping of buckets that correspond to the given logical volume. The grouping of buckets corresponds to the given logical volume. The bucket identifier further comprises a third portion comprising an indication of an offset into the grouping of buckets that corresponds to the bucket comprising the given metadata page.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, information associated with a relationship between a physical layer block and a virtual logic block for RAID storage. The information associated with the relationship between the physical layer block and the virtual logic block may be written within the RAID storage. The physical layer block within the RAID storage may be rebuilt only when the physical layer block includes the information associated with the relationship between the physical layer block and the virtual logic block.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.

Abstract: A data storage device includes a nonvolatile memory including a plurality of memory blocks and page buffers for data input/output, the page buffers being electrically connected to the plurality of memory blocks, respectively, and a controller configured to, when a number of free memory blocks among the plurality of memory blocks is equal to or less than a predetermined threshold number, select, as a candidate source memory block group, memory blocks each having a number of valid pages equal to or less than a predetermined number within the nonvolatile memory, select, as a source memory block, a memory block having a minimum amount of time required to read valid data from the valid page within the candidate source memory block group and perform a garbage collection operation to the source memory block.

Abstract: A storage device is provided. The storage device includes a boot ROM stores a plurality of public keys and a boot ROM image, an OTP memory identifies a first public key among the plurality of public keys, a first memory including a first area the stores the plurality of public keys and a flash boot image different from the boot ROM image, and a second area that stores a first boot signature corresponding to the flash boot image, a second memory including a first firmware image including a first firmware signature, and a memory controller that receives a second firmware image including a second firmware signature and a second boot signature, receives a second public key among the plurality of public keys and the flash boot image based on the second firmware image being received, and write the second boot signature in the second area of the first memory.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: A data processing system according to one embodiment includes first and second data storage devices having a storage medium capable of permanently storing data; a data holding device having a storage medium capable of storing the data at a higher speed than the first and second data storage devices; and a controller that determines the type of data to be processed, and, in the case where the data to be processed is structured data, stores the data to be processed in the data holding device, then, collectively, in the first data storage device, and, in the case where the data to be processed is binary data, stores the data to be processed in the data holding device and in the second data storage device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device performs operations in parallel on a plurality of memory blocks. The controller determines, in response to a read request on a plane including a target memory block among the plurality of memory blocks, whether to perform a process for a partial suspension on the operations based on suspension counts of the plurality of memory blocks. The controller controls, when performing a process for the partial suspension, the non-volatile memory device to suspend the operation being performed on the target memory block and to keep performing the operations being performed on other memory blocks among the plurality of memory blocks.

Abstract: A method, article of manufacture, and apparatus for managing data. In some embodiments, this includes determining a usage level of a file, wherein the file is stored in a first storage system, moving the file to a second storage system based on the determined usage level of the file updating location information in a catalog based on the movement of the file, and performing at least a portion of a query on the file after updating location information in the catalog.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.

Abstract: A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to receive host commands, such as write commands. Upon determining that a received plurality of write commands are sequential, but includes one or more write commands that are unaligned with a memory granularity of the memory device, the one or more write commands are revised such that the one or more write commands are aligned with the memory granularity. The revised write command includes a first of the one or more write commands and a portion of a second of the one or more write commands. A beginning of the revised write command is aligned with the memory granularity and the end of the revised write command is also aligned with the memory granularity.

Abstract: A technique for managing SSDs in a data storage system generates an endurance value for each of multiple SSDs and arranges the SSDs in RAID groups based at least in part on the generated endurance values. As a result of such arranging, some RAID groups may include only SSDs with higher endurance values while other RAID groups may include only SSDs with lower endurance values. The data storage system may then run RAID groups with higher endurance values at higher speeds and may run RAID groups with lower endurance values at lower speeds.

Abstract: An interface receives storage requests for storing data in a software-defined storage network using an append-only storage scheme. The requests include an identifier of a data object to be stored. The requests are agnostic of hardware-specific details of the storage devices. A virtualization layer accesses space allocation data for the storage devices; and policies for prioritizing performance. Based on the data and policies, a physical storage location at the plurality of storage devices is selected for storing the data object. Metadata is generated for the data object indicating that the data object is an append-only object and mapping the physical storage location of the data object to the identifier. The request is translated to instructions for storing the data object at the physical storage location using the append-only storage scheme. The data object is stored at the physical storage location using the append-only storage scheme.

Abstract: A method for provided use in a storage device having a controller, the method comprising: identifying, by the controller, a plurality of logical regions in the storage device; obtaining, by the controller, a respective usage metric for each of the logical regions; updating, by the controller, a translation data structure of the storage device, the translation data structure being updated to map any of the logical regions of the storage device to a respective physical portion of the storage device, the respective physical portion being selected based on the respective usage metric of the logical region, wherein the translation data structure is part of a flash translation layer of the storage device, and the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device.

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

Abstract: Systems and methods data storage device performance prediction based on garbage collection resources are described. The data storage device may process host storage operations and determine a valid fragment count parameter for a current or future data block. Based on the valid fragment count parameter a predicted performance value for host storage operations is determined and the host device is notified of the predicted performance value.

Abstract: Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.

Abstract: A storage device including a nonvolatile memory device is described. The storage device includes a controller that receives a write command and data from an external host device. The controller preferentially writes the data in an area based on a normal write policy when the data is associated with a normal write, and in an area based on a turbo write policy when the data is associated with a turbo write. The controller may also receive a read command, to read data from an area based on the read command, and output the data to the external host device. The controller may also move the data in response to move information of the read command when the read command is received together with move information.

Abstract: Techniques provide for managing data storage. The techniques involve in response to receiving a request for unmapping a logical storage unit associated with a first disk slice on a first physical disk and the first disk slice, determining information associated with the first disk slice; generating, based on the information, a first entry and a second entry corresponding to the first disk slice; adding the first entry into a queue of failed disk slices to enable data stored on the first disk slice to be cleared; and adding the second entry into a queue of free disk slices to enable the first disk slice to be mapped to a further logical storage unit. Accordingly, such techniques can remarkably improve the write I/O performance of the system and prolong the lifetime of the SSD.

Abstract: A method, a computing device, and a non-transitory machine-readable medium for allocating data compression activities in a storage system are provided. A method includes tracking, by a storage controller, computing resources corresponding to a storage server. The storage controller processes one or more host read requests to access data requested by one or more hosts, the processing of the one or more host read requests including decompressing the data requested by the one or more hosts from the storage server and providing the decompressed data to the one or more hosts. The storage controller determines an amount of available computing resources after processing the one or more host read requests. Based on the amount of available computing resources, the storage controller performs inline compression of a first portion of host write requests and background compression of a second portion of the host write requests.

Abstract: An interface is instantiated for receiving storage requests for storing data in a software-defined storage network using an append-only storage scheme. The interface receives requests that are agnostic of interfaces and hardware-specific details of the storage devices of the software-defined storage network. A request comprises an identifier of a data object to be stored in the software-defined storage network using the append-only storage scheme. Metadata is generated for the data object indicating that the data object is an append-only object; and the request is translated to instructions for storing the data object in the storage devices using the append-only storage scheme. The data object is stored at one of the plurality of storage devices based on the instructions. The metadata is updated to indicate a mapping between the data object and a stored location of the data object.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system performs an operation of recovering system data lost due to SPO when an SPO recovery operation is performed, and flushes recovered system data into the memory device after a first time point at which the operation of recovering the system data is completed and before a second time point at which a power off preparation request is received from a host.

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: A method, a device, and an integrated circuit utilizes a temperature restricted mode. The method includes determining a temperature of the device. When the temperature is below a first threshold, the method includes enabling a first mode comprising select network operations. When the temperature is above a brick threshold, the method includes enabling a second mode comprising disabling the select network operations. When the temperature is above the first threshold and below the brick threshold, the method includes enabling a third mode comprising modifying at least one of the select network operations.

Abstract: A memory system includes: a plurality of memory devices including a memory cell array having a plurality of planes, the plurality of memory devices being commonly connected to a memory controller through a channel; a super block including pages included in the planes of at least two memory devices among the plurality of memory devices; and the memory controller for transmitting, to the memory devices, at least one command instructing an operation on the super block and an address corresponding to the command. Each of the memory devices includes: peripheral circuit for performing the operation on the memory cell array; a group selection signal generator for outputting a group selection signal indicating the at least two memory devices constituting the super block; and control logic for controlling the peripheral circuit to perform an operation corresponding to the command, based on the group selection signal.

Abstract: Methods, non-transitory machine readable media, and computing devices that use extended physical region page (PRP) lists to improve storage device performance are disclosed. With this technology, a PRP list is generated that includes pointers retrieved from a scatter/gather list (SGL) for memory buffers representing data segments associated with a storage operation. The PRP list is extended to include a pointer to an allocated memory page configured to store metadata segments represented by other memory buffers referenced by other pointers in the SGL. A command request that includes the extended PRP list is submitted to a storage device for execution of the storage operation. With this technology, storage operations are advantageously enabled for non-volatile memory express (NVMe) solid-state drive (SSDs), for example, that do not support SGL transfers.

Abstract: Aspects of a storage device are provided which reduce write amplification by minimizing data flushes from cache to SLC blocks during RMW operations. A memory of the storage device includes a first memory location of one or more single-level cells and a second memory location of one or more multiple-level cells. A controller of the storage device receives first data associated with a first range of logical addresses and second data associated with a second range of logical addresses. During a RMW operation of the first data, the controller determines whether the first range overlaps with the second range, and stores or flushes the second data in the first memory location when an overlap is determined. The controller stores or writes the second data in the second memory location when an overlap is not determined. Accordingly, data flushing to the single-level cells is minimized when no overlap is determined.

Abstract: Methods, systems, and devices for secure self-purging memory partitions are described. Systems, techniques and devices are described herein in which data stored in a portion of a secure partition of memory may be removed from the secure partition. In some examples, a portion of secure partition may be allocated as self-purging memory such that data stored therein may be selectively removed in response to a logic address associated with the data being overwritten. In some cases, the data may be removed by programming the memory cells associated with the data to a specific voltage distribution. In some cases, the secure partition may include separate portions having different sets of operating parameters for access operations.

Abstract: A memory system, and a method of operating the memory system, includes a memory device including a plurality of memory blocks. The memory system also includes a memory controller for controlling the memory device to perform a data copy operation of moving and storing valid data stored in a selected memory block among the plurality of memory blocks in a target block among the plurality of memory blocks. The memory controller is configured to control the memory device to perform the data copy operation by preferentially selecting a weak page among a plurality of pages included in the selected memory block rather than the other pages.

Abstract: A memory controller may control a memory device including a first storage area and a second storage area. The memory controller may include: a memory operation controller and a block information manager. The memory operation controller may control the memory device to perform a block merge operation of programming data stored in a victim block among normal blocks of the first storage area to a target block among the normal blocks, and perform a data migration operation of copying data stored in blocks of the first storage area to blocks of the second storage area. The block information manager may store block map information indicating whether each of the blocks of the first storage area is a normal block or a merge block. The target block may be changed from a normal block to a merge block by the block merge operation.

Abstract: A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

Abstract: A memory device includes a plurality of memory blocks, a read count storage, and a read reclaim processor. The read count storage stores read count information including a read count of each of the plurality of memory blocks. The read reclaim processor provides a memory controller with a status read response including a status code representing a priority order of a read reclaim operation on a target block, in response to a status read command received from the memory controller.

Abstract: The present technology relates to a memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells, a data register connected to the memory cell array through a bit line and configured to store data sensed through the bit line, a cache register configured to cache the data stored in the data register, and a control logic configured to control a caching operation of receiving a cache read command from a memory controller and storing the data, which is stored in the data register, in the cache register, during a cache read period, in response to the cache read command, wherein the control logic controls the caching operation based on whether the cache read command is a first command received after receiving a normal read command from the memory controller.