Abstract: An operation method of a storage device, which includes a nonvolatile memory device, includes receiving a first key-value (KV) command including a first key from an external host device; transmitting a first value corresponding to the first key from the nonvolatile memory device to the external host device as first user data, in response to the first KV command; receiving a second KV command including a second key, from the external host device; and performing a first administrative operation based on a second value corresponding to the second key, in response to the second KV command. The first KV command and the second KV command are KV commands of a same type.

Abstract: Various implementations described herein relate to systems and methods for managing metadata for an atomic write operation, including determining metadata for data, queuing the metadata in an atomic list, in response to determining that atomic commit has occurred, moving the metadata from the atomic list to write lookup lists based on logical information of the data, and determining one of metadata pages of a non-volatile memory for each of the write lookup lists based on the logical information.

Abstract: Techniques for data placement may include receiving data portions stored at logical addresses, and storing the data portions on slices of physical storage located in storage tiers. The storage tiers may include different size slices on the different tiers. In one embodiment, slices in the same tier are all the same size. In another embodiment, slices in the same tier may be of different sizes. Slices of data may be demoted and promoted among the storage tiers as the workloads of the slices changes over time. Demotion may include combining slices into a larger slice. Promotion may include partitioning a slice into smaller slices. Additionally, multiple slices of a tier may be combined into a larger slice in the tier. A slice in the tier may be partitioned into multiple smaller slices also located in the tier.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.

Abstract: A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by an NVMe storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.

Abstract: This application provides an information processing method, an apparatus, a device, and a system. The information processing method includes: A host chip determines first information, where the first information includes a first logical address set. The host chip generates first indication information, where the first indication information includes the first logical address set and a first physical address set that is determined based on a mapping relationship between a logical address and a physical address and that corresponds to the first logical address set, the first physical address set includes N physical addresses, the N physical addresses are in a one-to-one correspondence with N logical addresses included in the first logical address set, and N is an integer greater than or equal to 2. The host chip sends a first request to a storage chip connected to the host chip, where the first request includes the first indication information.

Abstract: A secure cloud-based privileged access management (CBPAM) service manages on-premise resources. While enrolling an on-premise authentication domain admin group, a secured cloud-based shadow administrating group (SCBSAG) is created; a SCBSAG security identification includes at least part of the enrollee's security identification. The SCBSAG belongs to a clean CBPAM authentication domain which may be secured by defense in depth controls such as time limits on authentication or authorization, password avoidance, least privilege, one-way syncing, and one-way trust. Management via the configured SCBSAG may be fostered by emptying the on-premise admin group, although a break glass account may be kept. CBPAM services direct administrative actions toward on-premise resources through SCBSAGs for cloud tenants, providing secure management control as a service, with broader geographic scope and lower maintenance burdens and costs than privileged access management approaches that are not cloud-based.

Abstract: A multiple storage node system including a first and second node is provided. The first node includes a first baseboard management controller (BMC), a first flash ROM configured to store a first flash image, and a first switch device configured to connect the first BMC to the first flash ROM. The second node includes an exact configuration of the first node. The first BMC is connected to the second switch device, and the second flash image is the same as the first flash.

Abstract: A storage device comprises a flash memory and processing circuitry. The processing circuitry is configured to divide a storage area into pages to manage the storage area, and deletes each of the blocks including a plurality of pages. The processing circuitry receives a write instruction including address information specifying a writing location of the data, and stores, with respect to a plurality of groups in which each group includes one or more blocks, a plurality of group identification information each identifying a group and information specifying blocks included in the group in association with each other. The processing circuitry performs a predetermined calculation to obtain group identification information, and identifies a group including a block including pages onto which data is to be written according to the write instruction. Finally, the processing circuitry writes the data onto the pages of the block included in the group identified.

Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.

Abstract: A memory controller for controlling a plurality of memory chips of a non-volatile memory includes a first core configured to identify a size of a remaining space of a page to be written in a memory chip on which a write operation is to be performed among the plurality of memory chips and fetch a first write command from a first submission queue among a plurality of submission queues included in a host, the first write command being related to data having a size corresponding to that of the remaining space of the page to be written, and a second core configured to control the non-volatile memory to store data related to the fetched first write command in the remaining space of the page to be written.

Abstract: A method includes: receiving a service participation request of a target service transmitted by a user terminal, wherein the user terminal comprises an iOS operating system; obtaining target identification data from a system server according to the service participation request, wherein the target identification data comprises first identification data used for identifying whether the user terminal participates in the target service, and/or second identification data used for identifying whether the device data of the user terminal is modified, and the system server is a server corresponding to the iOS operating system; and according to the target identification data, determining whether to allow the user terminal to participate in the target service.

Abstract: Flexibly expanding the storage capacity of a data storage system by adding a single physical storage device or any number of disk drives to an existing storage system without the need to reconfigure existing erasure encoding groups of the system. The physical storage devices of a data storage system may be divided into a plurality of slices, and each slice may be a member of an erasure encoding group. Physical storage devices that are added to the data storage system may be divided into same number of slices and/to slices of a same size, which then may be added to existing erasure encoding groups, utilized as spare slices or left idle until all of the slices are integrated into the data storage system.

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, a cache storage, victim row identification circuitry and victim row protection circuitry. The victim row identification circuitry is configured to detect a rapid rate of access requests from the processing circuitry to a given row of a DRAM and, responsive to said detecting, identify at least one victim row associated with said given row. The victim row protection circuitry is configured to copy data stored within said at least one victim row to the cache storage.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

Abstract: A data storage apparatus may include a storage and a controller configured to operate in a throttling mode including a first performance mode and a second performance mode based on measured temperature of the storage. The controller comprises a performance adjusting component configured to determine target performance of the first performance mode based on at least one of temperature of the storage and the number of entries into the second performance mode when the temperature of the storage is greater than or equal to a first threshold value.

Abstract: A memory system includes: a memory device including a plurality of memory blocks each having a plurality of pages suitable for storing data; and a controller suitable for: receiving a plurality of commands from a host; controlling the memory device to perform a plurality of command operations in response to the plurality of commands; identifying parameters for the memory blocks affected by the command operations performed to the memory blocks; selecting first memory blocks among the memory blocks according to the parameters; and controlling the memory device to swap data stored in the first memory blocks to second memory blocks among the memory blocks.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: A non-volatile memory device includes a non-volatile memory unit, a control unit, and an interface. The control unit receives a write request, determines whether data is an object of a write of sequential management when a write size of the received data is smaller than a management unit of erasure, performs first write processing in which the received data smaller than the management unit of the erasure is sequentially written when the data is the object of the write of the sequential management, and performs second write processing in which the received data smaller than the management unit of the erasure is written by the management unit of the write when the data is not the object of the write of the sequential management.

Abstract: A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units; reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units; identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation; and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.

Abstract: The present application pertains to a processing device or a distributed processing system using the processing device.

Abstract: Techniques for generating a model for predicting when different hybrid prefetcher configurations should be used are disclosed. Techniques for using the model to predict when different hybrid prefetcher configurations should be used are also disclosed. The techniques for generating the model include obtaining a set of input data, and generating trees based on the training data. Each tree is associated with a different hybrid prefetcher configuration and the trees output certainty scores for the associated hybrid prefetcher configuration based on hardware feature measurements. To decide on a hybrid prefetcher configuration to use, a prefetcher traverses multiple trees to obtain certainty scores for different hybrid prefetcher configurations and identifies a hybrid prefetcher configuration to used based on a comparison of the certainty scores.

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Abstract: Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.

Abstract: A method includes the steps of storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a number of read units, wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit, storing, in each of the at least one spanning read units that include the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit, and locating an Lpage of data stored in the NVM by referring to an entry stored a flash memory controller map table.

Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.

Abstract: Provided is a method of data storage, the method including receiving a write request including a user key, determining the user key exists in a cache, generating or updating metadata corresponding to the user key, writing data corresponding to the write request to a storage device, converting the metadata to a device format corresponding to the storage device, and storing the metadata on the storage device.

Abstract: A scheduling system for a memory controller is provided. The system includes a scheduler configurable to receive a plurality of operation requests from a plurality of masters. The scheduler is configurable to form a sequence of one or more phases from each of the operation requests. The scheduler is configurable to arbitrate the plurality of operation requests and the one or more phases through one or more configurable policies. The system includes a sequencer configurable to receive the one or more phases and communicate with at least two flash memory devices having differing types of flash memory device interfaces through a plurality of channels.

Abstract: A system is provided to receive a first request to write data to a storage system, which comprises an MRAM, a NOR, a DRAM, and a NAND. The system writes the data to the MRAM. The system copies the data from the MRAM: to the NOR in response to determining that the data is read at a frequency greater than a first predetermined threshold and is updated at a frequency less than a second predetermined threshold; to the DRAM in response to determining that the data is read at a frequency less than the first predetermined threshold and is updated at a frequency greater than the second predetermined threshold; and to the NAND in response to determining that the data is read at a frequency less than the first predetermined threshold and is updated at a frequency less than the second predetermined threshold.

Abstract: A memory system includes a non-volatile memory device and controller circuitry. The non-volatile memory device includes an array of memory cells that includes memory blocks and pages. Each separate memory block includes a separate, respective set of one or more pages. The controller circuitry is configured to control an operation of the non-volatile memory device. The controller circuitry includes processing circuitry configured to perform a recovery operation for the non-volatile memory device in response to a determination that a specific event has occurred at the memory system during a program operation of the non-volatile memory device. The recovery operation includes determining status information associated with a first group including at least one page, determining a quantity of a set of pages included in a second group based on the status information, and programming dummy data for one or more pages of the set of pages included in the second group.

Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.

Abstract: Methods of operating a die might include determining an expected peak current magnitude of the die for a period of time, and outputting the expected peak current magnitude from the die prior to completion of the period of time. Apparatus might be configured to perform similar methods.

Abstract: It is possible to perform a stochastic process based on a metropolis algorithm while reducing a physical quantity of a circuit. Provided is an information processing apparatus including one or a plurality of array circuits. In this apparatus, each of the array circuits includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of one node of a coupling model, a second memory that stores a coupling coefficient indicating coupling from a node of another unit connected to an unit of the second memory, and a logic circuit that determines a value indicating a subsequent state of the one node based on a value indicating a state of the node of the other unit and the coupling coefficient. Further, the logic circuit sets a first random variable in accordance with an exponential distribution of a parameter ? as an input.

Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system; and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.

Abstract: Disclosed methods and systems allow a central server to monitor electronic units of work accessible to a group of computers and generate a nodal data structure representing the units of work. The server then uses various protocols, such as hashing algorithms and/or executing artificial intelligence and machine learning models to identify similar and/or related units of work. The server then merges/links the nodes corresponding to the similar/related units of work. The server also monitors all user activities. When a user or a software system/service accesses electronic content on his, her, or its electronic device, the server identifies a node corresponding to the accessed electronic content and associated unit(s) of work and presents searchable data and actions related to the identified node and any related/linked nodes.

Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.

Abstract: A data processing system includes a host configured to handle data in response to an input received by the host, and a plurality of memory systems engaged with the host and configured to store or output the data in response to a request generated by the host. A first memory system among the plurality of memory systems can perform generation, erasure, or updating of metadata for the plurality of memory systems.

Abstract: A storage device includes a memory device and a controller. The memory device stores attribute information associated with a host memory buffer allocated on a host memory. The controller communicates with the host memory such that a plurality of pieces of data associated with operations of the memory device is buffered, based on the attribute information, in a plurality of host memory buffers allocated on the host memory. The controller communicates with the host memory such that first data corresponding to a first attribute group managed in the attribute information is buffered in a first host memory buffer among the plurality of host memory buffers and second data corresponding to a second attribute group different from the first attribute group is buffered in a second host memory buffer separate from the first host memory buffer.

Abstract: According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.

Abstract: A method of operating a storage system is provided. The method includes executing an operating system on one or more processors of a compute device that is coupled to one or more solid-state drives and executing a file system on the one or more processors of the compute device. The method includes configuring the compute device with one or more replaceable plug-ins that are specific to the one or more solid-state drives, and executing a flash translation layer on the one or more processors of the compute device, with assistance through the one or more replaceable plug-ins for reading and writing the one or more solid-state drives.

Abstract: The present disclosure provides an operating method of a storage controller. The operating method includes receiving user data and environmental information, obtaining logical-characteristic information and physical-characteristic information, defining a current state, obtaining expectation values, and performing a write operation. User data and environmental information is received from a non-volatile memory. The current state may be defined based on the logical-characteristic information and the physical-characteristic information. Expectation values may be obtained based on policy information and the current state. The write operation may be performed on the user data through a physical stream corresponding to a maximum value among the expectation values.

Abstract: A memory controller may include a host interface controller, a first queue, a second queue, and a cache memory. The host interface controller may be configured to generate, based on a request received from a host, one or more command segments corresponding to the request. The first queue may be configured to store the one or more command segments. The second queue may be configured to store a target command segment from among the one or more command segments. The memory controller caches a target map segment corresponding to the target command segment into the cache memory in response to the target command segment being transferred from the first queue to the second queue.

Abstract: A memory system may include a memory device including a plurality of memory blocks and a controller suitable for determining whether to change from a normal mode to a dirty mode based on a size of free space of a host a sum of an amount of restoration of garbage collection for victim blocks and a size of all free blocks in the memory device. In the dirty mode, the controller controls the memory device to perform a garbage collection operation on the victim blocks at a frequency greater than frequency at which a garbage collection operation is performed in the normal mode.

Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.

Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

Abstract: A technique includes, in a pre-operating system environment of a computer system, a hardware processor of the computer system executing machine executable instructions to determine whether a sanitization option was selected in a prior operating system environment of the computer system. In response to determining that the sanitization option was selected, the hardware processor executes the instructions in the pre-operating system environment to determine, for an adapter of the computer system, a storage inventory associated with the adapter and sanitize the storage inventory.

Abstract: According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.

Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.