Abstract: Present disclosure relates to a method and a system for searching through a Ternary Content Addressable Memory (TCAM). The system comprises a Digital Light Processing System (DLP) receiving an input query. The DLP comprises a 2-Dimensional array of digital micro mirrors configured for reflecting light from one or more input sources in the TCAM to a predefined position. The system further comprises a detection screen having a detection area. The detection area is configured for generating an image of a resultant pixel according to the reflection of the light, wherein the resultant pixel corresponds to a search result for an input query.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: Secure communication between users and resources of an electrical infrastructure and associated systems and methods. A representative secure distributed energy resource (DER) communication system provides for the creation of trust rules that govern the permitted communications between users and resources of an electrical infrastructure system, and the enforcement of the trust rules.

Abstract: In order to control a technical system using a control model, a transformation function is provided for reducing and/or obfuscating operating data of the technical system so as to obtain transformed operating data. In addition, the control model is generated by a model generator according to a first set of operating data of the technical system. In an access domain separated from the control model, a second set of operating data of the technical system is recorded and transformed by the transformation function into a transformed second set of operating data which is received by a model execution system. The control model is then executed by the model execution system, by supplying the transformed second set of operating data in an access domain separated from the second set of operating data, control data being derived from the transformed second set of operating data.

Abstract: Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.

Abstract: A method includes automatically determining a component of a security label for each first record in a first table of a database having multiple tables, including: identifying a second record related to the first record according to a foreign key relationship; identifying a component of the security label for the second record; and assigning a value for the component of the security label for the first record based on the identified component of the security label for the second record. The method includes storing the determined security label in the record.

Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.

Abstract: A storage system and method for automatic data phasing are disclosed. In one embodiment, a storage system is configured to receive, from a host, data to be written in the memory and an indication of an expected lifespan of the data; and determine whether to perform a garbage collection operation on the data based on the expected lifespan of the data. Other embodiments are provided.

Abstract: A method of translating a virtual address into a physical memory address in an ARM System Memory Management Unit version 3 (SMMUv3) system includes searching a Configuration Cache memory for a matching tag that matches an associated tag upon receiving the virtual address and the associated tag, and extracting, in a single memory lookup cycle, a matching data field associated with the matching tag when the matching tag is found in the Configuration Cache memory. A matching data field of the Configuration Cache memory includes a matching Stream Table Entry (STE) and a matching Context Descriptor (CD), both associated with the matching tag. The Configuration Cache memory may be configured as a content-addressable memory. The method further includes storing entries associated with a multiple memory lookup cycle virtual address-to-physical address translation into the Configuration Cache memory, each of the entries including a tag, an associated STE and an associated CD.

Abstract: This disclosure generally relates to data delivery in distributed applications. One example method includes identifying a data source associated with a shuffle operation, the data source configured provide data from a data set associated with the shuffle operation; identifying a data sink associated with the shuffle operation, the data sink configured to receive data provided by the data source; associating a shuffler component with the shuffle operation, the shuffler component configured to receive data from the data source and provide the data to the data sink; receiving, by the shuffler component, a first data portion from the data source; providing, by the shuffler component, the first data portion to the data sink; receiving, by the shuffler component, a second data portion from the data source, the second data portion being received from the data source prior to or concurrent with providing the first data portion to the data sink.

Abstract: A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.

Abstract: For each of multiple storage volumes of a distributed storage system, it is determined whether the storage volume has a relatively high potential deduplicability or a relatively low potential deduplicability. Responsive to determining that the storage volume has the relatively high potential deduplicability, a first write flow is executed for each of a plurality of write requests directed to the storage volume, the first write flow utilizing content-based signatures of respective data pages of the storage volume to store the data pages in storage devices of the distributed storage system. Responsive to determining that the storage volume has the relatively low potential deduplicability, a second write flow is executed for each of a plurality of write requests directed to the storage volume, the second write flow utilizing non-content-based signatures of respective data pages of the storage volume to store the data pages in storage devices of the distributed storage system.

Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

Abstract: In a network device, a hash calculator generates a lookup hash value from data fields associated with a packet received by the network device. A compressed lookup key generator generates a compressed lookup key for the packet using the lookup hash value. A content addressable memory (CAM) stores compressed patterns corresponding to compressed lookup keys, uses the compressed lookup key received from the compressed lookup key generator to determine if the received compressed lookup key matches any stored compressed patterns, and outputs an index corresponding to a stored compressed pattern that matches the compressed lookup key. A memory stores uncompressed patterns corresponding to the compressed patterns stored in the CAM, and retrieves an uncompressed pattern using the index output by the CAM. A comparator generate a signal that indicates whether the uncompressed pattern retrieved from the memory matches the data fields associated with the packet.

Abstract: A collection of rules comprising fields that may have wildcard values. The method includes defining first and second subsets of the fields, the second subset being exclusive of the first subset. Intersections of overlapping fields of the first subset are added to the first subset to form an augmented first subset. Metadata from the augmented first subset and the fields not selected for the first subset are combined to define second parts of the rules. Data items are classified by matching a search key to one of the first parts and one of the second parts of the rules.

Abstract: A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Abstract: A framework for memory optimization of database indexes, and in particular for aging full-text index data, is described herein. In one embodiment, if, while a database table is aged, there are index tables associated with the database table, the associated index tables are automatically aged. This way, the system memory footprint will be reduced, leading to reduced cost as less system memory is required to perform remaining operations, and leading to increased performance as more system memory is available for other operations.

Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.

Abstract: Methods, systems, and computer-readable mediums for managing forwarding equivalence class (FEC) hierarchies, including obtaining a forwarding equivalence class (FEC) hierarchy; making a first determination that a first hardware component supports a maximum levels of indirection (MLI) quantity; making a second determination that the FEC hierarchy has a hierarchy height; based on the first determination and the second determination, performing a comparison between the MLI quantity and the hierarchy height to obtain a comparison result; and based on the comparison result, performing a FEC hierarchy action set.

Abstract: A processing device monitors performance of a first thread of a first application executing on one of a plurality of processing cores of a storage system. The first thread comprises an internal scheduler controlling switching between a plurality of sub-threads of the first thread, and an external scheduler controlling release of the processing core by the first thread for use by at least a second thread of a second application different than the first application. In conjunction with monitoring the performance of the first thread in executing the first application, the processing device maintains a cumulative suspend time of the first thread over multiple suspensions of the first thread, with one or more of the multiple suspensions allowing at least the second thread of the second application to execute on the processing core, and generates performance measurements for sub-threads of the first thread using the cumulative suspend time.

Abstract: Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or system calls in the host program corresponding to the different functions then use jump logic to pass function selection values to an accelerator program in the accelerator that inform the accelerator program which function it is being instructed to perform. This jump logic can be generated by an accelerator compiler and then inserted into the host program as a host compiler generates the executable (e.g., the compiled binary) for the host program.

Abstract: Methods, apparatus, and processor-readable storage media for management of unit-based virtual accelerator resources are provided herein. An example computer-implemented method includes obtaining multiple accelerator device resource consumption measurements, wherein the measurements represent multiple accelerator device resource types consumed by one or more accelerator devices over a defined temporal interval; computing a composite unit of measurement of accelerator device resource consumption, attributable to the one or more accelerator devices over the defined temporal interval, by normalizing the multiple accelerator device resource consumption measurements using a scaling factor that is based at least in part on one or more static aspects of the one or more accelerator devices; and outputting the composite unit of measurement to at least one user.

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Abstract: A method is provided for error detection in a ternary content addressable memory, TCAM, preferably in real-time, wherein the error detection is initiated with a read operation at a specified input address (200), wherein an additional random access memory, RAM, is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries (210) which each consist of data and a mask are placed at the same address locations. In addition, a method is provided for error detection in a TCAM, preferably in real-time, wherein the error detection is triggered by the found of searched input key (400) and starts with a read operation at a specified memory address (410), wherein an additional RAM is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries (420) which each consist of data and a mask are placed at the same address locations.

Abstract: A method includes: executing a first process includes receiving an entry that includes a kay and a value, selecting a first list from among a plurality of lists in accordance with a first hash value, adding, to the selected first list, a first identifier in association with the received entry, and storing the received entry in any of a first memory device and a second memory device that is greater in latency than the first memory device; and executing a second process that includes receiving a searching request for a value, selecting the first list based on the first hash value derived from the searching key in the received searching request, obtaining the first identifier from the first list selected in the second process, obtaining the entry associated with the first identifier obtained in the second process, and outputting the value in the entry obtained in the second process.

Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

Abstract: Various systems, processes, and products may be used to filter multicast messages in virtual environments. In one implementation, a multicast filtering address is received by a network adapter. A frequency of use of the multicast filtering address is determined and, based on the frequency of use of the multicast filtering address, the multicast filtering address is stored in either a multicast filtering store of the network adapter or a local filtering store of a respective virtual machine.

Abstract: Method and apparatus are disclosed for cache control in a parallel processing system. The apparatus includes a plurality of application specific engines configured to generate a plurality of commands, a cache array configured to store the plurality of commands, and a cache command controller configured to receive a command asynchronously from an application specific engine in the plurality of application specific engines, update the cache array to include the received command, and validate the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines.

Abstract: An apparatus comprises a set-associative cache comprising a plurality of sets of cache entries, and cache replacement policy storage circuitry to store a plurality of local replacement policy entries. Each local replacement policy entry comprises local replacement policy information specific to a corresponding set of the set-associative cache. Cache control circuitry controls replacement of cache entries of the set-associative cache based on the local replacement policy information stored in the cache replacement policy storage circuitry. The cache replacement policy storage circuitry stores local replacement policy entries for a proper subset of sets of the set-associative cache.

Abstract: An apparatus includes a processing device comprising a processor coupled to a memory. The processing device is configured, in conjunction with synchronous replication of at least one logical storage volume between first and second storage systems, to receive a synchronous write request comprising a data page to be written to the logical storage volume, to determine a content-based signature for the data page, and to send the content-based signature from the first storage system to the second storage system. Responsive to receipt in the first storage system of an indication from the second storage system that the data page having the content-based signature is not already present in the second storage system, the processing device is further configured to send the data page from the first storage system to the second storage system. The processing device in some embodiments implements a distributed storage controller of a content addressable storage system.

Abstract: In an example embodiment, a distributed storage system includes a service tier including a service node to receive a request for a logical object comprising binary data and metadata describing the binary data, and a storage tier including a plurality of storage nodes, wherein one or more of the storage nodes is to store the metadata describing the binary data. The distributed storage system also includes a coordination tier to store mapping information identifying the one or more of the storage nodes storing the metadata. The service node is also to receive the mapping information from the coordination tier, to access the metadata describing the binary data from one of the one or more of the storage nodes based on the mapping information, and to return the metadata describing the binary data in a response to the request.

Abstract: In various embodiments, an ordered atomic operation enables a parallel processing subsystem to executes an atomic operation associated with a memory location in a specified order relative to other ordered atomic operations associated with the memory location. A level 2 (L2) cache slice includes an atomic processing circuit and a content-addressable memory (CAM). The CAM stores an ordered atomic operation specifying at least a memory address, an atomic operation, and an ordering number. In operation, the atomic processing circuit performs a look-up operation on the CAM, where the look-up operation specifies the memory address. After the atomic processing circuit determines that the ordering number is equal to a current ordering number associated with the memory address, the atomic processing circuit executes the atomic operation and returns the result to a processor executing an algorithm.

Abstract: Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an) apparatus configured to perform the actions of the methods.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Abstract: A storage system comprises multiple storage nodes each comprising at least one storage device. Each of the storage nodes further comprises a set of processing modules configured to communicate over one or more networks with corresponding sets of processing modules on other ones of the storage nodes. The sets of processing modules of the storage nodes each comprise at least one data module and at least one control module. The storage system is configured to assign portions of a content-based signature space of the storage system to respective ones of the data modules, and to assign portions of a logical address space of the storage system to respective ones of the control modules. The assignment of portions of the logical address space to the control modules is configured to at least partially offset an unbalanced condition between local physical storage capacities of the data modules.

Abstract: A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector-matrix pair of rows, and writing the product to an R-product-j row in the array.

Abstract: A method includes receiving, at a content provisioning system from one or more client devices, one or more requests for file digests stored in respective data stores of a plurality of data stores in a distributed file system. The file digests are distributed across different ones of the plurality of data stores in the distributed file system. The method also includes determining a location of a given one of the requested file digests in one or more of the plurality of data stores and retrieving the given file digest from the determined location. The method further includes shuffling the distribution of the file digests across the plurality of data stores in the distributed file system.

Abstract: Disclosed is a method for accessing a code Static Random Access Memory (SRAM) and an electronic device. The method is applied to an electronic device including a first controller, a code SRAM and an in circuit emulator (ICE); and the method includes: receiving, by the ICE, a first address at which the first controller accesses the code SRAM; transmitting, by the ICE, a first code to the first controller if the first address is the same as a second address, where the second address is an address corresponding to an abnormal address cell in the code SRAM, and the first code is a correct code of the abnormal address cell; or obtaining, by the ICE, a second code corresponding to the first address from the code SRAM, and transmitting the second code to the first controller, if the first address is different from the second address.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for communicating and sharing blockchain data. One of the methods includes sending current state information associated with a current block of a blockchain to one or more shared storage nodes of the blockchain network; sending a hash value to the one of the one or more shared storage nodes for retrieving an account state stored in the historic state tree; receiving the account state in response to sending the hash value; and verifying, by the consensus node, that the account state is part of the blockchain based on the hash value.

Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

Abstract: A semiconductor memory device includes a memory cell including a first memory unit and a second memory unit which are coupled to a complementary bit line pair, an operation controller configured to successively select the first memory unit and the second memory unit, during a read operation which reads data from the memory cell, a first readout unit coupled to one of the bit line pair, and configured to judge a logical value of the data read from the selected first memory unit onto the one of the bit line pair, and a second readout unit coupled to the other of the bit line pair, and configured to judge a logical value of the data read from the selected second memory unit onto the other of the bit line pair.

Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

Abstract: An apparatus for providing fault resilience has storage for providing a plurality of compare data blocks, and processing circuitry that performs, for each compare data block, a processing operation using the input data and the compare data block to produce a match condition indication for that compare data block. Performance of the processing operation for each compare data block should result in only one match condition indication indicating a match. Evaluation circuitry evaluates the match condition indications produced for the plurality of compare data blocks and is arranged, in the presence of only one match condition indication indicating a match, to perform a false hit check procedure in order to check for presence of a false hit. In the presence of the false hit, the evaluation circuitry produces an error indication as the outcome indication, but otherwise produces a hit indication as the outcome indication.

Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a system to create and employ associative memory maps for analysis of security file and/or logs are disclosed. In one aspect, a method includes the actions of receiving, from an external application, a request for a recommended action; extracting information regarding the entities and relationships between the entities from a data source; constructing an associative memory map from the extracted information; selecting a subgraph from the associative memory map based on a result of employing a vector to search nodes in the associative memory map; identifying the nodes most relevant to the requested recommend action base on a shortest paths of traversal in the selected subgraph of nodes; determining the requested recommended action based on an event identified in the relationships between the identified most relevant nodes; and transmitting the recommended action to the external application.

Abstract: Certain hash-based operations in network devices and other devices, such as mapping and/or lookup operations, are improved by manipulating a hash key prior to executing a hash function on the hash key and/or by manipulating outputs of a hash function. A device may be configured to manipulate hash keys and/or outputs using manipulation logic based on one or more predefined manipulation values. A similar hash-based operation may be performed by multiple devices within a network of computing devices. Different devices may utilize different predefined manipulation values for their respective implementations of the manipulation logic. For instance, each device may assign itself a random mask value for key transformation logic as part of an initialization process when the device powers up and/or each time the device reboots. In an embodiment, described techniques may increase the entropy of hashing function outputs in certain contexts, thereby increasing the effectiveness of certain hashing functions.

Abstract: A hash content addressable memory system includes a hash content addressable memory block (HCB) that is a physical subsystem of the hash content addressable memory system. The first HCB include first bus select logic. The first bus select logic is connected to a plurality of key buses and to a plurality of operation buses. Each key bus from the plurality of key buses and each operation bus from the plurality of operation buses is connected to one and only one client in a plurality of clients. Every client in the plurality of clients is connected to only one key bus from the plurality of key buses and is connected to only one operation bus from the plurality of operation buses.