Content Addressable Memory (cam) Patents (Class 711/108)
  • Patent number: 10684961
    Abstract: External memory protection may be implemented for content addressable memory (CAM). Memory protection data, such as duplicate values for entries in a CAM or error detection codes generated from values of the entries in a CAM, may be stored in a random access memory that is separate from the CAM. When an entry in the CAM is accessed to perform a lookup or scrubbing operation, the memory protection data may be obtained from the RAM. A validation of the value of the entry may then be performed according to the memory protection data to determine whether the value is valid.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 16, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Kiran Kalkunte Seshadri, Thomas A. Volpe
  • Patent number: 10637662
    Abstract: A computer-implemented method comprising: receiving, by a computing device, biometrics data of a user via a user device as part of a request to access a secure device; applying, by the computing device, a non-invertible function to the biometrics data to scramble the biometrics data; determining, by the computing device, whether the scrambled biometrics data matches a pre-registered version of the scrambled biometrics data; and providing, by the computing device, an authentication message to the secure device requesting authentication of the user based on determining that the scrambled biometrics data matches the pre-registered version of the scrambled biometrics data, wherein the providing the authentication message provides a user of the user device with access to the secure device.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aaron K. Baughman, Charles E. Beller, Sean M. Fuoco, Chennakesavalu Govindasamy, Palani Sakthi
  • Patent number: 10601699
    Abstract: Aspects of the present disclosure involve systems for providing multiple egress routes from a telecommunications network for a client of the network. In general, the system provides for a client of the network to receive intended packets of information through multiple connections to the network such that load balancing and failover services for traffic to the customer are provided. The process and system allows for telecommunications network to utilize a common next-hop value of announced border gateway protocol (BGP) routes to advertise multiple routes to reach a destination customer network or address. By utilizing a common next-hop value in the announced BGP information, the devices of the network may load balance communication packets to the destination customer or address among the multiple egress locations from the network, as well as providing fast failover to alternate routes when a failure at the network or customer occurs.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 24, 2020
    Assignee: Level 3 Communications, LLC
    Inventors: Francis Ferguson, Eric Osborne, Clyde David Cooper, III, Brent W. Smith
  • Patent number: 10594704
    Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
  • Patent number: 10581796
    Abstract: Examples relate to the configuration of network connections for computing devices. In some examples, a computing device determines that a network is inaccessible through a first network connection provided by a network access node. The computing device determines that the network is accessible through a first computing device that provides a second connection to the network. The computing device generates gateway configuration data for a second computing device based on an address for the first computing device. The computing device transmits the gateway configuration data to the second computing device to cause the second computing device to use the first computing device as a gateway.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: March 3, 2020
    Assignee: AIRWATCH LLC
    Inventors: Suman Aluvala, Mahesh Kavatage, Pavan Rajkumar Rangain, Niranjan Paramashivaiah
  • Patent number: 10528399
    Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Fredrickson, John Borkenhagen, Michael A. Muston, Spencer K. Millican, John D. Irish
  • Patent number: 10529426
    Abstract: A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data; using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size; and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 7, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Sung-Yao Lin, Yueh-Pu Kuo, Yu-Min Hsiao
  • Patent number: 10521143
    Abstract: Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: December 31, 2019
    Assignee: NetApp Inc.
    Inventors: Ananthan Subramanian, Sriram Venketaraman, Ravikanth Dronamraju, Mohit Gupta
  • Patent number: 10498645
    Abstract: A system including first and second information handling systems may implement: a virtual bridge associated with a network information handling resource, a virtual machine to access the resources of the first information handling system; a virtualization environment to migrate the virtual machine from the first to the second information handling system using the virtual bridge; a first virtual function mapping the network information handling resource and the first information handling system; a second virtual function mapping the network information handling resource and the second information handling system; and a physical function mapping the network information handling resource and a chassis management controller. The physical function may be a Peripheral Component Interconnect Express (PCIe) I/O Virtualization (IOV) physical function.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: December 3, 2019
    Assignee: Dell Products, L.P.
    Inventors: Babu Chandrasekhar, Michael Brundridge, Syama Poluri, William Lynn
  • Patent number: 10489455
    Abstract: A scoped search engine is disclosed. The scoped search engine includes a memory unit storing reference data records. The scoped search engine also includes a data comparison unit that searches the reference data records using different searches. The scoped search engine further includes a match analysis unit that combines result data from the different searches and determines a scope for a subsequent search based on the combined result data.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Samuel S. Adams, Igor Arsovski, Suparna Bhattacharya, John M. Cohn, Gary P. Noble, Krishnan S. Rengarajan
  • Patent number: 10453171
    Abstract: A processor is configured to store color component values associated with a first subset of vertices of a three-dimensional (3-D) look up table (LUT) in a first subset of memory elements. The color component values are defined according to a destination gamut. A data select module is configured to access the color component values from the first subset of the memory elements concurrently with the processor storing color component values associated with a second subset of the vertices of the 3-D LUT in a second subset of the memory elements. The data select module is configured to access the color component values from the first and second subsets of the memory elements in response to the processor storing the color component values associated with the second subset of the vertices of the 3-D LUT in the second subset of the memory elements. This process can be extended to additional subsets.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 22, 2019
    Assignee: ATI Technologies ULC
    Inventors: Yuxin Chen, Chun-Chin Yeh
  • Patent number: 10437802
    Abstract: The present disclosure relates to a system and methods of implementing an integer-value database using a single I/O operation. In particular, the present disclosure relates to methods of writing and reading information to a database using key/value pairs, including receiving, at a database management system, a value to be written to a database, the database including a plurality of segments stored on a storage medium, and assigning, by the database management system, an assigned key to the value based on keys previously used in the database. The method may further include storing, by the database management system, the assigned key and the value to a segment at a virtual end of the database, wherein the segment is identified in a mapping index by an offset and the mapping index identifies a first key in the segment, and returning the assigned key.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 8, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Frederik Jacqueline Luc De Schrijver
  • Patent number: 10409672
    Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: David J Pignatelli, Fan Zhang, Yu Cai
  • Patent number: 10397115
    Abstract: One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Naader Hasani, Shishir Gupta, David Delano Ward, Mohammed Ismael Tatar, Shahin Habibi, Sreedhar Ravipalli, David Richard Barach
  • Patent number: 10387311
    Abstract: A cache structure implemented in a microprocessor core include a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets containing cache line information, and outputs a first set-ID indicative of an individual predictor data set. The logical directory contains a plurality of logical data sets containing cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ute Gaertner, Christian Jacobi, Gregory Miaskovsky, Martin Recktenwald, Timothy Slegel, Aaron Tsai
  • Patent number: 10382597
    Abstract: Disclosed is a system and method of providing transport-level identification and isolation of container traffic. The method includes receiving, at a component in a network, a packet having a data field, extracting, at a network layer, container identification data from the data field and applying a policy to the packet at the component based on the container identification data. The data field can include one of a header, an IPv6 extension header, a service function chaining container identification, a network service header, and an optional field of an IPv4 packet.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 13, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sebastian Jeuk, Gonzalo Salgueiro
  • Patent number: 10372579
    Abstract: A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Artesyn Embedded Computing, Inc.
    Inventors: Gary Perkins, Malcolm J. Rush, Andrew Porter
  • Patent number: 10340007
    Abstract: Various examples are provided examples related to resistive content addressable memory (RCAM) based in-memory computation architectures. In one example, a system includes a content addressable memory (CAM) including an array of cells having a memristor based crossbar and an interconnection switch matrix having a gateless memristor array, which is coupled to an output of the CAM. In another example, a method, includes comparing activated bit values stored a key register with corresponding bit values in a row of a CAM, setting a tag bit value to indicate that the activated bit values match the corresponding bit values, and writing masked key bit values to corresponding bit locations in the row of the CAM based on the tag bit value.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 2, 2019
    Assignees: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Khaled Nabil Salama, Mohammed Affan Zidan, Fadi J. Kurdahi, Ahmed Eltawil, Hasan Erdem Yantir
  • Patent number: 10318587
    Abstract: An algorithmic TCAM based ternary lookup method is provided. The method stores entries for ternary lookup into several sub-tables. All entries in each sub-table have a sub-table key that includes the same common portion of the entry. No two sub-tables are associated with the same sub-table key. The method stores the keys in a sub-table keys table in TCAM. Each key has a different priority. The method stores the entries for each sub-table in random access memory. Each entry in a sub-table has a different priority. The method receives a search request to perform a ternary lookup for an input data item. A ternary lookup into the ternary sub-table key table stored in TCAM is performed to retrieve a sub-table index. The method performs a ternary lookup across the entries of the sub-table associated with the retrieved index to identify the highest priority matched entry for the input data item.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 11, 2019
    Assignee: BAREFOOT NETWORKS, INC.
    Inventors: Patrick Bosshart, Michael G. Ferrara, Jay E. S. Peterson
  • Patent number: 10303544
    Abstract: A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: May 28, 2019
    Inventors: Jay E. S. Peterson, Patrick Bosshart, Michael G. Ferrara
  • Patent number: 10296457
    Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Ruchira Sasanka, Rajat Agarwal
  • Patent number: 10289752
    Abstract: A processor may include a gather-update-scatter accelerator, and an allocator comprising circuitry to direct an instruction to the accelerator for execution. The instruction may include a search index, an operation to be performed, and a scalar data value. The accelerator may include a content-addressable memory (CAM) storing multiple entries, each of which stores a respective index key and a data value associated with the index key. The accelerator may include a CAM controller, which includes circuitry. The CAM controller may be configured to select, based on the information in the instruction, one of the plurality of entries in the CAM on which to operate. The CAM controller may be configured to perform an arithmetic or logical operation on the selected entry dependent on the information in the instruction. The CAM controller may be configured to store a result of the operation in the selected entry in the CAM.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Ganesh Venkatesh, Nicholas P. Carter, Deborah T. Marr
  • Patent number: 10276251
    Abstract: A memory system performs verification when writing to memory. It is possible that the memory system may be missing some components (or components may be otherwise unavailable). To account for missing or unavailable components when performing verification, the memory system uses a pattern of data that includes a mask identifying the missing or unavailable components. The mask is used to force a predetermined result of the verification for the missing or unavailable portions of the memory structure so that results of the verification that correspond to the missing or unavailable components are not counted as errors.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Sukhminder Singh Lobana, Kirubakaran Periyannan, Ankitkumar Babariya
  • Patent number: 10243590
    Abstract: A ternary content addressable memory (TCAM) may implement complete detection of single and double bit errors for entries. A single error correction double error detection (SECDED) error correction code may be generated and maintained for each entry in the TCAM. The SECDED error correction code may be generated from the parity bit and bits that indicate don't?care conditions in memory cells storing a value for an entry in the TCAM. When an entry of the TCAM is accessed, the value of the entry may be validated with respect to the SECDED error correction code. All single bit errors and double bit errors in the value or data stored for the value, such as a parity bit or value bit, may be detected. All single bit errors and some double bit errors may be corrected.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: March 26, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Kiran Kalkunte Seshadri
  • Patent number: 10223279
    Abstract: A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 5, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson
  • Patent number: 10210170
    Abstract: Deduplication is integrated with software building and chunk storing. A dedup module includes dedup software, a build graph interface, and a chunk store interface. A dedup graph includes a portion of the build graph, and a portion that represents build artifact file chunks. The dedup software queries whether chunks are present in the chunk store, submits a chunk for storage when the chunk is not already present, and avoids submitting the chunk when it is present. Queries may use hash comparisons, a hash tree dedup graph, chunk expiration dates, content addressable chunk store memory, inference of a child node's presence, recursion, and a local cache of node hashes and node expiration dates, for example. A change caused by the build impacts fewer dedup graph nodes than directory graph nodes, resulting in fewer storage operations to update the chunk storage with new or changed build artifacts.
    Type: Grant
    Filed: January 28, 2017
    Date of Patent: February 19, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Lars Kuhtz, John Thomas Erickson, Sudipta Sengupta, Vinod Sridharan, Xianzheng Dou, Wolfram Schulte
  • Patent number: 10210092
    Abstract: Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 19, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
  • Patent number: 10212082
    Abstract: In one embodiment, packets are forwarded in a network based on lookup results in a content-addressable memory that includes multiple blocks of content-addressable memory entries, with the relative priority of these blocks typically determined on a per search basis. In one embodiment, the content-addressable memory blocks perform lookup operations based on a search key resulting in a lookup results. The result determiner determines an overall highest-priority content-addressable memory lookup result based on ordering the lookup results according to a dynamic priority ordering (e.g., retrieved from storage) among the content-addressable memory blocks. One embodiment allows multiple searches to occur simultaneously among the content-addressable memory blocks by selectively performing lookup operations on multiple search keys.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: February 19, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Doron Shoham, Sivan Avraham
  • Patent number: 10204685
    Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, Suparna Bhattacharya, Arvind Kumar
  • Patent number: 10175902
    Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc..
    Inventors: David Matthew Springberg, Matthew David Rowley, Peter Edward Kaineg
  • Patent number: 10147467
    Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Tiwari
  • Patent number: 10140220
    Abstract: A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: November 27, 2018
    Inventor: Bertrand F. Cambou
  • Patent number: 10102264
    Abstract: The distributed computing backup and recovery (DCBR) system and method provide backup and recovery for distributed computing models (e.g., NoSQL). The DCBR system extends the protections from server node-level failure and introduces persistence in time so that the evolving data set may be stored and recovered to a past point in time. The DCBR system, instead of performing backup and recovery for an entire dataset, may be configured to apply to a subset of data. Instead of keeping or recovering snapshots of the entire dataset which requires the entire cluster, the DCBR system identifies the particular nodes and/or archive files where the dataset resides so that backup or recovery may be done with a much smaller number of nodes.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 16, 2018
    Assignee: Accenture Global Services Limited
    Inventors: Teresa Tung, Sameer Farooqui, Owen Richter
  • Patent number: 10095624
    Abstract: An intelligent cache pre-fetch system includes a pre-fetch throttling scheme to monitor a cache hit rate context. Pre-fetch reads of additional data are only launched when the context is below a given threshold. A pre-fetch read of additional data can be selectively initiated after determining that references to neighboring segments related to a compression region already in memory are not yet present in the cache. Additional throttling of pre-fetch reads can be accomplished by only initiating the selective pre-fetch of additional data after determining whether the compression region to which the neighboring segments are related is a hot region, where a hot region is characterized as a compression region having data that is accessed frequently as compared to data in other compression regions.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 9, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Satish Kumar Kashi Visvanathan, Rahul Ugale
  • Patent number: 10097378
    Abstract: Various systems and methods for implementing efficient TCAM resource sharing are described herein. Entries are allocated across a plurality of ternary content addressable memories (TCAMs), with the plurality of TCAMs including a primary TCAM and a secondary TCAM, where the entries are allocated by sequentially accessing a plurality of groups of value-mask-result (VMR) entries, with each group having at least one VMR entry associated with the group, and iteratively analyzing the VMR entries associated with each group to determine a result set of VMR entries, with the result set being a subset of VMR entries from the plurality of groups of VMR entries, and the result set to be stored in the primary TCAM.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 9, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Xuanming Dong, Vijaya Kumar Kulkarni, Cesare Cantù
  • Patent number: 10091226
    Abstract: The present invention relates to a multicore communication processing service. More specifically, aspects of the present invention provide a technology for converting a plurality of data packet units into one jumbo frame unit, copying the converted jumbo frame to a plurality of dual in-line memories (DIMMs) by logical distribution, and computing the jumbo frame through each CPU including multicore processors corresponding to the plurality of DIMM channels, thereby reducing the number of packets per second and securing efficiency in memories and CPU resources, and also adding/removing a header field for each data packet included in the jumbo frame according to a path transmitted or received from a network interface card (NIC) of the jumbo frame or processing the data packet using the header field only, thereby minimizing packet receive event and reducing context switching generated upon the packet receive event, which results in improvement of jumbo frame processing performance.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: October 2, 2018
    Assignee: WINS CO., LTD.
    Inventor: Young Kook Noh
  • Patent number: 10062429
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Bhushan Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu
  • Patent number: 10025716
    Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gostin, Craig Warner, John W Bockhaus
  • Patent number: 10019175
    Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 9984134
    Abstract: An extraction device for extracting a sub query to be converted to a program for processing stream data continuously inputted to a database, from a query including instructions, as sub queries, to be issued to a database management system. The extraction device includes: an input unit; an operation unit for calculating the memory increase amount in a case of processing the stream data and the processing time to be reduced for each sub query, and calculating the efficiency by using them; and an extraction unit for selecting at least one sub query whose efficiency is equal to or higher than the lower limit value, integrating the memory increase amount calculated for the selected sub query, and on condition that the integrated memory increase amount is equal to or smaller than the maximum memory increase amount, extracting the selected sub query as a conversion object.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Haruki Imai, Hideaki Komatsu, Akira Koseki, Toshiro Takase
  • Patent number: 9977734
    Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 22, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Daisuke Hashimoto
  • Patent number: 9971629
    Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9965821
    Abstract: A system and method for constructing binary radix trees in parallel, which are used for as a building block for constructing secondary trees. A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method is disclosed. The method includes determining a plurality of primitives comprising a total number of primitive nodes that are indexed, wherein the plurality of primitives correspond to leaf nodes of a hierarchical tree. The method includes sorting the plurality of primitives. The method includes building the hierarchical tree in a manner requiring at most a linear amount of temporary storage with respect to the total number of primitive nodes. The method includes building an internal node of the hierarchical tree in parallel with one or more of its ancestor nodes.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: May 8, 2018
    Assignee: NVIDIA CORPORATION
    Inventor: Tero Karras
  • Patent number: 9958924
    Abstract: According to one example embodiment, a modem or other network device include an energy module configured to enter a low-power, low-bandwidth state when not in active use by a user. The low-power state may be maintained under certain conditions where network activity is not present, and or when only non-bandwidth-critical traffic is present. The network device may include a user interface for configuring firewall rules, and the user may be able to concurrently designate particular types of traffic as important or unimportant. The energy module may also be integrated with a firewall, and power saving rules may be inferred from firewall rules.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: May 1, 2018
    Assignee: Cisco Technology, Inc.
    Inventor: Michael Overcash
  • Patent number: 9952933
    Abstract: Various systems, methods, and processes for caching and referencing multiple fingerprints while data operations are ongoing are disclosed. A first fingerprint is generated based on a first fingerprinting process. The first fingerprint is stored in association with a second fingerprint, which is based on a second fingerprinting process. The first fingerprint and the second fingerprint are associated with the same data segment. Data operations such as a backup operation, a restore operation, or a replication operation can be performed while the conversion of the data segment from the second fingerprint to the first fingerprint is ongoing.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 24, 2018
    Assignee: Veritas Technologies LLC
    Inventors: Xianbo Zhang, Haigang Wang
  • Patent number: 9940191
    Abstract: A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.
    Type: Grant
    Filed: November 21, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Bartholomew Blaner
  • Patent number: 9934031
    Abstract: A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Andrey Naraikin, Christopher J. Hughes
  • Patent number: 9906548
    Abstract: A method to augment a plurality of IPS or SIEM evidence information is provided. The method may include monitoring a plurality of processes associated with a computer system. The method may also include identifying a plurality of processes that have network activity. The method may further include capturing the identified plurality of processes that have network activity. The method may also include storing the identified captured plurality of processes that have network activity. The method may include monitoring a plurality of selected programs associated with an operating system of the computer system. The method may also include identifying a plurality of selected programs that have network activity. The method may further include capturing a plurality of screen capture images associated with the identified plurality of selected programs. The method may include storing, by the second component the captured plurality of system process activity.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chien Pang Lee, Hariharan Mahadevan
  • Patent number: 9906547
    Abstract: A method to augment a plurality of IPS or SIEM evidence information is provided. The method may include monitoring a plurality of processes associated with a computer system. The method may also include identifying a plurality of processes that have network activity. The method may further include capturing the identified plurality of processes that have network activity. The method may also include storing the identified captured plurality of processes that have network activity. The method may include monitoring a plurality of selected programs associated with an operating system of the computer system. The method may also include identifying a plurality of selected programs that have network activity. The method may further include capturing a plurality of screen capture images associated with the identified plurality of selected programs. The method may include storing, by the second component the captured plurality of system process activity.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chien Pang Lee, Hariharan Mahadevan
  • Patent number: 9899088
    Abstract: Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 20, 2018
    Assignee: XILINX, INC.
    Inventor: Weirong Jiang