Abstract: An algorithmic TCAM based ternary lookup method is provided. The method stores entries for ternary lookup into several sub-tables. All entries in each sub-table have a sub-table key that includes the same common portion of the entry. No two sub-tables are associated with the same sub-table key. The method stores the keys in a sub-table keys table in TCAM. Each key has a different priority. The method stores the entries for each sub-table in random access memory. Each entry in a sub-table has a different priority. The method receives a search request to perform a ternary lookup for an input data item. A ternary lookup into the ternary sub-table key table stored in TCAM is performed to retrieve a sub-table index. The method performs a ternary lookup across the entries of the sub-table associated with the retrieved index to identify the highest priority matched entry for the input data item.

Abstract: A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.

Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

Abstract: A processor may include a gather-update-scatter accelerator, and an allocator comprising circuitry to direct an instruction to the accelerator for execution. The instruction may include a search index, an operation to be performed, and a scalar data value. The accelerator may include a content-addressable memory (CAM) storing multiple entries, each of which stores a respective index key and a data value associated with the index key. The accelerator may include a CAM controller, which includes circuitry. The CAM controller may be configured to select, based on the information in the instruction, one of the plurality of entries in the CAM on which to operate. The CAM controller may be configured to perform an arithmetic or logical operation on the selected entry dependent on the information in the instruction. The CAM controller may be configured to store a result of the operation in the selected entry in the CAM.

Abstract: A memory system performs verification when writing to memory. It is possible that the memory system may be missing some components (or components may be otherwise unavailable). To account for missing or unavailable components when performing verification, the memory system uses a pattern of data that includes a mask identifying the missing or unavailable components. The mask is used to force a predetermined result of the verification for the missing or unavailable portions of the memory structure so that results of the verification that correspond to the missing or unavailable components are not counted as errors.

Abstract: A ternary content addressable memory (TCAM) may implement complete detection of single and double bit errors for entries. A single error correction double error detection (SECDED) error correction code may be generated and maintained for each entry in the TCAM. The SECDED error correction code may be generated from the parity bit and bits that indicate don't?care conditions in memory cells storing a value for an entry in the TCAM. When an entry of the TCAM is accessed, the value of the entry may be validated with respect to the SECDED error correction code. All single bit errors and double bit errors in the value or data stored for the value, such as a parity bit or value bit, may be detected. All single bit errors and some double bit errors may be corrected.

Abstract: A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.

Abstract: Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.

Abstract: In one embodiment, packets are forwarded in a network based on lookup results in a content-addressable memory that includes multiple blocks of content-addressable memory entries, with the relative priority of these blocks typically determined on a per search basis. In one embodiment, the content-addressable memory blocks perform lookup operations based on a search key resulting in a lookup results. The result determiner determines an overall highest-priority content-addressable memory lookup result based on ordering the lookup results according to a dynamic priority ordering (e.g., retrieved from storage) among the content-addressable memory blocks. One embodiment allows multiple searches to occur simultaneously among the content-addressable memory blocks by selectively performing lookup operations on multiple search keys.

Abstract: Deduplication is integrated with software building and chunk storing. A dedup module includes dedup software, a build graph interface, and a chunk store interface. A dedup graph includes a portion of the build graph, and a portion that represents build artifact file chunks. The dedup software queries whether chunks are present in the chunk store, submits a chunk for storage when the chunk is not already present, and avoids submitting the chunk when it is present. Queries may use hash comparisons, a hash tree dedup graph, chunk expiration dates, content addressable chunk store memory, inference of a child node's presence, recursion, and a local cache of node hashes and node expiration dates, for example. A change caused by the build impacts fewer dedup graph nodes than directory graph nodes, resulting in fewer storage operations to update the chunk storage with new or changed build artifacts.

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.

Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.

Abstract: A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array.

Abstract: The distributed computing backup and recovery (DCBR) system and method provide backup and recovery for distributed computing models (e.g., NoSQL). The DCBR system extends the protections from server node-level failure and introduces persistence in time so that the evolving data set may be stored and recovered to a past point in time. The DCBR system, instead of performing backup and recovery for an entire dataset, may be configured to apply to a subset of data. Instead of keeping or recovering snapshots of the entire dataset which requires the entire cluster, the DCBR system identifies the particular nodes and/or archive files where the dataset resides so that backup or recovery may be done with a much smaller number of nodes.

Abstract: An intelligent cache pre-fetch system includes a pre-fetch throttling scheme to monitor a cache hit rate context. Pre-fetch reads of additional data are only launched when the context is below a given threshold. A pre-fetch read of additional data can be selectively initiated after determining that references to neighboring segments related to a compression region already in memory are not yet present in the cache. Additional throttling of pre-fetch reads can be accomplished by only initiating the selective pre-fetch of additional data after determining whether the compression region to which the neighboring segments are related is a hot region, where a hot region is characterized as a compression region having data that is accessed frequently as compared to data in other compression regions.

Abstract: Various systems and methods for implementing efficient TCAM resource sharing are described herein. Entries are allocated across a plurality of ternary content addressable memories (TCAMs), with the plurality of TCAMs including a primary TCAM and a secondary TCAM, where the entries are allocated by sequentially accessing a plurality of groups of value-mask-result (VMR) entries, with each group having at least one VMR entry associated with the group, and iteratively analyzing the VMR entries associated with each group to determine a result set of VMR entries, with the result set being a subset of VMR entries from the plurality of groups of VMR entries, and the result set to be stored in the primary TCAM.

Abstract: The present invention relates to a multicore communication processing service. More specifically, aspects of the present invention provide a technology for converting a plurality of data packet units into one jumbo frame unit, copying the converted jumbo frame to a plurality of dual in-line memories (DIMMs) by logical distribution, and computing the jumbo frame through each CPU including multicore processors corresponding to the plurality of DIMM channels, thereby reducing the number of packets per second and securing efficiency in memories and CPU resources, and also adding/removing a header field for each data packet included in the jumbo frame according to a path transmitted or received from a network interface card (NIC) of the jumbo frame or processing the data packet using the header field only, thereby minimizing packet receive event and reducing context switching generated upon the packet receive event, which results in improvement of jumbo frame processing performance.

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.

Abstract: An extraction device for extracting a sub query to be converted to a program for processing stream data continuously inputted to a database, from a query including instructions, as sub queries, to be issued to a database management system. The extraction device includes: an input unit; an operation unit for calculating the memory increase amount in a case of processing the stream data and the processing time to be reduced for each sub query, and calculating the efficiency by using them; and an extraction unit for selecting at least one sub query whose efficiency is equal to or higher than the lower limit value, integrating the memory increase amount calculated for the selected sub query, and on condition that the integrated memory increase amount is equal to or smaller than the maximum memory increase amount, extracting the selected sub query as a conversion object.

Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.

Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.

Abstract: A system and method for constructing binary radix trees in parallel, which are used for as a building block for constructing secondary trees. A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method is disclosed. The method includes determining a plurality of primitives comprising a total number of primitive nodes that are indexed, wherein the plurality of primitives correspond to leaf nodes of a hierarchical tree. The method includes sorting the plurality of primitives. The method includes building the hierarchical tree in a manner requiring at most a linear amount of temporary storage with respect to the total number of primitive nodes. The method includes building an internal node of the hierarchical tree in parallel with one or more of its ancestor nodes.

Abstract: According to one example embodiment, a modem or other network device include an energy module configured to enter a low-power, low-bandwidth state when not in active use by a user. The low-power state may be maintained under certain conditions where network activity is not present, and or when only non-bandwidth-critical traffic is present. The network device may include a user interface for configuring firewall rules, and the user may be able to concurrently designate particular types of traffic as important or unimportant. The energy module may also be integrated with a firewall, and power saving rules may be inferred from firewall rules.

Abstract: Various systems, methods, and processes for caching and referencing multiple fingerprints while data operations are ongoing are disclosed. A first fingerprint is generated based on a first fingerprinting process. The first fingerprint is stored in association with a second fingerprint, which is based on a second fingerprinting process. The first fingerprint and the second fingerprint are associated with the same data segment. Data operations such as a backup operation, a restore operation, or a replication operation can be performed while the conversion of the data segment from the second fingerprint to the first fingerprint is ongoing.

Abstract: A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.

Abstract: A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.

Abstract: A method to augment a plurality of IPS or SIEM evidence information is provided. The method may include monitoring a plurality of processes associated with a computer system. The method may also include identifying a plurality of processes that have network activity. The method may further include capturing the identified plurality of processes that have network activity. The method may also include storing the identified captured plurality of processes that have network activity. The method may include monitoring a plurality of selected programs associated with an operating system of the computer system. The method may also include identifying a plurality of selected programs that have network activity. The method may further include capturing a plurality of screen capture images associated with the identified plurality of selected programs. The method may include storing, by the second component the captured plurality of system process activity.

Abstract: A method to augment a plurality of IPS or SIEM evidence information is provided. The method may include monitoring a plurality of processes associated with a computer system. The method may also include identifying a plurality of processes that have network activity. The method may further include capturing the identified plurality of processes that have network activity. The method may also include storing the identified captured plurality of processes that have network activity. The method may include monitoring a plurality of selected programs associated with an operating system of the computer system. The method may also include identifying a plurality of selected programs that have network activity. The method may further include capturing a plurality of screen capture images associated with the identified plurality of selected programs. The method may include storing, by the second component the captured plurality of system process activity.

Abstract: Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.

Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.

Abstract: A semiconductor device includes a CPU core, a frequency regulating circuit, and a frequency control circuit. The frequency regulating circuit includes a table. The frequency control circuit provides a clock to the CPU core. The CPU core outputs an operating state signal indicating an operating state of the CPU core. The frequency regulating circuit controls a frequency of the clock based on the table and the operating state signal. Thus it is possible to provide a semiconductor device that allows performance to follow a dynamically changing load.

Abstract: Systems, methods and/or devices that enhance the reliability with which data can be stored in and read from a memory utilize an error indicator, obtained from using one reading threshold voltage for decoding, to adaptively determine the reading threshold voltage(s) used for subsequent decoding attempts. For example, in some implementations, the method includes initiating performance of a first read operation, using a first reading threshold voltage, to obtain a first error indicator, and further includes initiating performance of a second set of additional read operations using two or more second reading threshold voltages, the second reading threshold voltages determined in accordance with the first error indicator, to obtain a second error indicator. In some embodiments, when the first error indicator is greater than a first threshold, a difference between two of the second reading threshold voltages is greater than when the first error indicator is less than a first threshold.

Abstract: A method, non-transitory computer readable medium, and device that assists with file-based host-side caching and application consistent write back includes receiving a write operation on a file from a client computing device. When the file for which the write operation has been received is determined when the file is present in the cache. An acknowledgement is sent back to the client computing device indicating the acceptance of the write operation when the file for which the write operation has been received is determined to be present within the cache. The write-back operation is completed for data present in the cache of the storage management computing device to one of the plurality of servers upon sending the acknowledgement.

Abstract: A method, system, and/or computer program product stores and retrieves payload data using a ternary content addressed memory (TCAM) hybrid memory. TCAM data is transmitted to a context masking device. The TCAM data identifies a type of payload data, and the context masking device masks the TCAM data with a context mask to create a masked TCAM data. One or more processors append the masked TCAM to payload data to create multiple stored units of TCAM-identified payload data in a location addressable store (LAS). The processor(s) receive a request for data. The request includes a masked request TCAM data that identifies a content and context of requested data. An exclusive OR (XOR) chip identifies relevant payload data within the LAS that are within a predefined Hamming distance of the masked request TCAM data. The processor(s) return the relevant payload data within the LAS to the requester.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for providing a memory device with volatile and non-volatile media. A volatile memory medium is on a circuit board configured to be installed on a memory bus of a processor. A non-volatile memory medium is on the same circuit board. A mapping module is configured to selectively store data in either the volatile memory medium or the non-volatile memory medium. The data is provided by way of one or more commands from the processor.

Abstract: In aspect an application may be configured to issue a request to store an object, with the request including an object reference. A delegate may be configured to receive the request to store the object, determine a hosted storage service, from among multiple hosted storage services, and a corresponding access protocol based on the object reference, and store the object in the hosted storage service using the corresponding protocol.

Abstract: A mechanism is provided for object-based storage management. A detection is made of an event being performed on or by the object. A determination is made as to whether the event meets with one or more rules in a set of rules that identify a backup or replication needing to be performed. Responsive to determining that the event meets with one or more rules in the set of rules that identify the backup or replication needing to be performed, an indication is made in a backup/replication field in metadata of the object that the backup and/or replication of the object needs to be performed. The indication in the backup/replication field in the metadata of the object causes one or more portions of the object to be backed up and/or replicated.

Abstract: Provided is a communication method for an administration node in a content centric network (CCN). The communication method includes receiving a packet requesting deletion of an invalid content from a requesting node that detects the invalid content, generating a content revocation list including a name of the invalid content and a period of time over which the deletion is to be performed, and flooding a data packet including the content revocation list to the requesting node and a normal node included in the CCN. Also provided are related communications methods for a receiving node and a normal node, as well as the nodes themselves.

Abstract: In one embodiment, a method includes accessing at least two determinations of the location of a mobile computing device, with each determined location having been determined without reference to explicit location information manually input by a user of the mobile computing device. At least one first determined location is compared with at least one second determined location, with comparisons being made between location determinations made based on different location determination input. A functionality associated with the mobile computing device is allowed if the first determined location corresponds to at least one of the second determined locations.

Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.

Abstract: A semiconductor memory may include a plurality of stacked semiconductor chips which are interconnected using through-chip vias. The semiconductor memory may set chip IDs of the respective semiconductor chips by using a chip code such that the chip IDs are different from each other, and perform a through-chip via test for the plurality of stacked semiconductor chips by changing the chip IDs of the respective semiconductor chips during a test mode period.

Abstract: A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.

Abstract: An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device. The storage device may allocate logical capacity in the logical address space. An allocation request may be allowed when there is sufficient unassigned and/or unallocated logical capacity to satisfy the request. Data may be stored on the non-volatile storage device by requesting physical storage capacity. A physical storage request, such as a storage request or physical storage reservation, when there is sufficient available physical storage capacity to satisfy the request. The device may maintain an index to associate logical identifiers (LIDs) in the logical address space with storage locations on the storage device. This index may be used to make logical capacity allocations and/or to manage physical storage space.

Abstract: Search circuitry responsive to a single instruction for undertaking a step of a search of a data array for an extreme value therein, a method of searching a data array to identify an extreme value therein and a location thereof and a single-instruction, multiple-data (SIMD) processing unit incorporating the search circuitry or the method. In one embodiment, the search circuitry includes: a comparison element configured to compare two values in the data array, (2) multiplexers coupled to the comparison element and configured to select a more extreme value of the two values and a location in the data array of the more extreme value and (3) an incrementer configured to increment a counter associated with the search.

Abstract: A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (CAM) block, a CAM state information storage block suitable for storing information on whether the setting information loaded on the CAM block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the CAM block is requested, the control logic selectively performs the reloading operation based on the information stored the CAM state information storage block.

Abstract: An electronic apparatus includes a storage section, a first generation section, a second generation section, an update section, and an output section. The storage section stores contents, titles thereof, and viewing history information on viewing histories of the contents by a user. The first generation section generates, based on the stored viewing history information, recommendation display information containing as a recommended-content list a list of titles of contents that the user has not viewed among the stored contents. The second generation section generates dependence information on first and second contents among the stored contents by analyzing text information on a network, the second content being created dependently on the first content. The update section updates, based on the dependence information, the recommendation display information so that the user is prevented from viewing the second content before the first content.

Abstract: For digest retrieval based on similarity search in deduplication processing in a data deduplication system using a processor device in a computing environment, input data is partitioned into fixed sized data chunks. Similarity elements and digest block boundaries and digest values are calculated for each of the fixed sized data chunks. Matching similarity elements are searched for in a search structure containing the similarity elements for each of the fixed sized data chunks in a repository of data. Positions of similar data are located in the repository. The positions of the similar data are used to locate and load into the memory stored digest values and corresponding stored digest block boundaries of the similar data in the repository. The digest values and the corresponding digest block boundaries of the input data are matched with the stored digest values and the corresponding stored digest block boundaries to find data matches.