Content Addressable Memory (cam) Patents (Class 711/108)
  • Publication number: 20140215143
    Abstract: Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D. Pickett, Frederick Perner
  • Publication number: 20140215144
    Abstract: Aspects of the disclosure provide a packet processing system. The packet processing system includes a plurality of processing units, a ternary content addressable memory (TCAM) engine, and an interface. The plurality of processing units is configured to process packets received from a computer network, and to perform an action on a received packet. The action is determined responsively to a lookup in a table of rules to determine a rule to be applied to the received packet. The TCAM engine has a plurality of TCAM banks defining respective subsets of a TCAM memory space to store the rules. The interface is configured to selectably associate the TCAM banks to the processing units. The association is configurable to allocate the subsets of the TCAM memory space to groups of the processing units to share the TCAM memory space by the processing units.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 31, 2014
    Applicant: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Lior VALENCY, Aron Wohlgemuth, Gil Levy
  • Publication number: 20140208016
    Abstract: A method includes determining addresses, determining masks, and storing the masks in a ternary content-addressable-memory for matching a candidate address to the masks to determine matches to the addresses. The addresses include an address width and positions, the address width equal to the number of positions. Each mask matches one or more addresses, includes a mask width equal to the address width, and includes matching criteria for determining whether to filter a given address. The matching criteria includes a matching component specifying that an identified position in the address includes a particular value or a wildcard component specifying that an identified position in the address is to be ignored. The masks include at least one mask with a wildcard component. The number of masks is less than the number of the addresses. The number of possible addresses corresponding to the masks is equal to the number of the addresses.
    Type: Application
    Filed: June 24, 2013
    Publication date: July 24, 2014
    Inventors: Yasir Malik, Ali Zaringhalam
  • Patent number: 8787059
    Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: July 22, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Vinay Iyengar
  • Patent number: 8788791
    Abstract: A comparand word is input to a plurality of hash circuits with each hash circuit responding to a different portion of the comparand word. The hash circuit outputs a hash signal which enables or pre-charges portions of a content addressable memory (CAM). The comparand word is also input to the CAM. The CAM compares the comparand word in the pre-charged portions of the CAM and outputs information responsive to the comparison. When Internet addresses are processed, the output information may be port information or an index for locating.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Keith R. Slavin
  • Patent number: 8782367
    Abstract: A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics S.A.
    Inventors: Stéphan Courcambeck, Albert Martinez, Jean Nicolai, William Orlando
  • Patent number: 8775580
    Abstract: Techniques are disclosed for zoning information to be shared with an NPIV proxy device or an NPV device such as a blade switch in a blade chassis. Doing so allows the NPV device to enforce zoning locally for the attached server blades and virtualized systems. The NPV device may learn zoning rules using Fiber Channel name server queries and registered state change notifications. Additionally, the NPV device may snoop name server queries to retrieve zoning information (or state change messages) without using the zoning change protocols and without consuming a Fiber Channel domain from the Fiber Channel fabric.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: July 8, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Madhava Rao Cheethirala, Subrata Banerjee, Raja Rao Tadimeti
  • Patent number: 8776191
    Abstract: Techniques for reducing storage space and detecting corruption in hash-based applications are presented. Data strings are hashed or transformed into numerically represented strings. Groupings of the numeric strings form a set. Each numeric string of a particular set is associated with a unique co-prime number. All the numeric strings and their corresponding co-prime numbers for a particular set are processed using a Chinese Remainder Theorem algorithm (CRT) to produce a single storage value. The single storage value is retained in place of the original numeric strings. The original numeric strings can be subsequently reproduced and verified using the single storage value and the co-prime numbers.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: July 8, 2014
    Assignee: Novell Intellectual Property Holdings, Inc.
    Inventors: Vardhan Itta Vishnu, Hithalapura Basavaraj Puttali
  • Patent number: 8775727
    Abstract: Described embodiments provide a lookup engine that receives lookup requests including a requested key and a speculative add requestor. Iteratively, for each one of the lookup requests, the lookup engine searches each entry of a lookup table for an entry having a key matching the requested key of the lookup request. If the lookup table does not include an entry having a key matching the requested key, the lookup engine sends a miss indication corresponding to the lookup request to the control processor. If the speculative add requestor is set, the lookup engine speculatively adds the requested key to a free entry in the lookup table. Speculatively added keys are searchable in the lookup table for subsequent lookup requests to maintain coherency of the lookup table without creating duplicate key entries, comparing missed keys with each other or stalling the lookup engine to insert missed keys.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Leonid Baryudin, Earl T. Cohen, Kent Wayne Wendorf
  • Patent number: 8775726
    Abstract: A range determination module determines a search range of TCAM content values and a search criteria module creates a TCAM search value from a search range by combining common higher order bits with don't care lower order bits that change within the search range. A match module searches TCAM using the search value to determine a match count. A division module creates upper/lower sub-ranges by creating upper/lower midpoint content values within the search range. Upper sub-range is between an upper content value and the upper midpoint content value and lower sub-range is between the lower midpoint content value and a lower content value. The upper midpoint content value includes changing a most significant don't care bit to a 1 and remaining don't care bits to 0. The lower midpoint content value includes changing a most significant don't care bit to 0 and remaining don't care bits to 1.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machine Corporation
    Inventor: Noriaki Asamoto
  • Patent number: 8767459
    Abstract: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 1, 2014
    Assignee: Apple Inc.
    Inventors: Yoav Kasorla, Naftali Sommer, Eyal Gurgi, Micha Anholt
  • Patent number: 8767488
    Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: July 1, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Publication number: 20140181394
    Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta
  • Publication number: 20140173193
    Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Brian Fahs, Eric T. ANDERSON, Nick Barrow-Williams, Shirish GADRE, Joel James MCCORMACK, Bryon S. NORDQUIST, Nirmal Raj Saxena, Lacky V. Shah
  • Patent number: 8756368
    Abstract: A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: June 17, 2014
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ely K. Tsern
  • Patent number: 8750144
    Abstract: Aspects of the invention provide for updating TCAMs while minimizing TCAM entry updates to add/delete ACL rules. For example, one aspect provides a method for minimizing updates in a router forwarding table, such as a TCAM, including a plurality of rules indexed by priority. This method comprises providing a proposed rule to be added to the router forwarding table, identifying a range of candidate entries in the router forwarding table for the proposed rule, determining a minimum set of rules to relocate, and creating an empty entry in the range of candidate entries based upon the minimum set of rules to relocate. The method may further comprise reallocating the minimum set of rules by, for example, shifting the minimum set of rules in sequence based on priority, and adding the proposed rule to the empty entry in the range of candidate entries.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: June 10, 2014
    Assignee: Google Inc.
    Inventors: Junlan Zhou, Zhengrong Ji
  • Publication number: 20140156924
    Abstract: A semiconductor memory device includes a power block configured to generate an internal voltage based on an external voltage which is applied through a power pad; a circuit block configured to operate according to the internal voltage and drive memory cells; and a CAM (content addressed memory) block configured to operate according to the external voltage and store setting information necessary for driving of the memory cells.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 5, 2014
    Applicant: SK HYNIX INC.
    Inventors: Chun Woo JEON, Hwang HUH
  • Publication number: 20140149655
    Abstract: A system including an associative memory. A first input device in communication with the associative memory is configured to receive comparison criteria associated with a first entity stored in the associative memory. A search engine is configured to acquire, using a processor in conjunction with the associative memory and also using the comparison criteria, an attribute category of the first entity and an attribute value of the first entity. A second input device is configured to input, using the processor in conjunction with the associative memory, the attribute category and the attribute value into a worksheet of the associative memory. A comparator is configured to compare, using the processor in conjunction with the associative memory, the first entity and a second entity. The comparator is further configured to apply the worksheet as part of comparing the first entity and the second entity.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Applicant: THE BOEING COMPANY
    Inventor: The Boeing Company
  • Publication number: 20140149656
    Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 29, 2014
    Applicant: Hicamp Systems, Inc.
    Inventor: David R. Cheriton
  • Patent number: 8730705
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 20, 2014
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 8723878
    Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongkon Bae, Kyuyoung Chung
  • Publication number: 20140122791
    Abstract: An example method includes partitioning a memory element of a router into a plurality of segments having one or more rows, where at least a portion of the one or more rows is encoded with a value mask (VM) list having a plurality of values and masks. The VM list is identified by a label, and the label is mapped to a base row number and a specific number of bits corresponding to the portion encoding the VM list. Another example method includes partitioning a prefix into a plurality of blocks, indexing to a hash table using a value of a specific block, where a bucket of the hash table corresponds to a segment of a ternary content addressable memory of a router, and storing the prefix in a row of the segment.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: John Andrew Fingerhut, Balamurugan Ramaraj
  • Publication number: 20140115249
    Abstract: A thread priority control mechanism is provided which uses the completion event of the preceding transaction to raise the priority of the next transaction in the order of execution when the transaction status has been changed from speculative to non-speculative. In one aspect of the present invention, a thread-level speculation mechanism is provided which has content-addressable memory, an address register and a comparator for recording transaction footprints, and a control logic circuit for supporting memory synchronization instructions. This supports hardware transaction memory in detecting transaction conflicts. This thread-level speculation mechanism includes a priority up bit for recording an attribute operand in a memory synchronization instruction, a means for generating a priority up event when a thread wake-up event has occurred and the priority up bit is 1, and a means for preventing the CAM from storing the load/store address when the instruction is a non-transaction instruction.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Christian Jacobi, Marcel Mitran, Moriyoshi Ohara
  • Publication number: 20140108717
    Abstract: A method and system enable tape back-up of objects stored to an object storage platform and also enable efficient backup to a secondary storage device data objects. An offline-replica bit within a metadata of an object being stored is set to a first value, indicating that the stored object is available for secondary storage to a second storage device. In response to receiving a request for backup of one or more objects from the object storage platform: the storage controller: identifies which objects have an offline-replica bit value that is the first value; and provides only those objects requested that have their offline-replica bit value equal to the first value. An external backup tracking mechanism identifies which objects have been backed-up to the secondary storage, and only those objects that have not previously been backed up are backed up during a subsequent backup request.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: DELL PRODUCTS L.P.
    Inventors: Xiaoyang Tian, Srikanth Nandigam, Wendy Chen
  • Publication number: 20140108718
    Abstract: The present invention discloses a method and an apparatus for setting a TCAM entry and relates to the field of communications, which are used to achieve an objective of improving utilization of a TCAM. The method for setting a TCAM entry includes: acquiring a number set formed by values of same fields in preset packets, where the packets are packets on which a same action needs to be performed, and the number set includes at least two numbers; acquiring a longest continuous mask of the number set; obtaining an acquisition result according to the longest continuous mask of the number set; and storing the acquisition result in a ternary content-addressable memory TCAM entry corresponding to the action. The solutions disclosed in the present invention are applicable to a scenario of setting a TCAM entry.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Zhiwei CHEN, Tao CHEN
  • Patent number: 8694754
    Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: April 8, 2014
    Assignee: OCZ Technology Group, Inc.
    Inventors: Franz Michael Schuette, William Ward Clawson
  • Publication number: 20140095785
    Abstract: A memory architecture power savings system includes a first memory module configured to provide data corresponding to a stored address from among a plurality of stored addresses by comparing the plurality of stored addresses to a search key in response to a control signal. A second memory module is configured to store a plurality of data entries corresponding to truncated portions of the plurality of stored addresses, and to generate the control signal by comparing the plurality of data entries to a truncated portion of the search key.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: Broadcom Corporation
    Inventor: Bindiganavale NATARAJ
  • Publication number: 20140095782
    Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a first search value is associated with a first range field; determining a first bitmap associated with the first search value, wherein the first bitmap indicates at least one range encompassing the first search value; generating a search key based on the first bitmap; and accessing the ternary content addressable memory based on the search key.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Toby J. Koktan, Andre Poulin, Michel Rochon
  • Publication number: 20140095783
    Abstract: Techniques for reducing a number of physical counters are provided. Logical counters may be associated with physical counters. The number of logical counters may be less than the number of physical counters. It may be determined if an association of a logical counter to a physical counter exists already. If not, a new association may be created. The physical counter associated with the logical counter may then be updated.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Steven Glen Jorgensen
  • Publication number: 20140095784
    Abstract: A technique for operating a processor includes translating, using an associated transaction lookaside buffer, a first virtual address into a first physical address through a first entry number in the transaction lookaside buffer. The technique also includes translating, using the transaction lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Thang M. Tran, Edmund J. Gieske
  • Patent number: 8688902
    Abstract: A method includes receiving input data comprising a plurality of bits and processing an access control list into an ESOP expression comprising a plurality of product terms. The method also includes storing a plurality of bits associated with the plurality of product terms in a TCAM comprising a plurality of rows and comparing the plurality of bits associated with the input data to the plurality of bits associated with the product terms stored in each row of the plurality of rows, such that each row of the TCAM outputs a plurality of signals, such that each of the plurality of signals indicate a match or no match for each bit stored in the selected row. The method includes receiving the plurality of signals from the plurality of rows by an ESOP evaluator and outputting an address associated with a selected row from the plurality of rows of the TCAM.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Limited
    Inventors: Stergios Stergiou, Jawahar Jain
  • Patent number: 8688903
    Abstract: An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Sandia Corporation
    Inventors: Karl Scott Hemmert, Keith D. Underwood
  • Patent number: 8688962
    Abstract: Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of data elements in response to a gather instruction. The apparatus includes memory comprising a plurality of memory rows including a memory row associated with the gather instruction. The apparatus further includes memory structure to store data element addresses accessed in response to the gather instruction.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Robert Valentine
  • Publication number: 20140089578
    Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Noriaki Asamoto
  • Patent number: 8683177
    Abstract: A content addressable memory (CAM) (100) can include a CAM memory array (102) having both a data field (102-0) and a mask field (102-1). A multiplexer (MUX) (108) can selectively load data from either a register (104) or an external data input (106) to one or both fields (102-0 and 102-1) of CAM memory array (102).
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 25, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Scott Smith
  • Publication number: 20140082273
    Abstract: A CAS data storage system replicates data on a non-CAS storage device. The CAS storage device recognizes duplicate data and stores the data only once, whereas the non-CAS device does not recognize duplication of data and requires full storage of the data. The CAS data storage device saves on redundant data transfer by transferring, in the case of duplicate data, the address of a primary location at which the data is stored and the address of the current duplication. The CAS data storage system includes a hash?address table for this purpose. The non-CAS storage device then copies its own data from the primary location into the current location.
    Type: Application
    Filed: September 20, 2012
    Publication date: March 20, 2014
    Applicant: XtremlO Ltd.
    Inventor: Yaron SEGEV
  • Publication number: 20140075108
    Abstract: Various systems and methods for implementing efficient TCAM resource sharing are described herein. Entries are allocated across a plurality of ternary content addressable memories (TCAMs), with the plurality of TCAMs including a primary TCAM and a secondary TCAM, where the entries are allocated by sequentially accessing a plurality of groups of value-mask-result (VMR) entries, with each group having at least one VMR entry associated with the group, and iteratively analyzing the VMR entries associated with each group to determine a result set of VMR entries, with the result set being a subset of VMR entries from the plurality of groups of VMR entries, and the result set to be stored in the primary TCAM.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: Cisco Technology, Inc.
    Inventors: Xuanming Dong, Vijaya Kumar Kulkarni, Cesare Cantú
  • Publication number: 20140068173
    Abstract: A digital system may utilize a serial content-addressable memory (CAM), capable of performing greater than, less than and/or equal comparisons between its contents and serially inputted data records according to a type of each data record, to select software routine addresses and associated parameters. The system may also include a scheduler, which may select one or more available processors to execute the software routines on the data records.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventor: Laurence H. COOKE
  • Publication number: 20140068175
    Abstract: A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Inventors: David Kaplan, John M. King
  • Publication number: 20140068176
    Abstract: Described embodiments provide a lookup engine that receives lookup requests including a requested key and a speculative add requestor. Iteratively, for each one of the lookup requests, the lookup engine searches each entry of a lookup table for an entry having a key matching the requested key of the lookup request. If the lookup table does not include an entry having a key matching the requested key, the lookup engine sends a miss indication corresponding to the lookup request to the control processor. If the speculative add requestor is set, the lookup engine speculatively adds the requested key to a free entry in the lookup table. Speculatively added keys are searchable in the lookup table for subsequent lookup requests to maintain coherency of the lookup table without creating duplicate key entries, comparing missed keys with each other or stalling the lookup engine to insert missed keys.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventors: Leonid Baryudin, Earl T. Cohen, Kent Wayne Wendorf
  • Publication number: 20140068174
    Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and the mask size to select a first portion of the IV. The first portion of the IV and the base address value are summed to generate a memory address. The memory address is used to read a word containing multiple result values and multiple reference values from memory. A second portion of the IV is compared with each reference value using a comparator circuit. A result value associated with the matching reference value is selected using a multiplexing circuit and a select value generated by the comparator circuit. The TM sends the selected result value to the processor.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Publication number: 20140068177
    Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: LSI CORPORATION
    Inventor: Ramprasad Raghavan
  • Publication number: 20140059289
    Abstract: In one embodiment, multiple content-addressable memory entries are associated with each other to effectively form a batch content-addressable memory entry that spans multiple physical entries of the content-addressable memory device. To match against this content-addressable memory entry, multiple lookup operations are required—i.e., one lookup operation for each combined physical entry. Further, one embodiment provides that a batch content-addressable memory entry can span one, two, three, or more physical content-addressable memory entries, and batch content-addressable memory entries of varying sizes could be programmed into a single content-addressable memory device. Thus, a lookup operation might take two lookup iterations on the physical entries of the content-addressable memory device, with a next lookup operation taking a different number of lookup iterations (e.g., one, three or more).
    Type: Application
    Filed: August 26, 2012
    Publication date: February 27, 2014
    Applicant: Cisco Technology, Inc. a corporation of California
    Inventors: Doron Shoham, Ilan Lisha, Yossi Socoletzky
  • Publication number: 20140059288
    Abstract: In one embodiment, batch entries include multiple content-addressable memory (CAM) entries, and CAM entries are allowed to be shared among different batch entries. For example, two or more batch entries might have a common set of bits (e.g., representing an address, an address prefix, etc.). Rather than consuming bits of multiple CAM entries, a single CAM entry can be programmed with this common information. Other CAM entries associated with different batch entries are programmed with the distinguishing/different values. A batch lookup operation on a batch entry of two or more CAM entries requires multiple lookup operations on the CAM entries. One embodiment uses a batch mask vector to provide information to decode what CAM entries are shared among which batch entries during a series of lookup operations, which can be performed in one or both directions through the CAM entries.
    Type: Application
    Filed: August 26, 2012
    Publication date: February 27, 2014
    Applicant: Cisco Technology, Inc. a corporation of California
    Inventors: Doron Shoham, Shimon Listman
  • Patent number: 8645404
    Abstract: A split data word including a portion of each of two word-aligned data words stored at two word-aligned address boundaries within a memory is read from a displaced-read memory address relative to the word-aligned address boundaries within the memory. The portions of each of the two word-aligned data words within the split data word are compared with corresponding portions of a word-aligned search pattern. A determination is made that a potential complete match for the word-aligned search pattern exists within at least one of the two word-aligned data words based upon an identified match of at least one of the portions of the two word-aligned data words within the split data word with a corresponding at least one portion of the word-aligned search pattern.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: K. S. Sadananda Aithal, Ajay K. Sami
  • Patent number: 8645620
    Abstract: An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peter Buchmann, Martin Leo Schmatz, Jan Van Lunteren
  • Patent number: 8645621
    Abstract: A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n<m. The method also includes mapping the at least one signal for each logical block to physical block from a corresponding a set of r+1 physical blocks, each set of r+1 physical blocks being different from one another.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: February 4, 2014
    Assignee: NetLogic Microsystems
    Inventor: Dinesh Maheshwari
  • Publication number: 20140032831
    Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Noriaki Asamoto
  • Publication number: 20140032832
    Abstract: An apparatus includes a range determination module that determines a search range of TCAM content values and a search criteria module that creates a TCAM search value from a search range by combining common higher order bits with don't care lower order bits that change within the search range. A match module searches the TCAM using the search value to determine a match count. A division module creates upper and lower sub-ranges by creating upper and lower midpoint content values within the search range. The upper sub-range is between an upper content value and the upper midpoint content value and the lower sub-range is between the lower midpoint content value and a lower content value. The upper midpoint content value includes changing a most significant don't care bit to a 1 and remaining don't care bits to 0. The lower midpoint content value includes changing a most significant don't care bit to 0 and remaining don't care bits to 1.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Noriaki Asamoto
  • Patent number: 8639875
    Abstract: A CAM-based search engine is disclosed that reduces power consumption during a plurality of different search operations concurrently performed in a plurality of device pipelines by selectively applying one of a number of different power reduction techniques for each pipeline in response to configuration data indicating the type of search operation that is being performed in the pipeline.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 28, 2014
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Cristian Estan