Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract: A Ternary Content Addressable Memory (TCAM)-based Longest Prefix Match (LPM) lookup table including a TCAM holding a plurality of prefix entries for looking up results in an associated RAM, the associated RAM storing results corresponding to TCAM match indices; additional Random Access Memory (RAM) storing results from the associated RAM; and one entry in the TCAM representing at least two entries in the additional RAM from the associated RAM, whereby at least one entry in the TCAM is made available.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: Methods, systems, and computer readable storage medium directed to efficiently storing value ranges in TCAM or other memory are disclosed. Storing a range of integer values in a memory includes determining a subrange within the range, so that, in a first and a second plurality of bit subsequences from binary representations respectively of a start value and an end value of the subrange, all except at most one bit subsequence in the first plurality is either equal in value to a corresponding bit subsequence in the second plurality or has a value of 0 and a corresponding bit subsequence of the second plurality has a maximum value. The storing a range of integer values in a memory further includes forming a first bit string based upon values of the first and second plurality of bit subsequences, and storing the first bit string in the memory.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: A ternary content-addressable memory (TCAM) that is implemented based on other types of memory (e.g., SRAM) in conjunction with processing, including hashing functions. Such a H-TCAM may be used, for example, in implementation of routing equipment. A method of storing routing information on a network device, the routing information comprising a plurality of entries, each entry has a key value and a mask value, commences by identifying a plurality of groups, each group comprising a subset number of entries having a different common mask. The groups are identified by determining a subset number of entries that have a common mask value, meaning at least a portion of the mask value that is the same for all entries of the subset number of entries.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: Described are techniques for data processing and caching. In response to a client failing to retrieve contents of a data element from a cache location specified by a first data element identifier including a first content-based identifier, the contents of the data element are obtained and stored at a cache location specified by the first data element identifier. The contents of the data element are updated at a second point in time and stored as second contents in the data element source. The data element at the second point in time has a second content-based identifier. In response to the client failing to retrieve the second contents of the data element from a cache location specified by a second data element identifier including the second content-based identifier, the second contents of the data element are obtained and stored at a cache location specified by the second data element identifier.

Abstract: In one embodiment, batch entries include multiple content-addressable memory (CAM) entries, and CAM entries are allowed to be shared among different batch entries. For example, two or more batch entries might have a common set of bits (e.g., representing an address, an address prefix, etc.). Rather than consuming bits of multiple CAM entries, a single CAM entry can be programmed with this common information. Other CAM entries associated with different batch entries are programmed with the distinguishing/different values. A batch lookup operation on a batch entry of two or more CAM entries requires multiple lookup operations on the CAM entries. One embodiment uses a batch mask vector to provide information to decode what CAM entries are shared among which batch entries during a series of lookup operations, which can be performed in one or both directions through the CAM entries.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.

Abstract: A CAS data storage system replicates data on a non-CAS storage device. The CAS storage device recognizes duplicate data and stores the data only once, whereas the non-CAS device does not recognize duplication of data and requires full storage of the data. The CAS data storage device saves on redundant data transfer by transferring, in the case of duplicate data, the address of a primary location at which the data is stored and the address of the current duplication. The CAS data storage system includes a hash?address table for this purpose. The non-CAS storage device then copies its own data from the primary location into the current location.

Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.

Abstract: Disclosed are various embodiments of a network switch for storing a prefix address and a mask corresponding to the prefix address, the prefix address and the mask each representing a binary value, the mask representing a number of significant bits of an address beginning with a most significant bit. The network switch obtains a network frame via one of a plurality of network interfaces, the network frame comprising a network address in a header of the network frame, the network address being a binary value representing a physical address of a network interface device. The network switch determines a truth value associated with a comparison of a mask number of bits of the prefix and network addresses, the truth value indicating an equivalence of the comparison. In response to the truth value, the network switch may initiate at least one action associated with the network frame.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: Methods and systems for a network device having a plurality of base-ports, each base-port having a plurality of sub-ports configured to operate independently as a port for sending and receiving information using one of a plurality of network links at a plurality of rates complying with a plurality of protocols. The network device includes a ternary content addressable memory (TCAM) module for storing a plurality of entries for routing frames that are received for the plurality of sub-ports complying with the plurality of protocols. Each TCAM entry has an associated history value that is used by a processor for the network device to purge TCAM entries based on an age of the TCAM entries.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit die, the transaction may be transmitted, without modification to the address, to the third integrated circuit die. The translation may be based upon a first table with each entry including a first address and a second translated address corresponding to the first address, and a second table with each entry including a first address and an indication if the transaction is to be forwarded without modification to the address.

Abstract: Aspects of the disclosure provide for increasing the capacity of ternary content addressable memories (TCAMs). For example, one aspect provides a method for adding rules to a TCAM, wherein the TCAM comprises multiple configurable banks. According to this method, a range of candidate banks in which the proposed rule may be stored is identified based on a priority of the proposed rule, and one of the candidate banks is selected for storing the proposed rule based on a width of the proposed rule and widths of the candidate banks. Another aspect provides a method for deleting one or more rules from a TCAM comprising multiple configurable banks. According to this method, once the rule is deleted, the bank from which it was deleted may be reduced in width, and therefore increased in capacity. For example, wider rules stored in this bank may be relocated to other banks using the method for adding rules to a TCAM.

Abstract: A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.

Abstract: A system is disclosed that includes a content addressable memory and an input register coupled to the content addressable memory. The input register can store a data word and the content addressable memory determines if the data word exists in the content addressable memory. The system also includes a power control circuit coupled to the content addressable memory for selectively providing power to at least a portion of the content addressable memory. The system includes power control logic coupled to the power control circuit to selectively reduce power to the at least a portion of the content addressable memory when valid data does not exist in the at least a portion of the content addressable memory.

Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.

Abstract: Embodiments of the present invention provide methods, systems, and apparatuses for a fault resilient collaborative media serving array comprising a plurality of nodes. In one embodiment, the present invention provides a method for creating a fault resilient collaborative media serving array where the array nodes do not share memory, the serving of a content file is accomplished by the collaborative efforts of many nodes in the array, and where there is no fixed allocation of sessions to nodes.

Abstract: Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.

Abstract: A transactional memory (TM) includes a selectable bank of hardware algorithm prework engines, a selectable bank of hardware lookup engines, and a memory unit. The memory unit stores result values (RVs), instructions, and lookup data operands. The transactional memory receives a lookup command across a bus from one of a plurality of processors. The lookup command includes a source identification value, data, a table number value, and a table set value. In response to the lookup command, the transactional memory selects one hardware algorithm prework engine and one hardware lookup engine to perform the lookup operation. The selected hardware algorithm prework engine modifies data included in the lookup command. The selected hardware lookup engine performs a lookup operation using the modified data and lookup operands provided by the memory unit. In response to performing the lookup operation, the transactional memory returns a result value and optionally an instruction.

Abstract: A content addressable memory (CAM)-based search engine is disclosed that reduces power consumption during a plurality of different search operations concurrently performed in a plurality of device pipelines by selectively applying one of a number of different power reduction techniques for each pipeline in response to configuration data indicating the type of search operation that is being performed in the pipeline.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.

Abstract: A system including an associative memory and a first input device in communication with the associative memory. The first input device is configured to receive an attribute value relating to a corresponding attribute of a subject of interest to a user. The system also includes a processor, in communication with the first input device, and configured to generate a first entity using the attribute value. The system also includes an associative memory configured to perform an analogy query using the entity to retrieve a second entity whose attributes match some attributes of the first entity. The associative memory is further configured to cluster first data in the first entity and second data in the second entity.

Abstract: A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.

Abstract: Efficient hardware implementations of a binary search algorithm are provided.

Abstract: A table lookup apparatus has a content-addressable memory (CAM) based device and a first cache. The CAM based device is used to store at least one table. The first cache is coupled to the CAM based device, and used to cache at least one input search key of the CAM based device and at least one corresponding search result. Besides, the table lookup apparatus may further includes a plurality of second caches and an arbiter. Each second cache is used to cache at least one input search key of the CAM based device and at least one corresponding search result. The arbiter is coupled between the first cache and each of the second caches, and used to arbitrate access of the first cache between the second caches.

Abstract: A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.

Abstract: A method is comprised of inputting a comparand word to a plurality of hash circuits, each hash circuit being responsive to a different portion of the comparand word. The hash circuits output a hash signal which is used to enable or precharge portions of a CAM. The comparand word is also input to the CAM. The CAM compares the comparand word in the precharged portions of the CAM and outputs information responsive to the comparing step. When used to process Internet addresses, the information output may be port information or an index from which port information may be located. A circuit is also disclosed as is a method of initializing the circuit.

Abstract: A system for ternary content addressable memory (TCAM) storage may include a TCAM having multiple entries and a processor that is communicatively coupled to the TCAM. The processor may be operative to receive a first numerical range and determine a first ternary representation of a second numerical range that encompasses the first numerical range. The processor may be further operative to determine a second ternary representation corresponding to at least one of a lower bound or an upper bound of the first numerical range. The processor may be further operative to store a combination of the first and second ternary representations in one of the entries of the TCAM. In one or more implementations, the numerical range may be a port range and the combination of the ternary representations may be stored in one of the entries of the TCAM as a portion of a packet classification rule.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a first search value is associated with a first range field; determining a first bitmap associated with the first search value, wherein the first bitmap indicates at least one range encompassing the first search value; generating a search key based on the first bitmap; and accessing the ternary content addressable memory based on the search key.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.

Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

Abstract: According to an example, multi-mode storage may include operating a first array including a first memory and a second array including a second memory in one or more modes of operation. The first memory may be a relatively denser memory compared to the second memory and the second memory may be a relatively faster memory compared to the first memory. The modes of operation may include a first mode of operation where the first array functions as the relatively denser memory compared to the second memory and the second array functions as the relatively faster memory compared to the first memory, a second mode of operation where the second array is operated as an automatic cache of a portion of a dataset, and a third mode of operation where a cache-tag functionality used to support the second mode of operation is instead used to provide a CAM.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.

Abstract: An integrated circuit (IC) that includes content addressable memories (CAM) is described. A CAM receives a key and searches through entries stored in the CAM for one or more entries that match the key. If a matching entry is found, the IC returns a storage address indicating a memory location at which the matching was found.

Abstract: Embodiments of the invention are directed to a TCAM for longest prefix matching in a routing system. The TCAM comprises a plurality of records of which a portion are configured into one or more address clusters each such cluster corresponding to a respective IP address prefix length and another portion of which are configured into a free cluster not corresponding to any IP address prefix length.

Abstract: The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item; searching the cache for presence of a row tag of the RAM data row corresponding to the data item of hash index; in response to presence, searching the RAM for a RAM data item corresponding to the input data item according to the corresponding row tag of the RAM data row; in response to absence, searching the RAM for a RAM data item corresponding to the input data item by using the data item of hash index; and in response to finding a RAM data item corresponding to the input data item in the RAM, outputting data corresponding to the RAM data item. The method can accelerate data search in the CAM.

Abstract: A system including an associative memory including a plurality of data and a plurality of associations among the plurality of data. The plurality of data is collected into associated groups. The associative memory is configured to be queried based on at least indirect relationships among the plurality of data. The system also includes an input device in communication with the associative memory, the input device configured to receive an input criteria. The system also includes an optimizer in communication with the input device and the associative memory. The optimizer is configured to generate, using the associative memory, a multi-dimensional criteria file from the input criteria. The optimizer converts the input criteria to numerical representations associated with expert weights and generates the multi-dimensional criteria file to include an optimized plurality of criteria relevant to the input criteria.

Abstract: Some embodiments relate to storing objects on a fixed-content archive storage system. When a request to modify an object is received, a new object or portion of an object is created, rather than overwriting the previous version of the object.

Abstract: Incoming data packets are often processed according to their origination or destination port. In order to efficiently determine applicable rules based on port values, ranges are stored in association with corresponding rules in a ternary memory. In order to reduce the amount of required memory to store these ranges, extra unused bits of the ACL that includes the rule can be used. Further, to maximize the storage capability of these limited extra bits, most common ranges can be stored in one or more bit partitions depending on whether they encompass other most common ranges to be stored in the extra bits. Through partitioning and intelligent bit assignment, many ranges can be stored in the limited extra bits, and can each remain individually addressable.

Abstract: To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal LU, and a definition of a logical unit. The management server displays a state of the storage system by using the received value based on the surplus capacity value.

Abstract: Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.

Abstract: Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.