Abstract: A low-heat, large-scale ternary content-addressable memory (TCAM) efficiently compares one or more input records with a set of entries. Compression may also be used. X bits are eliminated from entries and in some embodiments, a subset of non-X bits are also eliminated, minimizing entries that must be searched. Entry bit sets can be converted into sets of fields. A useful set of fields is a triplet comprising a start field, a length field, and a data field. Hashing determines the RAM line of the TCAM in which entries are stored and which RAM line is to be compared with a given input. Searches are only needed on entries in RAM lines corresponding to inputs of interest. Priority values decide the winner if more than one TCAM entry in the appropriate RAM line matches the input. Bin packing can be used to optimally allocate TCAM entries across different possible RAM lines.

Abstract: What is disclosed is process for backing data objects from a content addressed storage system to a tape storage device such that the data objects are written in a contiguous sequential fashion. Data objects are kept together on the storage medium, rather than fragmented. An embodiment of the present invention describes the software modules and memory buffers required to implement this process. Additionally, what is disclosed is a process that restores data objects that have been contiguously written to tape. According to one embodiment of the present invention, recovery of non-fragmented data objects is made more efficient and less prone to failure.

Abstract: A method may include, in response to a single command and an N-bit segment value, generating a search key comprising M segments for at least one of a plurality of different databases, the N-bit segment value forming different ones of the M search key segments according to a database configuration of the at least one database.

Abstract: A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.

Abstract: A method includes searching a content addressable memory based on a comparand. The comparand includes a collection of bits. A modified comparand is generated by modifying the comparand. The modified comparand is based at least in part on a comparand overlay data value. The content addressable memory is also searched with the modified comparand.

Abstract: A device for scalable block data storage and retrieval uses content addressing. Data storage devices store data blocks, and are connected over a network to computing modules. The modules comprise control modules and data modules and carry out content addressing for both storage and retrieval. The network defines separate control paths via the control modules and data paths via the data modules.

Abstract: A method and a computer readable medium having executable instructions are provided. The method and instructions when executed generates a first look-up key from a group of look-up key units stored in a data storage, generation of the first look up key being completed prior to the completion of a key generation processing cycle. A next look-up key unit from the group of look-up key units stored in the data storage may be skipped over when the next look up key corresponds to a second look-up key that has a key length equal to or smaller than a predetermined key length. A third look-up key unit may be selected from the group of look-up key units, the third look-up key unit associated with a third look-up key having a key length greater than a second predetermined key length, the second predetermined key length being greater than the first predetermined key length. The first look-up key and a portion of the third look-up key sequentially may be output during the same output processing cycle.

Abstract: A method is comprised of inputting a comparand word to a plurality of hash circuits, each hash circuit being responsive to a different portion of the comparand word. The hash circuits output a hash signal which is used to enable or precharge portions of a CAM. The comparand word is also input to the CAM. The CAM compares the comparand word in the precharged portions of the CAM and outputs information responsive to the comparing step. When used to process Internet addresses, the information output may be port information or an index from which port information may be located. A circuit is also disclosed as is a method of initializing the circuit.

Abstract: A network apparatus comprises a plurality of ports, and a forwarding engine coupled to the plurality of ports. The forwarding engine is configured to transfer data units received via at least some of the plurality of ports to one or more appropriate ports in the plurality of ports. The forwarding engine comprises a content addressable memory (CAM) device to store a plurality of data patterns organized in a plurality of groups, wherein the CAM device is configured to, responsive to input data, output in a single cycle a plurality of match indications corresponding to the plurality of groups. The forwarding engine also comprises a logic device coupled to the CAM device and configured to generate an action value based on the plurality of match indications, wherein the action value indicates an action to be taken by the forwarding engine.

Abstract: Reinforcement learning is one of the intellectual operations applied to autonomously moving robots etc. It is a system having excellent sides, for example, enabling operation in unknown environments. However, it has the basic problem called the “incomplete perception problem”. A variety of solution has been proposed, but none has been decisive. The systems also become complex. A simple and effective method of solution has been desired. A complex value function defining a state-action value by a complex number is introduced. Time series information is introduced into a phase part of the complex number value. Due to this, the time series information is introduced into the value function without using a complex algorithm, so the incomplete perception problem is effectively solved by simple loading of the method.

Abstract: Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.

Abstract: A hardware private array is a thread state storage that is embedded within the processor or within logic associated with a bus or wake-and-go logic. The hardware private array and/or wake-and-go array may have a limited storage area. Therefore, each thread may have an associated priority. If there is insufficient space in the hardware private array, then the wake-and-go mechanism may compare the priority of the thread to the priorities of the threads already stored in the hardware private array and wake-and-go array. If the thread has a higher priority than at least one thread already stored in the hardware private array and wake-and-go array, then the wake-and-go mechanism may remove a lowest priority thread, meaning the thread is removed from hardware private array and wake-and-go array and converted to a flee model.

Abstract: A program product, a translation lookaside buffer and a related method for operating the TLB is provided.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A network device, such as a firewall, may be configured to filter network traffic. The filter may include regular expressions that are converted by the firewall into a format that can be stored in a ternary content addressable memory. In one exemplary implementation, the filter definition may include one or more input regular expressions that include variables that are compared to a result based on an equality/inequality relationship, where multiple variables are combined using logical operations selected from a set of logical operations including (but not limited to) logical AND and logical OR operations. The firewall may convert the input regular expressions into a format in which the equality/inequality relationships are converted to a pure equality relationship and the multiple variables are combined using only logical OR operations. The firewall may program the ternary content-addressable memory to implement the filter based on the converted one or more input regular expressions.

Abstract: An improved technique is provided for compressing a packet classifier for a computer network system. A set of packet classification rules is first partitioned into one or more partitions. For each partition, columns of bits in each of the ternary strings of a given partition are reordered, the ternary strings within each partition are consolidated into one or more replacement strings and then the columns of bits of the replacement strings are rearranged back to the starting order. The rearranged replacement strings from each of the partitions are appended together to form a compressed packet classifier which may be instantiated in a content-addressable memory device.

Abstract: A system and method for storing data in a content-addressable system is provided. The system includes a content-addressable storage system and a persistent cache. The persistent cache includes a temporary address generator that is configured to generate a temporary address which is associated with data to be stored in the persistent cache, and a non-content-addressable storage system configured to store and retrieve data in the persistent cache using the temporary address. The persistent cache further comprises an address translator configured to map a temporary address associated with the data in the non-content addressable storage system with a content address associated with the data in the content-addressable storage system.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A non-volatile storage subsystem is capable of serving as a configuration controller for configuring/programming one or more field-programmable devices, such as FPGAs, of a target computer system. The storage subsystem may be in the form of a memory card or drive that plugs into a standard slot or external port of the target system. When connected to the target system, the storage subsystem uses the appropriate download interface/protocol to stream or otherwise send configuration data stored in its non-volatile storage to the target system's field-programmable device(s). Thus, the need for a configuration controller in the target system is avoided. Once the configuration process is complete, the storage subsystem preferably acts as a standard storage subsystem, such as an ATA storage drive, that may be used by the target system to store data.

Abstract: A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell configured to output a ground voltage in response to the read voltage.

Abstract: An image compression and decompression method compresses data based upon the data states, and decompresses the compressed data based upon the codes generated during the compression.

Abstract: A method and apparatus for detecting predefined signatures in packet payload is disclosed. In one embodiment, a method of string matching in a network packet payload includes performing hash on a current search string received in the network packet payload to generate respective search string hash values, storing the search string hash values in a hash buffer, performing rehash using the search string hash values to generate an associated search string rehashed value, performing a parallel search of the search string rehashed value against Content Addressable Memory (CAM) entries to determine if the search string rehashed value matches with one of the CAM entries, and identifying the current search string in the network packet payload as a match with one of the CAM entries based on the outcome of performing the parallel search.

Abstract: A method for producing a configurable content-addressable memory (CAM) cell design, in which the method includes: inputting the configurable CAM cell design to a computer, the configurable CAM cell design capable of being configured as one of a binary CAM design and a ternary CAM design, depending on connections of a metal overlay; selecting one of a first metal overlay design for the binary CAM design and a second metal overlay design for a ternary CAM design; if the first metal overlay design is selected, then combining the first metal overlay design with the configurable CAM cell design to produce a binary CAM design including two binary CAM cells with a single search port, and outputting the binary CAM design; and if the second metal overlay design is selected, then combining the second metal overly design with the configurable CAM cell design to produce a ternary CAM design including a single ternary CAM cell with two search ports, and outputting the ternary CAM design by the computer.

Abstract: A system is disclosed that includes a content addressable memory and an input register coupled to the content addressable memory. The input register can store a data word and the content addressable memory determines if the data word exists in the content addressable memory. The system also includes a power control circuit coupled to the content addressable memory for selectively providing power to at least a portion of the content addressable memory. The system includes power control logic coupled to the power control circuit to selectively reduce power to the at least a portion of the content addressable memory when valid data does not exist in the at least a portion of the content addressable memory.

Abstract: Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write speeds may be improved by adding a pending write buffer to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer is used to handle collisions for write accesses to the same block, allowing two simultaneous writes to any regular memory block to occur.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.

Abstract: A method may include comparing a first content addressable memory (“CAM”) entry with a first key value to generate a first comparison result; comparing each of multiple second CAM entries with a second key value to generate multiple second comparison results; and generating a match signal if the first key value matches the first CAM entry and the second key value matches at least one of the multiple second CAM entries.

Abstract: Methods and apparatus for expanded capacity virtual volumes in a virtualized storage system. A storage controller of the storage system parses a SCSI command block as it is received to generate a tag value indicating a segment of a virtual volume to which the command block is directed. The tag value is used to select one of a plurality of mapping segment objects stored in a memory of the controller. Each mapping segment objects maps logical block addresses of a corresponding segment of a corresponding virtual volume to physical storage addresses on the physical storage devices that comprise the virtual volume. An I/O processing circuit of the controller then processes the SCSI command block in accordance with the mapping information in the selected mapping segment object. In one exemplary embodiment, each segment of a virtual volume comprises 2 terabytes of storage capacity of the virtual volume.

Abstract: A method for searching within a data block for a data chunk having a predefined value, the method includes: fetching, by a processor, a data block search instruction; fetching, a data unit that includes multiple data chunks; wherein at least one data chunk within the data unit belongs to the data block; deciding whether to use a mask for data chunk level masking; searching, by a hardware accelerator, for a valid data chunk within the fetched data unit that has the predefined value; wherein the searching comprising applying a mask; wherein a valid data chunk in an non-masked data chunk that belongs to the data block; and determining whether to update the value of the mask and whether to fetch a new data unit that belongs to the data block.

Abstract: A method includes searching a content addressable memory based on a comparand. The comparand includes a collection of bits. A modified comparand is generated by modifying the comparand. The modified comparand is based at least in part on a comparand overlay data value. The content addressable memory is also searched with the modified comparand.

Abstract: A system has a data structure in which a value can be obtained from a key. In a write access, a first pair <Key,Hash(Value)> and a second pair <Hash(Value),Value> are stored respectively in a volatile storage device. The first pair <Key,Hash(Value)> is saved in a nonvolatile storage device before returning a response, and the second pair <Hash(Value),Value> is saved in the first storage device at any time with the second pair saved in the volatile storage device. In a read access in which a value is obtained from a key, it is determined that data is not stored normally if the second pair is not found in processing in which after obtaining the hash value of the value from the first pair, the second pair is read.

Abstract: A comparand word is input to a plurality of hash circuits, with each hash circuit responding to a different portion of the comparand word. The hash circuits output a hash signal which enables or precharges portions of a content addressable memory CAM. The comparand word is also input to the CAM. The CAM compares the comparand word in the precharged portions of the CAM and outputs information responsive to the comparison. When Internet addresses are processed, the output information is either port information or an index for locating port information.

Abstract: The invention discloses a method and system of maintaining states for the request queue of a hardware accelerator, wherein the request queue stores therein at least one Coprocessor Request Block (CRB) to be input into the hardware accelerator, the method comprising: receiving, in response to a CRB specified by the request queue is about to enter the hardware accelerator, the state pointer of the specified CRB; acquiring physical storage locations of other CRBs in the request queue that are stored in the request queue and are the same as the state pointer of the specified CRB; controlling the input of the specified CRB and the state information required for processing the specified CRB into a hardware buffer; receiving the state information of the specified CRB that has been processed in the hardware accelerator; if the above physical storage locations are not vacant, then making physical storage locations that are closest on the request queue of the specified CRB as the selected location and storing the recei

Abstract: The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non-volatile storage device operatively coupled to a host device. In some embodiments, data is stored to a cache area of a non-volatile memory within the peripheral non-volatile storage device in accordance with a historical rate at which other data was received by the peripheral storage device from the host device and/or a historical average time interval between successive host write requests received and/or an assessed rate at which data is required to be written to the non-volatile memory and/or a detecting by the peripheral non-volatile memory device that the host has read the storage ready/busy flag. In some embodiments, data is copied from a cache storage area of the non-volatile memory to a main storage area in accordance with the historical rate and/or the historical average time interval.

Abstract: A method, system, and computer program product for preventing network service attacks, including processing a message to validate the message for message version and syntax via a security firewall; canonicalizing the message and extracting a message header and body via a converter; converting the body into a Patricia Trie via the converter; and validating the header and the converted body for security via a comparator.

Abstract: One embodiment of a system for logging and reporting access to content includes a content addressable storage manager configured to control storing of data elements to the content storage and retrieving of data elements from the content storage, the content addressable storage manager including a content identifier generator configured to generate a content identifier for each data element stored in the content storage, and an access log module configured to record access data for each data element stored in the content storage and to associate the access data for each data element with a content identifier of that data element. The access log module is also configured to generate an access report that includes access data for one or more data elements stored in the content storage.

Abstract: Embodiments of the invention relate to associating a source string with a target content unit stored on a content addressable storage (CAS) system. This may be accomplished, in some embodiments, by storing on the CAS system an associative content unit that includes the source string in its binding part and includes the target content unit in its non-binding part.

Abstract: Methods for efficiently managing a ternary content-addressable memory (TCAM) by minimizing movements of TCAM entries include determining a first node and a second node in the TCAM, determining if there is a free TCAM entry between the first node and the second node, and storing the new entry in the free TCAM entry. Upon determining that a free TCAM entry does not exist between the first node and the second node, further determining a chain of nodes and then determining if there is a free TCAM entry in the chain of nodes. Upon determining that there is a free TCAM entry within the chain of nodes, moving the TCAM entries identified as the nodes in the chain of nodes to generate a free node nearest to the new entry and inserting the new entry in the free node. Moving the TCAM entries identified as the nodes in the chain of nodes preserves the order of the nodes.

Abstract: Ternary content-addressable memories (TCAMs) may be used to obtain a simple and very fast implementation of a router's forwarding engine. The applicability of TCAMs is, however, limited by their size and high power requirement. The present invention provides an improved method and associated algorithms to reduce the power needed to search a forwarding table using a TCAM. Additionally, the present invention teaches how to couple TCAMs and high bandwidth SRAMs so as to overcome both the power and size limitations of a pure TCAM forwarding engine. By using one of the novel TCAM-SRAM coupling schemes (M-12Wb), TCAM memory is reduced by a factor of about 5 on IPv4 data sets and by a factor of about 2.5 on IPv6 data sets; TCAM power requirement is reduced by a factor of about 10 on IPv4 data sets and by a factor of about 6 on IPv6 data sets.

Abstract: A method and apparatus for providing TCAM functionality in a custom integrated circuit (IC) is presented. An incoming key is broken into a predefined number of sub-keys. Each sub-key is sued to address a Random Access Memory (RAM), one RAM for each sub-key. An output of the RAM is collected for each sub-key, each output comprising a Partial Match Vector (PMV). The PMVs are bitwise ANDed to obtain a value which is provided to a priority encoder to obtain an index. The index is used to access a result RAM to return a result value for the key.

Abstract: A content addressable memory system, method and computer program product is described. The memory system comprises a location addressable store having data identified by location and multiple levels of content addressable stores each holding ternary content words. The content words are associated with references to data in the location addressable store. The content store levels might be implemented using different technologies that have different performance, capacity, and cost attributes. The memory system includes a content based cache for improved performance and a content addressable memory management unit for managing memory access operations and virtual memory addressing.

Abstract: An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

Abstract: A method, apparatus and computer program product for performing TCAM lookups in multi-threaded packet processors is presented. A Ternary Content Addressable Memory (TCAM) key is constructed for a packet and a Packet Reference Number (PRN) is generated. The TCAM key and the packet are tagged with the PRN. The TCAM key and the PRN are sent to a TCAM and in parallel the packet and the PRN are sent to a packet processing thread. The PRN is used to read the TCAM result when it is ready.

Abstract: A process for evaluating and geocoding of GIS data elements utilizes a plurality of “locate” tests and a weighting scheme to express the match results as a multidimensional vector. Multiple inputs and data sources, as well as ambiguous and partial input data, are used to generate an output with improved precision by applying a weighting function to each input element and generating a set of test vectors (i.e., in the input data element weighted by the known accuracy of the element/source). A sum of a plurality of tests is then generated as the “characteristic vector” of the test set. By using two (or more) different sets of tests, two (or more) characteristic vectors are formed. Various well-known algebraic techniques can then be used to evaluate the results of each set of tests and select the “best match” result.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A storage system includes a first storage device, and a second storage device retrieving stored data at higher speeds than the first storage device. The storage system further includes a feature calculation unit calculating feature data based on a data content of storage target data, a data management unit storing the storage target data and managing a storing position thereof based on the feature data calculated from the storage target data, and a duplication determination unit determining whether or not the same storage target data as the storage target data to be newly stored is already stored in the first storage device. In a case that the same storage target data as the storage target data to be newly stored is already stored in the first storage device, the data management unit stores the storage target data already stored in the first storage device into the second device.

Abstract: Computers are caused to provide a hash table wherein each entry is associated with a binary key and indexed by a selected portion of a hash value of the associated key, and points to a data structure location for storing non-selected portions of, or the entire hash value of, the binary key, and action data corresponding to the value of the binary key. Content addressable memory entries store a binary key, or a value unique to it, and an association to a corresponding action. Pointers to the data structure use selected portions of binary key hash values as an index when not selected portions of hash values of other binary keys, and associations are established between CAM entry and associated data structure locations when selected portions of the hash values of the binary keys are the same as selected portions of hash values of one or more other binary keys.

Abstract: An associative memory 4 for primary searching operation of an associative memory 23 supplies a valid state to a primary match line 13 corresponding to storage data coincident with search data 10 taking mask information into account, and supplies a value obtained from a result of a logical sum operation (an OR operation), with a valid state for the storage data as true, of all said coincident storage data to a counting means 25 as intermediate data 15. The counting means 25 supplies a result of an operation to the intermediate data 15 for counting the number of bits in an invalid state for the storage data to an associative memory 3 for secondary searching operations as secondary search data 19. Among secondary storage data obtained by carrying out said operation to said storage data, the associative memory 3 for secondary searching operation supplies a result of carrying out the searching operation of the secondary search data 19 to a secondary match line 21.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: Lookup techniques are described, which can achieve improvements in energy efficiency, speed, and cost, of IP address lookup, for example, in devices and systems employing ternary content addressable memory (TCAM). The disclosed subject matter describes dividing a route table into several sub-tries with disjoint range boundaries. In addition, the disclosed subject matter describes storing sub-tries of a route table between a TCAM and a faster and less costly memory. The disclosed details enable various refinements and modifications according to system design and tradeoff considerations.