Abstract: A method and system thereof for identifying records are described. Records on a node are distinguished from other records on the node by assigning each record a unique local identifier. When a record is moved from one node to another node, a unique global identifier is assigned to the record. A translation technique is employed to map the local identifier to the global identifier (and vice versa).

Abstract: Distributed content storage and retrieval is disclosed. A set of features associated with a content object is determined. A storage location is selected to perform an operation with respect to the content object, from a plurality of storage locations comprising a distributed content storage system, based at least in part on probability data indicating a degree to which the selected storage location is associated statistically with a feature comprising the set of features determined to be associated with the content object.

Abstract: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair.

Abstract: Some embodiments are directed to a technique for storing and/or locating content units stored on an object addressable storage (OAS) system, wherein each content unit is identified by an object identifier. The OAS system may comprise a plurality of zones, each of which stores content units. A mapping process may be defined that maps object identifiers for content units to zones on the OAS system. Thus, the storage location for a content unit on the OAS system may be the zone on the OAS system to which the object identifier for the content unit maps.

Abstract: A method for archival of messages in content addressable storage can be provided. The method can comprise identifying a plurality of messages for archival. The identified messages can be subjected to extraction of attachments therefrom. The messages, minus any removed attachments, can then be concatenated into a container file. Finally, the container file and the extracted attachments are stored in a content addressable storage system.

Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and according to the rules used for generating the feature vectors corresponding to the stored documents such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more additional result columns coding for a similarity measure betwe

Abstract: In a packet switching device or system, such as a router, switch, combination router/switch, or component thereof, a method of and system for performing a table lookup operation using a lookup table index that exceeds a CAM key size is provided. Multiple CAM accesses are performed, each using a CAM key derived from a subset of lookup table index, resulting in one or more CAM entries. One or more matching table entries are derived from the one or more CAM entries resulting from the multiple CAM accesses.

Abstract: An exact match lookup system includes a hash function that generates a hash value in response to an input hash key. The hash value is used to retrieve a hash bucket index value from a hash bucket index table. The hash bucket index value is used to retrieve a plurality of hash keys from a plurality of hash bucket tables, in parallel. The retrieved hash keys are compared with the input hash key to identify a match. Hit logic generates an output index by concatenating the hash bucket index value with an address associated with the hash bucket table that provides the matching hash key. An exact match result is provided in response to the output index. A content addressable memory (CAM) may store hash keys that do not fit in the hash bucket tables.

Abstract: A method of minimizing an amount of memory area required to store a plurality of rules associated with one or more access control lists (ACLs) includes selectively combining the plurality of rules into one or more groups depending upon similarities between the entries within each field and storing the groups in a database including a content addressable memory (CAM) device and a random access memory (RAM) device.

Abstract: A content addressable memory (CAM) device, method, and method of generating entries for range matching are disclosed. A CAM device (800) according to one embodiment can include a pre-encoder (806) that encodes range bit values W into additional bits E. Additional bits E can indicate compression of range rules according to particular bit pairs. A CAM array (802) can include entries that store compressed range code values (RANGE) with corresponding additional bit values (ENC). Alternate embodiments can include pre-encoders that encode portions of range values (K1 to Ki) in a “one-hot” fashion. Corresponding CAM entries can include encoded value having sections that each represent increasingly finer divisions of a range space.

Abstract: In an embodiment, a packet data switching system comprises content-addressable memory configured to redirect, to a measurement computer, a request to access a server application program hosted at a server computer in response to receiving the request from a client computer; the measurement computer comprises request rewriting logic configured to receive the request via redirection based on the CAM, to record a first time value representing a time of receiving the request, to forward the request to the server application, to receive a response from the server computer to the request, to rewrite a payload of the response by embedding a browser-executable measurement reporting script into the payload, and to forward the rewritten response to the client; performance recording logic configured to receive a second time value from the client based on the client computer executing the measurement reporting script, and to store a performance record with the time values.

Abstract: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata and then programmed in PRISM for evaluating content with the search rules.

Abstract: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata (FSA) and then programmed in PRISM for evaluating content with the search rules. PRISM architecture comprises of a plurality of programmable PRISM Search Engines (PSE), each capable of supporting a predetermined size FSAs. FSA extension architecture is created to extend the predetermined size limit of an FSA supported by PSE, by coupling multiple PSEs together to behave as a composite PSE to support larger FSAs.

Abstract: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory derived using randomly accessible dynamic memory circuits that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the dynamic Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata and then programmed in dynamic PRISM for evaluating content with the search rules.

Abstract: A method includes searching a content addressable memory based on a comparand. The comparand includes a collection of bits. A modified comparand is generated by modifying the comparand. The modified comparand is based at least in part on a comparand overlay data value. The content addressable memory is also searched with the modified comparand.

Abstract: A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM), includes a storage unit for storing a portion of content data, and a match module for comparing the portion of the content data with a respective portion of search data received by the match module. The match module includes a first static logic gate associated with a first half of the storage unit storing a sub-portion of the portion of the content data, and a second static logic gate associated with a second half of the storage unit. The first static logic gate forwards a signal for disabling the second static logic gate if the sub-portion of the portion of the content data does not match with a respective sub-portion of the portion of the search data.

Abstract: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata (FSA) and then programmed in PRISM for evaluating content with the search rules. PRISM architecture comprises of a plurality of programmable PRISM Search Engines (PSE) organized in PRISM memory clusters that are used simultaneously to search content presented to PRISM. A context switching architecture enables transitioning of PSE states between different input contexts.

Abstract: A memory system comprises first memory that includes memory cells. Content addressable memory (CAM) includes CAM memory cells, stores addresses of selected ones of the memory cells, stores data having the addresses in corresponding ones of the CAM memory cells and retrieves data having the addresses from corresponding ones of the CAM memory cells. An adaptive refresh module stores data from selected ones of the memory cells in the CAM memory cells to one of increase and maintain a time period between refreshing of the memory cells.

Abstract: Methods and apparatus for rating Uniform Resource Locators (URLs) are disclosed. The method includes determining a request size pertaining to a length of the URL to be rated and for generating a rating request message containing the URL. The rating request message is a DNS (domain name system) message if the request size is less than or equal to a predefined size limitation, and the rating request message is a HTTP (hypertext transfer protocol) message if the request size is greater than the predefined size limitation.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: A device for performing searches includes a comparand data register configured to store a comparand received from a host processor where the comparand includes a collection of bits. The device also includes logic configured to generate a modified comparand corresponding to the comparand and based at least in part on a comparand overlay data value. The logic is also configured to search the CAM with the modified comparand.

Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.

Abstract: A memory system comprises first memory that includes memory cells that are selectively refreshed at a refresh rate. A test module tests operation of the memory cells at the refresh rate and that identifies T of the memory cells that are inoperable when refreshed at the refresh rate, where T is an integer greater than zero. Content addressable memory (CAM) includes D CAM memory cells where D is an integer greater than or equal to one. An adaptive refresh module selectively adjusts a refresh rate of the first memory based on T and D.

Abstract: An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described.

Abstract: Subject matter disclosed herein relates to remapping memory devices.

Abstract: A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows.

Abstract: Subject matter disclosed herein relates to remapping memory devices.

Abstract: A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address.

Abstract: A content addressed storage device configured to maintain content address mapping is disclosed. A data object to be stored on the content addressed storage device and a local data object identifier by which the data object is known to the sending source are received from a sending source. A content address to be associated with the data object on the content addressed storage device is determined based at least in part on the contents of the data object. The data object is stored on the content addressed storage device in a storage location associated with the content address. A mapping that associates the local data object identifier with the content address is maintained on the content addressed storage device.

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract: A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are utilized as an index for referencing a look-up table. One or more look-up tables may be realized for supporting memory operations facilitating efficient transfer modes available in the RAM.

Abstract: Apparatus having corresponding methods and computer programs, to detect a pattern in a string, comprises a memory circuit to store W-character segments of the pattern, where each segment comprises a fragment of the pattern; a key circuit to generate W-character keys each including a fragment of the string; a comparison circuit to compare the keys and the segments; where, when a segment matches a key, the comparison circuit indicates an initial match between the pattern and the string; and where, when one of the segments matches only a L-character fragment of one of the keys, wherein L<W, the key circuit generates a new key including the L-character fragment and a K-character fragment of the string including K=W?L consecutive characters from the string that are adjacent to the L matching characters in the string.

Abstract: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged according to a 2-dimensional priority scheme. Data words outside a selected 1×M column are masked to be ignored in determining a match, and the CAM is searched. Each search includes N compare cycles and each compare cycle having a different 1×M column selected. A highest priority match per compare cycle is pipelined from a priority encoder with the pipelined matches arranged to communicate a priority order in a first dimension of the 2-dimensional priority scheme.

Abstract: A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage portion that is constructed as a CAM. For each row of the CAM a match determination is made that indicates if the TAG portion is the same as contents of the particular row. A decoder decodes an index portion and provides an output for each row. On a per row basis the output of the decoder is logically combined with the hit/miss signals to determine if there is a hit for the TAG memory. If there is a hit for the TAG memory, a translated address corresponding to the index portion of the address is then output as the selected translated address.

Abstract: Systems, methods and computer program products are provided for a distributed associative memory base. Such methods may include providing a distributed memory base that includes a network of networks of associative memory networks. The memory base may include a network of associative memory networks, a respective associative memory network comprising associations among a respective observer entity and a plurality of observed entities that are observed by the respective observer entity. Ones of the associative memory networks are physically and/or logically independent from other ones of the associative memory networks. Methods include imagining associations from the associative memory base using a plurality of streaming queues that correspond to ones of a plurality of rows of ones of the associative memory networks.

Abstract: A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.

Abstract: An extensible fingerprint comprised of an ordered list of fingerprints generated by applying each of a plurality of distinct fingerprinting functions to the content of a data item. The extensible fingerprint can be extended by using a new fingerprinting function to compute a new fingerprint and adding the new fingerprint to the list so that the old extensible fingerprint of a data item is used as a prefix of the new extensible fingerprint for that data item. Thus, the fingerprint can be incrementally extended over time. A content-addressed storage system uses extensible fingerprints as addresses and can also change over time.

Abstract: Methods for efficiently managing a ternary content-addressable memory (TCAM) by minimizing movements of TCAM entries include determining a first node and a second node in the TCAM, determining if there is a free TCAM entry between the first node and the second node, and storing the new entry in the free TCAM entry. Upon determining that a free TCAM entry does not exist between the first node and the second node, further determining a chain of nodes and then determining if there is a free TCAM entry in the chain of nodes. Upon determining that there is a free TCAM entry within the chain of nodes, moving the TCAM entries identified as the nodes in the chain of nodes to generate a free node nearest to the new entry and inserting the new entry in the free node. Moving the TCAM entries identified as the nodes in the chain of nodes preserves the order of the nodes.

Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB<0> and <1>). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL<0>, keyFIB<0> and keyFIB<1>).

Abstract: A multi-protocol, multi-stage, real-time frame classifier is disclosed. A preliminary multi-protocol frame composition analyzer is provided for performing preliminary multi-protocol frame classification for incoming frames. A parsing instruction generator is provided for processing at least the incoming frame and the preliminary multi-protocol frame classification to provide parsing instructions. A multi-stage parsing engine provides multi-stage parsing of the incoming frame according to the parsing instructions to generate search results presenting information about the incoming frame. An advanced level of data extraction is provided across various frame protocols without imposing a performance penalty. Longest prefix match searches and/or direct lookup searches are supported. Moreover, conditional extractions, instruction branching, multi-stage processing are all performed in real time.

Abstract: A nonvolatile memory device has a memory cell array including a memory cell group for storing option information, and a controller configured to wait for a preset period of time after a command for loading the option information has been received before performing an operation of loading the option information.

Abstract: A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.

Abstract: A method for error detection in a cache memory for storing data, the access to the data stored in the cache memory taking place by addresses assigned to them, wherein for the addresses assigned to the stored data, at least one first test signature made up of at least one first signature bit is generated and also stored in the cache memory.

Abstract: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. Content search rules include of regular expressions which are compiled to finite state automata (FSA) and further include of patterns of strings a first set of which are compiled to a compressed signature database and a second set of which are compiled into FSAs. The finite state automata are then programmed in Programmable Intelligent Search Memory (PRISM) programmable FSA rule blocks and the compressed signature database is programmed in the PRISM signature search engines for evaluating content with the content search rules. A compiler compiles the content search rules for evaluation by PRISM memory.

Abstract: Memory architecture provides capabilities for high performance content search using regular expressions and patterns of strings. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules include of regular expressions which are converted to finite state automata and then programmed in PRISM for evaluating content with the search rules. The PRISM memory provides features for complex regular expression symbols like interval symbol, range detection, complement control, bit masking and the like and enables complex symbols and compact regular expression representation.

Abstract: A scheduling co-processor for scheduling the execution of threads on a processor is disclosed. In certain embodiments, the scheduling co-processor includes one or more engines (such as lookup tables) that are programmable with a Petri-net representation of a thread scheduling algorithm. The scheduling co-processor may further include a token list to store tokens associated with the Petri-net; an enabled-thread list to indicate which threads are enabled for execution in response to particular tokens being present in the token list; and a ready-thread list to indicate which threads from the enabled-thread list are ready for execution when data and/or space availability conditions associated with the threads are satisfied.

Abstract: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata and then programmed in PRISM for evaluating content with the search rules. The PRISM memory provides features for complex regular expression symbols like range detection, complement control, bit masking and the like and enables complex symbols and compact regular expression representation.

Abstract: Techniques and systems are described herein to maintain a mapping of logical to physical registers—for example, in the context of a multithreaded processor that supports renaming. A mapping unit may have a plurality of entries, each of which stores rename information for a dedicated one of a set of physical registers available to the processor for renaming. This physically-indexed mapping unit may support multiple threads, and may comprise a content-addressable memory (CAM) in certain embodiments. The mapping unit may support various combinations of read operations (to determine if a logical register is mapped to a physical register), write operations (to create or modify one or more entries containing mapping information), thread flush operations, and commit operations. More than one of such operations may be performed substantially simultaneously in certain embodiments.

Abstract: A search engine device includes a lookup circuit, such as a content addressable memory (CAM) array. This lookup circuit is configured to generate multiple active match signals in response to detecting multiple matches between a search operand applied to said lookup circuit and multiple entries therein, during a search operation. A priority sequencer circuit is also provided. This priority sequencer circuit, which is electrically coupled to outputs of the lookup circuit, is configured to sequentially encode each of the multiple active match signals according to priority.

Abstract: An apparatus is equipped with a content addressable memory (CAM) to store one or more key entries corresponding to a data class represented by the CAM. Each of the one or more key entries is associated with a key tag corresponding to one of one or more subclasses of the data class. The apparatus is further equipped with logic coupled to the CAM to extract a data key from a data stream, to compare all or part of the data key with the one or more key entries to determine if the data key is a member of the data class, and to classify the data key as belonging to one of the one or more subclasses of the data class if the data key is determined to be a member of data class.