Abstract: A non-volatile Content Addressable Memory element including a non volatile memristor memory element; a data bus for applying a data signal to be programmed into the memristor memory element; a search bus for applying a search term; an output or match bus; logic to selectively enable the search bus and the data bus; wherein the logic is configurable to set the logic state of the memristor according to a logic signal applied to the data bus, and configurable to enable the logic state of the memristor to be compared to a logic state on the search bus with the match bus signaling a true logic state upon matching.

Abstract: In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) having compact bitcells with embedded partial A+B=K logic to generate two speculative hit/miss signals under control of a delayed evaluate signal. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: An interface module includes ports; a first memory that stores identifiers indicating processing operations for data blocks associating with the ports; a content-addressable memory that stores keys, each including at least one port and one identifier; a second memory that stores processing information associated with the keys and indicating processing operations for data blocks; an action code circuit that, when a data block has been received, obtains, from the first memory, an identifier set for a port that has received the data block; a generation circuit that generates a key from the port that has received the data block and the identifier obtained by the action code circuit; and a judgment circuit that judges how to process the received data block in accordance with a piece of the processing information associated with the generated key obtained by searching the content-addressable memory using the key generated by the generation circuit.

Abstract: A method includes searching a content addressable memory based on a comparand. The comparand includes a collection of bits. A modified comparand is generated by modifying the comparand. The modified comparand is based at least in part on a comparand overlay data value. The content addressable memory is also searched with the modified comparand.

Abstract: A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.

Abstract: According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

Abstract: A system and method for storing data in a content-addressable system is provided. The system includes a content-addressable storage system and a persistent cache. The persistent cache includes a temporary address generator that is configured to generate a temporary address which is associated with data to be stored in the persistent cache, and a non-content-addressable storage system configured to store and retrieve data in the persistent cache using the temporary address. The persistent cache further comprises an address translator configured to map a temporary address associated with the data in the non-content addressable storage system with a content address associated with the data in the content-addressable storage system.

Abstract: An improved technique is provided for compressing a packet classifier for a computer network system. A set of packet classification rules is first partitioned into one or more partitions. For each partition, columns of bits in each of the ternary strings of a given partition are reordered, the ternary strings within each partition are consolidated into one or more replacement strings and then the columns of bits of the replacement strings are rearranged back to the starting order. The rearranged replacement strings from each of the partitions are appended together to form a compressed packet classifier which may be instantiated in a content-addressable memory device.

Abstract: A method and apparatus for managing information for projects is provided. Information for the projects is stored as data entities in an associative memory. The associative memory includes a plurality of data having a plurality of associations in which the data entities are included in the plurality of data. The associative memory further includes a content-addressable structure. The associative memory is configured to be queried based on at least one relationship selected from a group that includes direct relationships and indirect relationships among the plurality of data. The data entities stored in the associative memory are grouped to form a number of clusters. A report is generated using the number of clusters.

Abstract: An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full. Also, an associative list processing unit and method comprising employing a plurality of prioritized cell blocks and using a tree of prioritized multiplexers descending from the plurality of cell blocks.

Abstract: A system and method for optimizing memory bus bandwidth, is achieved by utilization of the memory bus, either by utilizing the idle time of the memory bus, or by prioritizing prefetch requests to exploit the bank structure of the external memory. When a bus master of the memory bus makes a request to access a particular line in a memory device, the memory controller generates a request for accessing a line next to the current line that is requested by the bus master. Data corresponding to the next line is retrieved from the memory device and stored in the memory-controller when the memory bus is idle. The stored data may be served to a bus master upon request for the data. However, the memory bus is not engaged when the data stored in the memory controller is served. Therefore idle time of the memory bus is utilized.

Abstract: The associative memory comprises a simplified functional processing unit (SFPU), implemented by an LUT logic network, that implements simplified CAM function g, where g is the function derived from CAM function ƒ by replacing the value showing “invalid” with the don't care, an auxiliary memory that stores the inverse function ƒ?1 of said CAM function ƒ; and an output modifier that checks whether the output value of said SFPU is equal to the output value of the CAM function ƒ; wherein the SFPU produces the operational value (“tentative index value”) for the simplified CAM function g; the auxiliary memory produces the value of the inverse function ƒ?1 when the tentative index value is applied; the output modifier compares the input data with the value of the inverse function ƒ?1, and produces the output of said SFPU if they are the same, otherwise produces the signal showing the “invalid”.

Abstract: Technologies are generally described for exploiting program phase behavior to duplicate most recently and/or frequently accessed tag entries in a Tag Replication Buffer (TRB) to protect the information integrity of tag arrays in a processor cache. The reliability/effectiveness of microprocessor cache performance may be further improved by capturing/duplicating tags of dirty cache lines, exploiting the fact that detected error-corrupted clean cache lines can be recovered by L2 cache. A deterministic TRB replacement triggered early write-back scheme may provide full duplication and recovery of single-bit errors for tags of dirty cache lines.

Abstract: A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.

Abstract: A hierarchical storage management (HSM) system and method. A system is provided comprising: a data usage monitor for extracting data object information from data objects in a hierarchical storage complex that is managed by a content management system; a data relationship repository for storing data object information, wherein the data object information includes relationship data for data objects in the hierarchical storage complex; and a system that analyzes the relationship data and makes data management action recommendations for the hierarchical storage complex.

Abstract: A content addressable memory (CAM) (100) can include a CAM memory array (102) having both a data field (102-0) and a mask field (102-1). A multiplexer (MUX) (108) can selectively load data from either a register (104) or an external data input (106) to one or both fields (102-0 and 102-1) of CAM memory array (102).

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: In accordance with exemplary embodiments of the present invention, a content addressable data structure system may include directed acyclic graphs (DAGs) of data content that are addressed using both a user-defined search key and content of data blocks. Internal keys of retention roots of the DAGs may be derived from the user-defined search key while the remaining blocks may be content addressed. As opposed to using a content address, the user may provide the search key when retrieving and deleting DAGs retaining the data content. In addition, the internal keys may be implemented using internal content addressable storage operations, such as applying a hash function and employing a distributed hash table.

Abstract: Embodiments of the invention relate to associating a source string with a target content unit stored on a content addressable storage (CAS) system. This may be accomplished, in some embodiments, by storing on the CAS system an associative content unit that includes the source string in its binding part and includes the target content unit in its non-binding part.

Abstract: A CAS data storage system with one or more source CAS data storage spaces and one or more destination CAS data storage spaces, and a communication line therebetween, receives input data at the source storage space for local storage and for replication to the destination CAS storage space. CAS metadata is used in the replication procedure between the two separate CAS storage spaces. Thus, data at the source storage space is used to form an active buffer for transfer to the destination storage space, the active buffer holding a hash result of the respective data item and a storage address. The system detects whenever there is more than one data item in said active buffer sharing a same storage address and upon such detection transfers a respective hash result of only the last of the data items.

Abstract: An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.

Abstract: A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n<m. The method also includes mapping the at least one signal for each logical block to physical block from a corresponding a set of r+1 physical blocks, each set of r+1 physical blocks being different from one another.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: An image forming apparatus includes a memory interface configured to receive an external memory, an internal memory, a reading unit, a writing unit, and an activating unit. The activating unit activates the image forming apparatus when an external memory is connected to the memory interface and model data read from the external memory by the reading unit is the same as model data about the image forming apparatus stored in the internal memory.

Abstract: A network device allocates a number of blocks of memory in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and assigns unused blocks of memory of the TCAM to a free pool. The network device also detects execution of a run mechanism by the TCAM, and allocates, based on the execution of the run mechanism, one of the unused blocks of memory to a filter or rule of one of the multiple databases.

Abstract: Managing data on a federated CAS system includes determining a group of objects to be stored on a single CAS system of the federated CAS system, obtaining a cookie corresponding a particular one of the CAS systems of the federated CAS system in response to initially writing at least one object of the group of objects, where the at least one object is written to the particular one of the CAS systems, and providing the cookie in connection with writing objects of the group of objects following initially writing at least one object of the group of objects. The cookie causes the objects to be written to the particular one of the CAS systems. The cookie may be provided by at least one router that maintains the federated CAS system, which may be separate from both a processing device and the particular one of the CAS systems.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A method of transmitting data between a plurality of inter-connected elements. The method comprises receiving a message from a first element, said message comprising a routing key plus optionally a data payload. The routing key is processed to identify a plurality of said inter-connected elements, and data is transmitted to said identified plurality of inter-connected elements.

Abstract: The address generator has a hash network for producing hashed Y1, which is obtained by hushing X1, to an input vector X=(X1, X2), a tentative address generator Y1 for making an address generation function f(X) to a tentative address A? when no hash collision occurs and otherwise making one of unique addresses A to A?, a data regenerator for producing X?=f?1(A?), a unique address generator for producing A? when X? coincides with X and otherwise producing “invalid value”, a complementary address generator for producing (X) to X, to which the unique address generator produces “invalid value”, and otherwise producing “invalid value”, and an output combiner which produces, when the outputs of the unique address generator and the complementary address generator have values other than the “invalid value”, the values as a unique address A and otherwise produces “invalid value” as A.

Abstract: A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.

Abstract: An apparatus, system, and method are disclosed for efficiently mapping virtual and physical addresses. A forward mapping module uses a forward map to identify physical addresses of data of a data segment from a virtual address. The data segment is identified in a storage request. The virtual addresses include discrete addresses within a virtual address space where the virtual addresses sparsely populate the virtual address space. A reverse mapping module uses a reverse map to determine a virtual address of a data segment from a physical address. The reverse map maps the data storage device into erase regions such that a portion of the reverse map spans an erase region of the data storage device erased together during a storage space recovery operation. A storage space recovery module uses the reverse map to identify valid data in an erase region prior to an operation to recover the erase region.

Abstract: Systems and methods for managing databases are disclosed. One disclosed system includes a processor-addressable physical memory and a processor in communication with said processor-addressable physical memory and configured to execute an environment and to allocate an environment memory to said environment. In such a system, said environment is configured to maintain a database of objects in a database memory within said environment memory. An application executes in an application memory within said environment memory, and upon instantiation of a database object, the application environment allocates memory in said database for said database object, the database providing master storage for said database object.

Abstract: A content addressable memory (CAM) can include a CAM memory array having both a data field and a mask field. A multiplexer (MUX) can selectively load data from either a register or an external data input to one or both fields of the CAM memory array.

Abstract: One embodiment of the invention relates to the transfer of content between a host computer that issues OAS access requests and a block I/O storage system. Specifically, a host computer may issue an access request for a content unit that identifies the content unit is an object identifier. The request may be received by a second server, which may determine the block address(es) on the block I/O storage system at which the content unit is stored. A request may then be sent to the block I/O storage system to retrieve the content stored at the requested block address(es) and the block I/O storage system may return the content.

Abstract: An ordered storage structure implemented based on a content addressable memory (CAM). In an embodiment, a set of identifiers are formed with an order matching a desired access order for items. Each item is stored with a corresponding identifier in an entry of the CAM, with the identifiers being stored in the searchable fields/columns of the CAM. Thus, the items can be retrieved in the desired access order by providing the identifiers as search key inputs to the CAM in the desired access order.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract: A cache memory includes a CAM with an associativity of n (where n is a natural number) and an SRAM, and storing or reading out corresponding data when a tag address is specified by a CPU connected to the cache memory, the tag address constituted by a first sub-tag address and a second sub-tag address. The cache memory classifies the data, according to the time at which a read request has been made, into at least a first generation which corresponds to a read request made at a recent time and a second generation which corresponds to a read request made at a time which is different from the recent time. The first sub-tag address is managed by the CAM. The second sub-tag address is managed by the SRAM. The cache memory allows a plurality of second sub-tag addresses to be associated with a same first sub-tag address.

Abstract: When a data word is designated through a network search engine, a FIFO unit, and the like, a relay apparatus according to the invention searches for an associative memory address corresponding to the data word. Even when the associative memory address is internally converted to a contents memory address, the relay apparatus stores the contents memory address by causing it to correspond to a search result corresponding to the contents memory address as well as outputs the associative memory address together with the search result.

Abstract: A method and apparatus for performing a hold operation while keeping the data in place as the data is in a hold state. Such a method and apparatus substantially eliminates the need for a copy operation and thus provides advantages cost and management savings. The method and apparatus define a hold delete operation along with hold life points in a CAS system.

Abstract: A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n<m. The method also includes mapping the at least one signal for each logical block to physical block from a corresponding a set of r+1 physical blocks, each set of r+1 physical blocks being different from one another.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: Apparatus, systems, and methods may operate to send a window copy message including changed window identification information to a remote node when metadata associated with a changed foreground window at a local node has been cached, and otherwise, to locally cache the window metadata and send the window metadata and window pixel data to the remote node. When a preselected minimum bandwidth connection is not available between the local node and the remote node, additional operations may include sending a rectangle paint message including changed rectangle identification information to the remote node when rectangle metadata associated with a changed rectangle of a designated minimum size at the local node has been cached, and otherwise, to locally cache the rectangle metadata and send the rectangle metadata and rectangle pixel data to the remote node. Additional apparatus, systems, and methods are disclosed.

Abstract: A system of retrieving documents comprising: coding a plurality of stored documents as a respective document feature vector; generating a query feature vector based on a query document; and performing one or more logical operations between the query feature vector and the document feature vector to obtain respective similarity measures.

Abstract: A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.

Abstract: A device may select a longest run of contiguous unwritten pages from multiple runs of contiguous unwritten pages provided in a ternary content addressable memory, and may write a rule on a page that is located at a middle portion of the longest run to create two runs of contiguous unwritten pages. The device may also receive a packet, and may apply the rule to the packet.

Abstract: Techniques for performing de-duplication for data blocks in a computer storage environment. At least one chunking/hashing unit receives input data from a source and processes it to output data blocks and content addresses for them. In one aspect, the chunking/hashing unit outputs all blocks without checking to see whether any is a duplicate of a block previously stored on the storage environment. In another aspect, each data block is processed by one of a plurality of distributed object addressable storage (OAS) devices that each is selected to process data blocks having content addresses with a particular range. The OAS devices determine whether each received data block is a duplicate of another previously stored on the computer storage environment, and when it is not, stores the data block.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.