Abstract: An arithmetic logic unit (140) improves the processing of information. The arithmetic logic unit (140) includes a register unit (250), a ternary content addressable memory (260), and an operations unit (270).

Abstract: A ternary content addressable memory (TCAM) system and method of operating the same can enable a user to configure the system to operate as either a pseudo TCAM or full TCAM system. Control logic (206) can have an address modification circuit (250) coupled between multiple inputs and row decoders (206-0 and 206-1) for simultaneously writing the same mask value to mask fields of a predetermined number of memory locations in a full TCAM array.

Abstract: A mixed serial-parallel content addressable memory (CAM) includes serial CAM cells and parallel CAM cells that are arranged in multiple (N) columns and multiple (M) rows. Each row includes at least one serial CAM cell and at least two parallel CAM cells. The M rows are searched in parallel. For each row, the serial CAM cells are searched sequentially, and the parallel CAM cells are selectively searched in parallel. The CAM further includes a driver that generates search lines for the N columns of CAM cells, one search line per column. The driver sets the search lines to an N-bit value to search for in the CAM. Prior to each search operation, the driver presets at least one search line for at least one column of serial CAM cells to precharge a match line for each row.

Abstract: A memory system including: a memory device; an ECC system installed in the memory device so as to generate a warning signal in case there are uncorrectable errors; an address generating circuit for generating internal addresses in place of bad area addresses in accordance with the waning signal, the progressing of the internal addresses being selected as to avoid address collision with the address progressing of the memory device at least at the beginning; and a CAM for storing the internal addresses as substitutive area addresses, the CAM being referred to at an access time of the memory device so as to generate the substitutive area addresses in place of the bad area addresses in accordance with the warning signal.

Abstract: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom, specialized instruction, operating system call, or application programming interface call that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address, expected data value, and comparison type associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, logic associated with the CAM performs a comparison based on the data value being written, expected data value, and comparison type.

Abstract: There are provided a hardware accelerator and method for providing hardware acceleration for an application server and/or a layer 7 switch. The hardware accelerator includes a content access memory (CAM) configured to accelerate string comparison operations in the application server and/or layer 7 switch. The string comparison operations involve strings having varying key string positions.

Abstract: A search engine system (100) compares search key values to stored entry values, and includes first blocks of entries (102) and second blocks of entries (104). First blocks of entries (102) can be “search” blocks that can provide a relatively fast search speed of stored data value, and each store a unique first portion of one or more entry values. Second blocks of entries (104) can be randomly accessible entries logically arranged into search nodes that each correspond to a first portion of an entry value stored in the first block of entries. Each search node can include one or more second portions of an entry value.

Abstract: A content addressable memory (CAM) device (200) can provide for suppression of hit indications. Prioritized match indications (212) can be applied in parallel to both an encoding read-only-memory (ROM) (204-1) and suppression data store (206). A suppression data store (206) can output suppression bits (SH0 and SH1) that correspond to each CAM entry. Hit indications can be selectively suppressed according the values of suppression bits (SH0 and SH1). Hit suppression methods for a CAM device are also disclosed.

Abstract: In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells that is associated with a low-retention row of storage cells once every nth refresh interval.

Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory device including content addressable memory configured to store an address associated with one or more memory cells while an access operation is performed on the one or more memory cells. Other embodiments may be described.

Abstract: A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured to receive a second search signal and to provide second search result indications, a precedence number table coupled to the first and second type memory banks and configured to provide programmable precedence numbers, and a precedence determination circuit coupled to the first and second type memory banks and the precedence number table and configured to provide a third search result indication is disclosed. In one embodiment, the first type memory bank can be a static random access memory (SRAM) and the second type memory bank can be a ternary content addressable memory (TCAM).

Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract: A system for accessing a content-addressable memory in a packet processing system is described. A register holds a data element having a key field. Logic derives a value of the key responsive to 1) packet processing state data relating to one or more packets undergoing processing by the packet processing system, and 2) the value of this key field. The derived value of the key is presented to the memory. In response, the memory searches for an entry associated with the presented key value. If found, the content value associated with the entry is output. If not found, a signal indicative of a miss condition is output.

Abstract: In a method and apparatus for encoding a bit field within a memory device, the bit field is encoded in a manner that requires fewer memory device entries and fewer encoded bits per entry than conventional encoding schemes.

Abstract: A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.

Abstract: In a packet switching device or system, such as a router, switch, combination router/switch, or component thereof, a method of and system for performing a table lookup operation using a lookup table index that exceeds a CAM key size is provided. Multiple CAM accesses are performed, each using a CAM key derived from a subset of lookup table index, resulting in one or more CAM entries. One or more matching table entries are derived from the one or more CAM entries resulting from the multiple CAM accesses.

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: Ternary content-addressable memories (TCAMs) may be used to obtain a simple and very fast implementation of a router's forwarding engine. The applicability of TCAMs is, however, limited by their size and high power requirement. The present invention provides an improved method and associated algorithms to reduce the power needed to search a forwarding table using a TCAM. Additionally, the present invention teaches how to couple TCAMs and high bandwidth SRAMs so as to overcome both the power and size limitations of a pure TCAM forwarding engine. By using one of the novel TCAM-SRAM coupling schemes (M-12Wb), TCAM memory is reduced by a factor of about 5 on IPv4 data sets and by a factor of about 2.5 on IPv6 data sets; TCAM power requirement is reduced by a factor of about 10 on IPv4 data sets and by a factor of about 6 on IPv6 data sets.

Abstract: A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status portion has an independent status parity bit. The status parity bit is recalculated and updated whenever a status bit in the entry is changed. In another embodiment, each status bit is provided with a corresponding shadow status bit. Each status bit and its corresponding shadow status bit is always loaded with the same data. In this manner, every change 1-bit change to a status bit is made as two identical 1-bit changes to the status bit and its corresponding shadow status bit. The two identical 1-bit changes are parity neutral, thereby permitting status changes without requiring recomputing and saving a new parity.

Abstract: One embodiment is directed to a method of segregating one or more content addressable storage systems into a plurality of virtual pools. The virtual pools can be allocated to different content sources and/or can be assigned to different storage system capabilities. Another embodiment is directed to transmitting with an input/output request for a content unit information specifying at least one storage capability to be applied to the content unit, and/or receiving such an I/O and implementing the specified storage system capabilities. Another embodiment is directed to extracting from an I/O request from a source information relating to an impact of the I/O on at least one characteristic of the content units stored on a CAS system from the source.

Abstract: A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word decoders. A memory system according to another embodiment includes a word decoder storing an identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address. A memory system according to yet another embodiment includes a word decoder having more than sixteen address line inputs. A memory system according to a further embodiment includes a word decoder array having fewer word decoders than combinations of memory addresses. Methods are also provided.

Abstract: A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact pattern, the content search system including a first search circuit dedicated to perform an exact string match operation to determine whether the input string contains a first portion that matches the exact pattern, and a second search circuit dedicated to perform an inexact string match operation to determine whether the input string contains a second portion that matches the inexact pattern.

Abstract: The present invention relates to a method for polymorphic and systemic structuring of associative memory via a third-party manager that allows a human or electronic operator to manage various families of associative memory for various applications.

Abstract: Associative memory systems, methods and/or computer program products include a network of networks of associative memory networks. A network of entity associative memory networks is provided, a respective entity associative memory of which includes associations among a respective observer entity and observed entities that are observed by the respective observer entity, based on input documents. A network of feedback associative memory networks includes associations among observed entities for a respective positive and/or negative evaluation for a respective task of a respective user. A network of document associative memory networks includes associations among observed entities in a respective observed input source, such as a respective input document. A network of community associative memory networks includes associations among a respective observer entity, observed entities that are observed by the respective observer entity, and observed tasks of users in which the observer entity was queried.

Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

Abstract: In the present invention, a data processing device for processing streams of network borne data includes content inspection logic configurable to perform pattern matching functions on a received content stream and output match data, and a microengine for executing computer coded instructions, the microengine being coupled to the content inspection logic for configuring the pattern matching function of the content inspection unit in respect of a particular processing job for the received content stream and for processing the content stream independence on the match data. The microengine is adapted to reconfigure dynamically the content inspection logic in dependence on the match data thereby to modify the pattern matching function performed by the content inspection logic on the content stream during the course of a processing job. The present invention provides a novel architecture and method for processing content as it flows through a network.

Abstract: One embodiment is a system for locating content on a storage system, in which the storage system provides a location hint to the host of where the data is physically stored, which the host can resubmit with future access requests. In another embodiment, an index that maps content addresses to physical storage locations is cached on the storage system. In yet another embodiment, intrinsic locations are used to select a storage location for newly written data based on an address of the data. In a further embodiment, units of data that are stored at approximately the same time having location index entries that are proximate in the index.

Abstract: Access to content addressable data on a network is facilitated using digital information storing devices or data repositories (“silos”) that monitor broadcast data requests over the network. A number of silos automatically monitor both data requests and data itself that are broadcast over a network. The silos selectively store data. Each silo responds to data requests broadcast over the network with data the silo has previously intercepted. A content addressable file scheme is used to enable the data repositories to reliably identify data being requested. When a data request is received, each silo evaluates whether it has all or a portion of the data being requested and responds to requests when it has the data. Requests for data are implemented by broadcasting a cryptographic hash data identifier of the data file needed. The data identifier is used by a silo to determine which data to receive and store.

Abstract: Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed.

Abstract: In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.

Abstract: The disclosed invention presents a method and apparatus to a one dimensional prefix search problem. The problem consists looking up the best match to a word out of a table of one-dimensional prefixes. The invention addresses the problems with prior art of high power consumption, large silicon chip area for implementation and slow search speed. The prefix entries are divided in several subgroups. A function is described that can be efficiently implemented to determine which of these subgroups the presented word will find a best match in. Thus, it is necessary to search only this small subgroup of prefixes. This saves on power consumption as well as area. An efficient hardware embodiment of this idea which can search at a very high speed is also presented. The applications for this invention could include internet routing, telephone call routing and string matching.

Abstract: An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.

Abstract: A quaternary content-addressable memory includes multiple entries configured to match a lookup word, with each of these entries including multiple cells and with the lookup word including multiple lookup bits for matching corresponding cells of each of the entries. Each of the cells is individually configurable to be in one of multiple states identified by two bits, with these states including a first matching state for matching a value of a corresponding bit of the lookup word with the value having a first matching value, a second matching state for matching the value of the corresponding bit having a second matching value, a wildcard state for matching the value of the corresponding bit having either the first or the second matching value, and an ignore state for indicating to ignore the cell in determining whether or not the entry to which the cell belongs matches the lookup word.

Abstract: A method and apparatus adapted to perform content addressable memory (CAM) lookup by performing a lookup in parallel using multiple classification rules in the CAM with the same key, wherein the CAM lookup is used to resolve IPv4 and IPv6 addresses.

Abstract: An action group arbitration system can include an action table and a search block having a first type memory portion and a second type memory portion is disclosed. The search block can provide a plurality of search results, each corresponding to a group number, in response to a search key. The action table may receive the search results and provide an action indication in response to each of the plurality of search results that contain a hit indication. The first type memory portion can include static random access memory (SRAM) and the second type memory portion can include ternary content addressable memory (TCAM). Further, the action table may be divided into portions corresponding to the group number.

Abstract: Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry combines the match signals for memory locations to obtain combined match signals; the combination depends on an indicated search width, which can be one of a set of multiples of the memory location width. A priority encoder provides a priority signal indicating a combined match signal that has priority and is asserted; the priority encoder can therefore be smaller than would be necessary to prioritize all the match signals. An address encoder obtains most significant bits of an address code in response to the priority signal. Select circuitry responds to the priority signal by selecting match signals and suppress signals for the combined match signal with priority.

Abstract: A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).

Abstract: Access to content addressable data on a network is facilitated using digital information storing devices or data repositories (“silos”) that monitor broadcast data requests over the network. A number of silos automatically monitor both data requests and data itself that are broadcast over a network. The silos selectively store data. Each silo responds to data requests broadcast over the network with data the silo has previously intercepted. A content addressable file scheme is used to enable the data repositories to reliably identify data being requested. When a data request is received, each silo evaluates whether it has all or a portion of the data being requested and responds to requests when it has the data. Requests for data are implemented by broadcasting a cryptographic hash data identifier of the data file needed. The data identifier is used by a silo to determine which data to receive and store.

Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

Abstract: Access to content addressable data on a network is facilitated using digital information storing devices or data repositories (“silos”) that monitor broadcast data requests over the network. A number of silos automatically monitor both data requests and data itself that are broadcast over a network. The silos selectively store data. Each silo responds to data requests broadcast over the network with data the silo has previously intercepted. A content addressable file scheme is used to enable the data repositories to reliably identify data being requested. When a data request is received, each silo evaluates whether it has all or a portion of the data being requested and responds to requests when it has the data. Requests for data are implemented by broadcasting a cryptographic has data identifier of the data file needed. The data identifier is used by a silo to determine which data to receive and store.

Abstract: A method and system for detecting matching strings in a string of characters utilizing content addressable memory using primary and secondary matches is disclosed.

Abstract: A method and system for detecting matching strings in a string of characters utilizing content addressable memory is disclosed.

Abstract: A TCP/IP offload network interface device (NID) is integrated with a processing device that executes a stack. The TCP/IP offload NID can either be a full TCP/IP offload device or a partial TCP/IP offload device. Common types of packets are processed by the NID in a fast-path such that the stack is offloaded of TCP and IP protocol processing tasks. A hash is made from the packet header and is pushed onto a queue. The hash is later popped off the queue and is used to identify an associated TCB number from a hash table. A mechanism caches hash buckets in SRAM and stores other hash buckets in DRAM. An “IN SRAM CAM” is used to determine whether the TCB associated with the identified TCB number is cached in SRAM or whether it must be moved from DRAM into the SRAM cache. A lock table and a “lock table CAM” mechanism is disclosed that facilitates multiple processors working on the protocol processing of a single packet.

Abstract: A data processing apparatus operable to map an input data value 10 to a resultant data value 50 is disclosed, said data processing apparatus comprising: a ternary content addressable memory 20 operable to store a plurality of first data values; a data store operable 30 to store a plurality of second data values corresponding to said plurality of first data values; said ternary content addressable memory 20 comprising a data input operable to receive said input data value, said ternary content addressable memory being operable to match said input data value to a first data value and to control said data store to output a second data value corresponding to said matched first data value; said data processing apparatus further comprising exclusive combination logic operable to exclusively combine at least some bits of said output second data value with at least some bits of said input data value to produce at least some bits of said resultant data value.

Abstract: A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: A digital signal processor. The digital signal processor includes a first data classification block. The first data classification block outputs a first block priority number associated with a first data stored in the first data classification block that matches a search key. The digital signal processor includes a second data classification block. The second data classification block outputs a second priority number associated with a second data stored in the second data classification block that matches the search key. The digital signal processor includes a device index processor. The device index processor selects a most significant block priority number from the first block priority number and the second block priority number.

Abstract: Method and apparatus for using a Content Addressable Memory for sorting a plurality of data items is presented. The data items to be sorted are stored in the Content Addressable Memory. A plurality of bit-by-bit burst searches are performed on the contents of the Content Addressable Memory with all other bits in the search key masked. The number of burst searches is proportional to the total number of bits in the data items to be sorted. The search is deterministic dependent on the number of bits in each data item on which a sort is performed and on the number of data items to be sorted.