Abstract: A method of filtering high data rate traffic (2) based on its content, the method comprising identifying candidate fixed size partial strings (3) within the traffic; comparing characters within the candidate partial string with a content addressable memory (1) containing wanted partial string values and identifying matching traffic; wherein the partial string content includes at least one anchor character (7); wherein the partial string size is set to a predetermined number of characters adjacent to the anchor character; and, wherein partial strings ending in an anchor character are compared with wanted partial string values in the content addressable memory.

Abstract: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.

Abstract: Associative memory systems, methods and/or computer program products include a network of networks of associative memory networks. A network of entity associative memory networks is provided, a respective entity associative memory of which includes associations among a respective observer entity and observed entities that are observed by the respective observer entity, based on input documents. A network of feedback associative memory networks includes associations among observed entities for a respective positive and/or negative evaluation for a respective task of a respective user. A network of document associative memory networks includes associations among observed entities in a respective observed input source, such as a respective input document. A network of community associative memory networks includes associations among a respective observer entity, observed entities that are observed by the respective observer entity, and observed tasks of users in which the observer entity was queried.

Abstract: Representing a number of assets on an originating computer begins with selecting the assets to be represented. Cryptographic hash asset identifiers are generated; each of the asset identifiers is computed using the contents of a particular asset. The asset identifier is a content-based or content-addressable asset name for the asset and is location independent. An asset list is generated that includes the asset identifiers computed from the assets. A cryptographic hash asset list identifier is generated that is computed from the asset list. The asset list identifier is stored for later retrieval. The assets selected are also stored for safekeeping either locally or on a computer network. In the event of loss of the files from the originating computer, the asset list identifier is retrieved. Using the asset list identifier, the original asset list is found and retrieved from its safe location.

Abstract: A program product, a translation lookaside buffer and a related method for operating the TLB is provided.

Abstract: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

Abstract: A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.

Abstract: A system architecture optimized for pattern match applications is provided. This system architecture includes a host computer and a pattern match accelerator (PMA), which in turn includes one or more pattern match units (PMUs) and PMU control logic. The PMU control logic can divide a database, transmitted by the host computer, such that each of the PMUs receives a database portion. Each PMU includes a main memory for storing the database portion and a programmable logic device (PLD). The PLD can perform a search and score operation on its database portion. Advantageously, the PLD can be configured to generate an index of the database portion, and then configured to perform the search and score operation using that index. The PMU control logic can assemble the results of the pattern match application from each of the PMUs.

Abstract: Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison.

Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB<0> and <1>). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL<0>, keyFIB<0> and keyFIB<1>).

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract: A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

Abstract: A system and method for policing one or more flows of a data stream of packets associated with differing transmission protocols. The current capacity level for each flow is determined, as is the packet protocol associated with each packet. A packet parameter in the packet that is indicative of the bandwidth consumption of the packet is identified. The packet parameter is converted to a predetermined format if the packet is not associated with a predetermined packet protocol. A common bandwidth capacity test is performed to determine whether the packet is conforming or non-conforming, and is a function of the packet parameter and the current bandwidth capacity level.

Abstract: A search engine method and apparatus can store and update status information for each entry of a content addressable memory (CAM) array, for a learn operation, or the like. A search engine can include a status memory block external to and independent of the CAM array. A status memory block (800) can include a number of memory sections (806-0 to 806-2) that each includes a number of bit locations for storing a free/not-free status of CAM entries in a hierarchical fashion. Corresponding control sections (808-0 to 808-2) can include priority encoders (812-0 to 812-2) that determine a first free element in a memory section for a next hierarchical level, as well as status aggregation logic (814-0 to 814-2) that can generate an aggregated status that is propagated to a previous hierarchical level.

Abstract: A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

Abstract: A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record.

Abstract: A content addressed storage device configured to maintain content address mapping is disclosed. A data object to be stored on the content addressed storage device and a local data object identifier by which the data object is known to the sending source are received from a sending source. A content address to be associated with the data object on the content addressed storage device is determined based at least in part on the contents of the data object. The data object is stored on the content addressed storage device in a storage location associated with the content address. A mapping that associates the local data object identifier with the content address is maintained on the content addressed storage device.

Abstract: A content addressed storage device configured to maintain content address mapping is disclosed. A data object to be stored on the content addressed storage device and a local data object identifier by which the data object is known to the sending source are received from a sending source. A content address to be associated with the data object on the content addressed storage device is determined based at least in part on the contents of the data object. The data object is stored on the content addressed storage device in a storage location associated with the content address. A mapping that associates the local data object identifier with the content address is maintained on the content addressed storage device.

Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB<0> and <1>). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL<0>, keyFIB<0> and keyFIB<1>).

Abstract: A method and a computer readable medium having executable instructions are provided. The method and instructions when executed generates a first look-up key from a group of look-up key units stored in a data storage, generation of the first look up key being completed prior to the completion of a key generation processing cycle. A next look-up key unit from the group of look-up key units stored in the data storage may be skipped over when the next look up key corresponds to a second look-up key that has a key length equal to or smaller than a predetermined key length. A third look-up key unit may be selected from the group of look-up key units, the third look-up key unit associated with a third look-up key having a key length greater than a second predetermined key length, the second predetermined key length being greater than the first predetermined key length. The first look-up key and a portion of the third look-up key sequentially may be output during the same output processing cycle.

Abstract: Methods and apparatus are disclosed for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation. Each of the lookup units is assigned a subset of the possible values of the entries and is programmed with the corresponding entries. In performing a lookup operation on a lookup word, only the lookup units possibly containing a matching entry are enabled which saves power and dissipates less heat. A lookup operation is then performed in the enabled lookup units to generate the lookup result. A lookup unit may correspond to an associative memory device, an associative memory bank, sets of entries within one or more associative memory devices or banks, a lookup control and a memory device, and/or any other lookup mechanism. In one implementation, the partitioning of elements is based on a Patricia tree representation of the possible entries.

Abstract: A priority encoder circuit can include a number of sectional encoder circuits that each encode “m” inputs signals into sets of “P” encoder outputs, where m>p. Each sectional encoder circuit can also output a group indication signal representing the activation of any of the received m encoding input signals. Priority encoder logic can prioritized the group indication signals. A memory can include a different storage location accessed by each prioritized group indication signal.

Abstract: A method and apparatus for parallelizing address-mapping and page referencing in a memory controller. The page referencing may apply an input address to two separate content addressable memory components along with masks from a configuration register identifying rank-bank bits, page status bits and non-column bits. The content addressable memories each determine if matching content is present generating a ‘hit’ or ‘miss.’ The hit and miss indicators are applied to combinational logic to determine whether to generate a CAS, RAS-CAS or PRE-RAS-CAS indicator.

Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and according to the rules used for generating the feature vectors corresponding to the stored document s such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more additional result columns coding for a similarity measure betw

Abstract: Intelligent allocation of programmable comparison operations may reduce the number of associative memory entries required for programming an associative memory (e.g., ternary content-addressable memory) with multiple matching definitions (e.g., access control list entries, routing information, etc.), which may be particularly useful in identifying packet processing operations to be performed on packets in a packet switching device. The higher-cost comparison operations, in terms of the number of associative memory entries required to natively support such operations, are allocated to one or more comparison evaluators (e.g., programmable logic and/or processing elements configured to evaluate one or more comparison operations) configured to evaluate an input value with one or more of the programmable comparison operations in order to generate and provide one or more values representing results of the evaluations to one or more associative memories for use in identifying the packet processing operations.

Abstract: A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

Abstract: A content addressable memory (CAM) is disclosed that includes a memory having a first port configured to write a 1-bit data to the memory and a second port configured to read and write N-bit data. To update the CAM, an N-bit zero data word is written to the second port at a first address A2 to erase N bits of the memory at address A2, then the first address A2 is combined with a data value A0 to form a second address A1. Finally, a value 1 is written to the first data port at the address A1. Reading the second port at the first address A2 will produce an N-bit data word having value 1 at bit position A0 and zeros at all other bit positions. The CAM may be configured in reconfigurable hardware using random access memory and used in a stream data interface circuit.

Abstract: Embodiments of the present invention are directed to a method and apparatus for receiving an input/output (I/O) request from a host computer that specifies an operation to be performed on a content addressable storage (CAS) system and determining which operation is specified by the request before receipt of the I/O request by a content addressable storage system. In another embodiment, an I/O request from a host computer is received by a first CAS which determines if the request is to be processed by another CAS system. When it is determined that the request is to be processed by another CAS system, the first CAS system may forward the request to the other CAS system. In another embodiment, an appliance receives an I/O request from a host computer to perform an operation that accesses a unit of content. The appliance may set up a communication session between the host and a CAS system so that the unit of content may be transmitted between the host and the CAS system without passing through the appliance.

Abstract: A self-referencing redundancy scheme in a content addressable memory may use a faulty bit table, populated during manufacturing, to indicate, not only the address of all the defective memory locations, but also the data which they should hold. Then, during read out, a read out state machine may access the faulty bit table, determine the data the faulty location should have held, and write that faulty data onto latches associated with the faulty memory elements.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: A search key construction system including search key sections, each coupled to an output of a first multiplexer having a first programmable control, a second multiplexer having a second programmable control and an output coupled to the first multiplexer, and a third multiplexer having a third programmable control and an output coupled to the first multiplexer is disclosed. The first programmable control can include a key source select to enable one of a first type path, a second type path, and a third type path. The first type path can include a designated section position from a packet header, the second type path can include a short field from a packet attribute, and the third type field can include a long field from a packet header.

Abstract: A method, system and program product for equitable sharing of a CAM (Content Addressable Memory) table among multiple users of a switch. The method includes reserving buffers in the table to be shared, the remaining buffers being allocated to each user. The method further includes establishing whether or not an address contained in a packet from a user is listed in a buffer in the table, if the address is listed, updating a time-to-live value for the buffer for forwarding the packet and, if the address is not listed, determining whether or not the user has exceeded its allocated buffers and whether or not the reserved buffers have been exhausted, such that, if the user has exceeded its allocated buffers and the reserved buffers have been exhausted, the address is not added to the table and the user is precluded from using any additional buffers in the network switch.

Abstract: A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.

Abstract: A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also presented.

Abstract: A method and system thereof for identifying records are described. Records on a node are distinguished from other records on the node by assigning each record a unique local identifier. When a record is moved from one node to another node, a unique global identifier is assigned to the record. A translation technique is employed to map the local identifier to the global identifier (and vice versa).

Abstract: A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands.

Abstract: A method and system for ordering addressees in address fields (141-143) is provided. The method includes entering a plurality of addresses in an address field (141-143) of a message; selecting an ordering policy (134); and ordering (132) the addresses in the address field (141-143) in accordance with the selected ordering policy. The ordering policy (134) may include general ordering policies such as alphabetical ordering, or flattering ordering in which the recipient's address is at the head of the address field. Weightings for individual addressees may be defined. Weightings may be absolute and/or relative to other addressees. An ordering policy (134) may be selected for each of the address fields “To:”, “Cc:”, and “Bcc:”.

Abstract: One embodiment is directed to a method for use in a computer system comprising at least first and second computers, wherein the first provides content addressable storage. A request to access a unit of data stored by the first computer is issued by the second computer and received by the first. In one embodiment, the unit of data comprises a first identifier identifying at least one digital asset and metadata relating to the at least one digital asset, and the request identifies the unit of data via a second identifier based, at least in part, on the content of the unit of data. In another embodiment, a request to access a unit of data is sent from a second computer and received at a first computer and identifies the unit of data via a content identifier based, at least in part, on the content of the unit of data. The content identifier is the only identifier that can be used in communication between the first and second computers to identify the unit of data.

Abstract: A segmented search line circuit device for content addressable memory is provided. This device includes a content addressable memory and a segmented unit, wherein the content addressable memory has a plurality of cells arranged in an array and a search line connected between each pair of adjacent cells. Moreover, a first segmented unit is connected between the cells to divide the cells into a plurality of segments to search and between a pair of the adjacent segments to cut off the search lines between the pair of the adjacent segments. Because the circuit of this device is divided into a plurality of segments to search, the circuit of the search line driver need not be modified. As a result, this circuit device can diminish the loading capacitance of the search line driver and reduce the power consumption with the segmented search method.

Abstract: Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread receives a signal from a last thread once the last thread has the reference to the data. The initial thread, in response to the signal, modifies the data and updates changes to the data within the cache and then sends another signal to a next thread, indicating that the next thread may now perform a volatile operation on the data within the cache.

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer readable media, mechanisms, and means for partitioning and filtering a search space of particular use for determining a longest prefix match thereon, such as for routing packets. One implementation uses one or more filtering mechanisms to filter portions of a lookup word against a first set of lookup values, such as, but not limited to the value of any corresponding portion of any entry in the search space. A set of possible matching prefixes defined by consecutive matching portions of the lookup word from the highest-order position are determined, and lookup operations are typically performed in parallel on each of these possible matching prefixes to generate a set of matching results (if any), which is typically used to identify the longest matching prefix.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular segment (102 and 104). If a search target value TARGET matches a programmable information value (PIV0 and PIV1), search operations may be performed in a segment (102 or 104). If a search target value TARGET does not match a programmable information value, (PIV0 and PIV1), search operations may be prevented within a segment (102 or 104).