Abstract: According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases.

Abstract: A host accessing memory devices by providing common address and command information on a parallel-connected serial bus to each of the memory devices and shifting data in the memory devices through a daisy-chain serial interface.

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.

Abstract: High availability (HA) protection is provided for an executing virtual machine. At a checkpoint in the HA process, the active server suspends the virtual machine; and the active server copies dirty memory pages to a buffer. During the suspension of the virtual machine on the active host server, dirty memory pages are copied to a ring buffer. A copy process copies the dirty pages to a first location in the buffer. At a predetermined benchmark or threshold, a transmission process can begin. The transmission process can read data out of the buffer at a second location to send to the standby host. Both the copy and transmission processes can operate asynchronously on the ring buffer. The ring buffer cannot overflow because the transmission process continues to empty the ring buffer as the copy process continues. This arrangement allows for using smaller buffers and prevents buffer overflows, and thereby, it reduces the VM suspension time and improves the system efficiency.

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

Abstract: In one of the storage control apparatuses in the remote copy system which performs asynchronous remote copy between the storage control apparatuses, virtual logical volumes complying with Thin Provisioning are adopted as journal volumes to which journals are written. The controller in the one of the storage control apparatuses assigns a smaller actual area based on the storage apparatus than in case of assignment to the entire area of the journal volume, and adds a journal to the assigned actual area. If a new journal cannot be added, the controller performs wraparound, that is, overwrites the oldest journal in the assigned actual area by the new journal.

Abstract: A storage battery control device detects an overhead wire supply current value showing a sum of a current value output from a storage battery and a current value output from a transformer substation, and charging or discharging of the storage battery is controlled so that a charging rate of the storage battery becomes a charging rate target value when the detected overhead wire supply current value is less than a first threshold. In addition, charging or discharging of the storage battery is controlled so that the output voltage of the storage battery control device is maintained at a constant voltage control mode when the detected overhead wire supply current value is greater than or equal to the first threshold.

Abstract: An A/D converter that is attached to a programmable controller (PLC) and sequentially converts an analog value inputted from outside into a digital value. The A/D converter includes: a shared memory that can read-access from a CPU unit that controls the entire PLC and includes a log storage area with a ring buffer configuration for sequentially logging the digital value and a parameter storage area for storing a head pointer serving as a parameter indicating a position where a next log data is stored; and a logging executing unit that writes a digital value in an address indicated by the head pointer in the log storage area as log data and updates the head pointer.

Abstract: Embodiments of systems, apparatuses, and methods for a circular buffer in a redundant virtualization environment are disclosed. In one embodiment, an apparatus includes a head indicator storage location, an outgoing tail indicator storage location, a buffer tail storage location, and fetch hardware. The head indicator, outgoing tail indicators, and buffer tail indicators are to indicate a head, outgoing tail, and buffer tail, respectively, of a circular buffer. The fetch hardware is to fetch from the head of the circular buffer and advance the head no further than the outgoing tail. The buffer tail is to be filled by software and advanced no further than the head.

Abstract: An audio context object gathers multiple channels of audio data from an audio device and stores each channel of data separately in a ring buffer. Clients of the audio context can request any number of channels of data at any interval from the audio context. Multiple clients can share the same audio device. The ring buffer used by the audio context object stores the channels of audio data in a two-dimensional array such that each channel of audio data is stored in contiguous memory.

Abstract: The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

Abstract: Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.

Abstract: The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the shared use of such external volumes by a plurality of available virtualization storage devices. By virtualizing and incorporating the external volume of an external storage device, a first virtualization storage device is able to provide the volume to a host as though it is an internal volume. When the load of the first virtualization storage device increases, a second virtualization storage device 2 is newly introduced, and connected to the storage system. When a transfer direction is issued from a management terminal, the external volume relating to the selected logical volume is transferred from the first virtualization storage device to the second virtualization storage device.

Abstract: A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.

Abstract: An apparatus and a method for operating on data at a cache node of a data grid system is described. An asynchronous future-based interface of a computer system receives a request to operate on a cache node of a cluster. An acknowledgment is sent back upon receipt of the request prior to operating on the cache node. The cache node is then operated on based on the request. The operation is replicated to other cache nodes in the cluster. An acknowledgment that the operation has been completed in the cluster is sent back.

Abstract: A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.

Abstract: Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers.

Abstract: A beltway mechanism that takes advantage of atomic locking mechanisms supported by certain classes of hardware processors to handle the tasks that require atomic access to data structures while also reducing the overhead associated with these atomic locking mechanisms. The beltway mechanisms described herein can be used to control access to software and hardware facilities in an efficient manner.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: Embodiments of the present invention provide a method and system, in a network storage system, for producing a balanced reconstruction load across storage devices (disks) in a storage array (array) using a scalable declustered layout. A scalable declustered layout is a logical configuration of parity groups across storage units (disk segments) which spread the chunk load and total share load of parity groups across disks in the array. Creation of a scalable declustered layout is achieved by sequentially selecting and allocating each chunk of a new (prospective) parity group according to the then-current load on each disk. The scalable declustered layout is then implemented on the disks to produce a balanced reconstruction load across disks when recovering from a disk failure.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: Methods and systems are provided for aging EV-DO pages in a queue based on latency-sensitivity. An access node receives data for access terminals, and responsively generates pages and adds them to the back of a queue. The access node associates a respective aging value with any latency-tolerant pages. The access node transmits the pages in the queue, which involves: (a) assessing the pages on a first-in, first-out basis; (b) transmitting latency-sensitive pages when those pages reach the front of the queue; (c) sending latency-tolerant pages to the back of the queue (and incrementing their aging values) when those pages reach the front of the queue with an aging value that is less than a maximum-delay parameter; and (d) transmitting latency-tolerant pages when those pages reach the front of the queue with an aging value that is greater than or equal to the maximum-delay parameter.

Abstract: The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the shared use of such external volumes by a plurality of available virtualization storage devices. By virtualizing and incorporating the external volume of an external storage device, a first virtualization storage device is able to provide the volume to a host as though it is an internal volume. When the load of the first virtualization storage device increases, a second virtualization storage device 2 is newly introduced, and connected to the storage system. When a transfer direction is issued from a management terminal, the external volume relating to the selected logical volume is transferred from the first virtualization storage device to the second virtualization storage device.

Abstract: In one embodiment, a mechanism for a reader page for a ring buffer is disclosed. In one embodiment, a method for implementing a reader page for a ring buffer includes allocating, by a processing device, a block of storage separate from a ring buffer as a reader page for a reader of the ring buffer, the ring buffer stored in a physical memory device, and swapping, by the processing device, a head page of the ring buffer with the reader page so that the reader page is part of the ring buffer and the head page is no longer attached to the ring buffer.

Abstract: A method may include comparing a first content addressable memory (“CAM”) entry with a first key value to generate a first comparison result; comparing each of multiple second CAM entries with a second key value to generate multiple second comparison results; and generating a match signal if the first key value matches the first CAM entry and the second key value matches at least one of the multiple second CAM entries.

Abstract: Methods, apparatuses, and systems directed to efficient compression processing in system architectures including a control plane and a data plane. Particular implementations feature integration of compression operations and mode selection with a beltway mechanism that takes advantage of atomic locking mechanisms supported by certain classes of hardware processors to handle the tasks that require atomic access to data structures while also reducing the overhead associated with these atomic locking mechanisms.

Abstract: In one embodiment, a mechanism for a lockless ring buffer in overwrite mode is disclosed. In one embodiment, a method for implementing a lockless ring buffer in overwrite mode includes aligning memory addresses for each page of a ring buffer to form maskable bits in the address to be used as a state flag for the page and utilizing at least a two least significant bits of each of the addresses to represent the state flag associated with the page represented by the address, wherein the state flag indicates one of three states including a header state, an update state, and a normal state.

Abstract: A method for accessing cells of a ring buffer by one or more writers, wherein the one or more writers are prevented from simultaneously accessing a cell of the ring buffer. In addition, a method for accessing cells of a ring buffer by one or more readers, wherein the one or more readers are prevented from simultaneously accessing a cell of the ring buffer.

Abstract: A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.

Abstract: The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the shared use of such external volumes by a plurality of available virtualization storage devices. By virtualizing and incorporating the external volume of an external storage device, a first virtualization storage device is able to provide the volume to a host as though it is an internal volume. When the load of the first virtualization storage device increases, a second virtualization storage device 2 is newly introduced, and connected to the storage system. When a transfer direction is issued from a management terminal, the external volume relating to the selected logical volume is transferred from the first virtualization storage device to the second virtualization storage device.

Abstract: PET system including array, data processing, and data acquisition. Data acquisition includes one-to-N channel write striping, N-to-one channel read unstriping, N data storage elements, and control logic. Control logic allocates (statically or dynamically) write/read access to data storage elements. Dynamic allocation can be conditional, e.g., that data storage elements be available to receive all input data from array. Embodiments include an input buffer where the condition is determined dynamically based on capacity of the input buffer to temporarily preserve all input data supplied during periods data storage element unavailability. Communication between array and data acquisition can be Fibre Channel simplex implementing only FC-0, FC-1. Data storage elements have data handling bandwidth equal to or greater than (data output rate /N) plus (data input rate/N). Control logic, write striping, read unstriping can be implemented in FPGA. Data storage elements can form a Redundant Array of Independent Disks, e.

Abstract: A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address signal, and a write permission signal. The storage unit writes and stores input data, in response to the first control signal. The write permission signal is received from an external source and indicates whether to protect the written data.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: A scanning optimization manager scans files for malicious code. The scanning optimization manager creates listings of the portions of scanned files accessed during the scanning. The scanning optimization manager proceeds to utilize these listings of accessed portions of files as I/O hints to optimize subsequent scans of the files for malicious code.

Abstract: The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the shared use of such external volumes by a plurality of available virtualization storage devices. By virtualizing and incorporating the external volume of an external storage device, a first virtualization storage device is able to provide the volume to a host as though it is an internal volume. When the load of the first virtualization storage device increases, a second virtualization storage device 2 is newly introduced, and connected to the storage system. When a transfer direction is issued from a management terminal, the external volume relating to the selected logical volume is transferred from the first virtualization storage device to the second virtualization storage device.

Abstract: In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to track the total number of transmission words in the FIFO array. A dynamic threshold controller tracks transmission word insertions and deletions in the FIFO array for a predetermined period of time and provides a threshold level adjustment signal based on the tracked transmission word insertions and deletions and a transmission word threshold level. A FIFO level adjuster provides transmission word insert and delete commands and adjusts the threshold level of the FIFO array in response to the threshold level adjustment signal.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: A network-attached disk (NAD) system is disclosed that includes an NAD device for receiving a disk access command from a host through a network, and a device driver at the host for controlling the NAD device through the network, where the device driver creates a virtual host bus adapter so that the host recognizes the NAD device as if it is a local device to the host. The host may run the UNIX or Windows family of operating systems. The NAD device includes a disk for storing data, a disk controller for controlling the disk, and a network adapter for receiving a disk access command from the host through a network port.

Abstract: A network-attached disk (NAD) system is disclosed that includes an NAD device for receiving a disk access command from a host through a network, and a device driver at the host for controlling the NAD device through the network, where the device driver creates a virtual host bus adapter so that the host recognizes the NAD device as if it is a local device to the host. The host may run the UNIX or Windows family of operating systems. The NAD device includes a disk for storing data, a disk controller for controlling the disk, and a network adapter for receiving a disk access command from the host through a network port.

Abstract: A method is described for reading out sensor data from an intermediate memory written by at least one sensor to the intermediate memory at a data-transfer rate (Tpas). A sampling rate (Tsg) is selected in such a way as to avoid an overflow of the intermediate memory and all buffered sensor data is read into a control unit memory at the predetermined sampling rate (Tsg), the intermediate memory generating a message (RBE) if no new sensor data is present in the intermediate memory at the time of sampling.

Abstract: Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule.

Abstract: A method and apparatus to reduce the number of rule entries used to implement ranging matching in a Content Addressable Memory (“CAM”) array. A first CAM entry is stored in a single CAM cell of an array of CAM cells. The first CAM entry is compared with a first key entry of the CAM array to generate a first comparison result. Each of multiple second CAM entries is stored in corresponding multiple CAM cells of the array of CAM cells. The multiple second CAM entries are compared with a second key entry to generate multiple second comparison results. A match signal is generated by the CAM array if the first key entry matches the first CAM entry and the second key entry matches one of the multiple second CAM entries.

Abstract: An audio context object gathers multiple channels of audio data from an audio device and stores each channel of data separately in a ring buffer. Clients of the audio context can request any number of channels of data at any interval from the audio context. Multiple clients can share the same audio device. The ring buffer used by the audio context object stores the channels of audio data in a two-dimensional array such that each channel of audio data is stored in contiguous memory.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: An audio input/output control apparatus, in which the speed difference between writing speed in writing audio data to a ring buffer and reading speed in reading out the audio data under a constant speed is calculated. When a read-address is forcibly changed according to the speed difference, between the signal level of the audio data corresponding to a read-address before the change and the signal level of the audio data corresponding to a read-address after the change, an address position at which the signal level change is less than a predetermined value is determined as a read-address after the change. So, the amount of signal processing can be significantly reduced, and the quality of audio data can be maintained.

Abstract: In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to track the total number of transmission words in the FIFO array. A dynamic threshold controller tracks transmission word insertions and deletions in the FIFO array for a predetermined period of time and provides a threshold level adjustment signal based on the tracked transmission word insertions and deletions and a transmission word threshold level. A FIFO level adjuster provides transmission word insert and delete commands and adjusts the threshold level of the FIFO array in response to the threshold level adjustment signal.

Abstract: A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF1, FF2) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.

Abstract: A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.

Abstract: An apparatus and method for an improved stack comprises an advantageous indexing scheme and stack arrangement allowing more efficient performance of stack operations. The most-recently-used stack item appears at the top of the stack and the least-recently-used item is at the bottom of the stack. Values in between the top and bottom items are ordered from top to bottom with succeedingly less recently used items. An indexing scheme is used to indirectly reference locations of the stack items in the stack. A set of registers is used to reference the locations of the stack items in an embedded memory array. The registers function as pointers to the memory array locations. To promote an item to the top of the stack, the item is identified as the most-recently-used and the contents of the other registers are changed to specify the new locations, e.g. these pointers are shifted down one.