Abstract: A system and method for controlling the direction of data flow in a memory system is provided. The system comprising memory devices, a memory controller, a buffering structure, and a data flow director. The memory controller sends data, such as read-data, write-data, address information and command information, to the memory devices and receives data from the memory devices. The buffering structure interconnects the memory device and the memory controller. The buffering structure is adapted to operate in a bi-directional manner for the direction of data flow therethrough. The data flow director, which may reside in the buffering structure, the memory controller, the memory devices, or an external device, controls the direction of data flow through the buffering structure based on the data transmitted from the memory controller or the memory device.

Abstract: A dynamic data queuing mechanism for network packets is disclosed. A three-dimensional coil may be expanded or contracted in length. In addition, the size of each loop of the three-dimensional coil may be adjusted. Moreover, simple circular queue and dynamic buffer management techniques are combined to implement circular queues that may be adjusted in size. Size adjustment, in turn, causes an entire queue either to expand or contract. Circular queue size is changed dynamically, without any copying or moving of queue data. This advantage is attained with little overhead added to conventional circular queues, and is useful in reducing memory requirements for simple circular queues by adjusting queue size as needs change. This is particularly useful for multiple queues that share the same memory space.

Abstract: An apparatus and method for creating and maintaining a cyclic or circular buffer are implemented using logical blocks corresponding to the physical blocks of the buffer. The logical blocks are mapped to the physical blocks of the cyclic buffer, and are used to create an index table for the buffer. Each entry in the index table corresponds to one or more blocks in the buffer, and has a logical block number respectively associated with a buffer block. When information from the buffer is accessed, the index table is consulted to determine if the requested information is stored in the buffer. If the information is stored in the buffer, the logical block number corresponding to the information is retrieved from the entry and translated into a corresponding physical block number. Using logical block numbers allows simple determination of whether the buffer block is valid, and how new or fresh the buffer block is without requiring a generation or cycle number.

Abstract: A method and system for accommodating at least one high priority data element from a plurality of data elements written into a ring buffer including a processor that preempts a ring buffer by modifying at least one of the data elements previously written to the ring buffer to create modified data elements in response to detecting a high priority data element to be written into the ring buffer. The processor modifies the plurality of data elements previously written to the ring buffer to create the modified data elements. The processor resubmits to the ring buffer at least one of the data elements corresponding to at least one of the modified data elements for execution by a graphics co-processor in response to processing the at least one high priority data element.

Abstract: A method and apparatus for using a debug bus as a capture buffer are described. In one embodiment, the invention is directed to an apparatus for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; logic for comparing a value of the counter with a preselected register address on each count of the counter; and logic for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.

Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal.

Abstract: A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a “circular increment” or “circular decrement” instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these “bounds” flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed.

Abstract: A memory device that includes a digital storage unit having a data storage unit that stores data in a systematic arrangement, a systematic arrangement of plural data portals each provided for accessing the data locations; a generator that produces systematic, cyclical, relative movement between the data locations and the data portals; and a controller that selects at least one of the data portals in accordance with an input command and a calculation based on the relative movement. When one or more of the plural portals is selected, data can be input or output in a manner which is predictable, straight-forward, free of scheduling constraints, and very efficient, without contention between the separate portals.

Abstract: A first-in first-out (FIFO) storage device for storing data including continuous identical values, which is reduced in a required circuit scale and increased in a reading operation speed, and which comprises a memory region (13) provided with a counter unit and a data unit corresponding to a plurality of addresses, a comparison unit (11) for checking whether or not a new input data is identical with an input data one data ahead of the new one, and a write control unit (12) for controlling, based on the checked result by the comparison unit (11), to write the current input data into a new address in the data unit of the memory region (13) when the new input data is not identical with the one-data-ahead input data and for controlling to count up a count value in a one-address-ahead address in the counter unit of the memory region (13) when the two data are identical with other.

Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.

Abstract: A multi-threaded microprocessor with support for packet header splitting during receive packet processing operations and packet header splicing during transmit packet processing operations, as well as optimized recovery of transmit resources, is presented.

Abstract: A method of transferring a block of data from a first to a second circular buffer of a computer system. The method comprises notifying the DMA controller of the source and destination addresses for the transfer, the sizes of the circular buffers, and the size of the data block to be transferred. At the DMA controller, respective base and rollover addresses of the circular buffers are identified. Data is read from the first circular buffer starting at the source address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached. Data is written to the second circular buffer starting at the destination address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached.

Abstract: A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.

Abstract: A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon completing a filter process and determining that the ring-buffer data stored in said ring-buffer memory space is no longer necessary after the filter-process is carried out.

Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.

Abstract: The present invention provides a register-indirect addressing mode using modulo arithmetic to transpose addresses for digital processing systems. The preferred systems and methods permit direct access of column data, which improves matrix computation significantly. The overhead of transpose mode is minimal because it can be implemented, if desired, by sharing hardware and/or software used in circular buffers. Transpose addressing mode also reduces program size and processor power consumed by reducing the sequence of instruction cycles.

Abstract: The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.

Abstract: A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. The method can be extended to enable three or more write pointers for even higher frequency operation.

Abstract: To permit safe writing of the pointer (P) pointing to the current record in a cyclic memory or ring memory, e.g. an EEPROM, the new record (D'#3) is written to the memory location (R3) containing the oldest record, and then the pointer (P) is updated. The pointer (P) consists of a first pointer (P1, P1*) and a second pointer (P2, P2*) redundant with respect to the first pointer. Each pointer contains a check value in the form of the inverse or complement code of the actual pointer. Due to the second pointer and the check value, the pointer is written with optimal safety. In case of a disturbance in the course of pointer updating, the old first pointer can later alternatively be recovered from the second pointer or the second pointer updated with the aid of the new first pointer.

Abstract: The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.

Abstract: An apparatus for accessing a banked embedded dynamic random access memory device is disclosed. The apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.

Abstract: A hardware based modulo addressing scheme is described that is fast and makes efficient use of logic. The scheme uses a subtractor, multiplexers and AND/OR logic to produce modulo addresses to address, for example, a circular buffer in a memory. The buffer is defined by the user based on start and end addresses and an offset value. The offset may be positive or negative and may be greater than one.

Abstract: A loop buffer for storing and holding instructions executed within loops for digital signal processing. Control logic detects the beginning and ending of a loop to signal the loop buffer control logic to start instruction execution in a cyclical fashion using the instructions stored within the loop buffer. After completion of the required number of loops, the instructions in the loop buffer are overwritten with new instructions until the next loop is to be processed. The loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.

Abstract: A two-stage, pipelined modulo address generator (MAG) (30′) for generating from a current pointer into a circular buffer of size L, a next pointer into the buffer, is comprised of a pointer generation stage (32′) and a modulo correction and pointer selection stage (34′), each adapted to operate in a selected one of two modes. In the first operating mode: the pointer generation stage (32′) generates a sequential pointer which is a selected offset from the current pointer; and the modulo correction and pointer selection stage (34′) generates, modulo L, a modulo corrected sequential pointer, and provides as the next pointer the sequential pointer, if it is in the buffer, and the modulo corrected sequential pointer, otherwise.

Abstract: Data is written into a circular buffer at an address pointed to by a write pointer. A number is written into the address with the data. Each time the circular buffer is traversed by the write pointer this number increments modulo a predetermined number. This number makes the circular buffer appear longer than it really is and can be used to identify underruns. The buffer has application in a segmentation and reassembly device for ATM constant bit rate services.

Abstract: A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a “circular increment” or “circular decrement” instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these “bounds” flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed.

Abstract: A distributed digital imaging processing system having a number of processing units and circular FIFO buffers connected together using data transforming streams. Processing units read data from buffers using a transforming read streams. These read streams reorder the buffer data to form patches representing neighborhood pixels and may provide the same data multiple times. After processing a patch, a processing unit writes the resultant patch into a buffer using a transforming write stream which reorders the data into the storage format of the buffer. Several buffers can feed a single processor and one processor can feed several buffers. All the details of each data stream (buffer, current buffer location, patch size, access pattern) are stored in a table entry, along with a pointer to the data stream that it must follow in the buffer to avoid the hazards of reading and writing data out of order.

Abstract: Systems and methods are disclosed in which a computer system having main memory and persistent memory is caused to perform a method for caching related objects. The computer system receives a plurality of objects from an origin server and computes a hash value based on source information about an object. Then the computer system stores the object based on the hash value with other related objects. Additionally, a computer system consistent with the present invention may retrieve related objects from the cache by performing a batch read of related objects.

Abstract: A processor comprises an instruction cache that stores a cache line of instructions and an execution engine for executing the instructions, along with a buffer to store a plurality of entries. A first logic circuit divides the cache line into instruction bundles, each of which gets written into an entry of the buffer. A second logic circuit reads out a number of consecutive instruction bundles from the buffer for dispersal to the execution engine to optimize speculative fetching and maximizing instruction supply to the execution resources of the processor.

Abstract: A register read circuit reads out register values of X (natural number) registers corresponding to selection register numbers. The registers are each assigned to a unique register number. Register numbers that correspond to the X registers to be selected among the registers are given to the register read circuit as the selection register numbers. The register read circuit includes register value selection circuits each of which selects the register value of one of the X registers corresponding to the register numbers associated with remainders of modulo of the register numbers by Y, which is a natural number larger than or equal to X. Each of the selection circuits selects and outputs one of register values from the registers in response to a selection control input based on the given register number, the register value selection circuits being correspondent to the remainders.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: The present invention relates to a FIFO (First In First Out) memory control circuit for controlling FIFO memory which is used in various electronic devices. Specifically, the present invention relates to a FIFO memory control circuit capable of performing asynchronous read/write control hen a write clock and a read clock are different and it is known or determined which of these clocks has a higher clock frequency.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle.

Abstract: The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.

Abstract: A data processing system having a central processing unit (CPU) with address generation circuitry for accessing a circular buffer region in a non-aligned manner is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory ports. A data transfer address for each load/store instruction is formed by fetching the instruction (600), decoding the instruction (610) to determine instruction type, transfer data size, addressing mode and scaling selection.

Abstract: A method and apparatus accepts a query to update or delete rows in a temporal table of a database. The query may describe which rows are to be updated, a calculation for the value to be used to update each row of the table, and a period of validity, during which the changes are to take place. The method and apparatus creates a sequence of queries and SQL program elements that together can make up an SQL program that will execute the query received. The SQL program can split any row of the table to be updated into multiple rows so that each of the multiple rows of the table to be changed have an effective period during which no changes occur in the table to be changed or any other tables referenced in the query received and no effective periods span the beginning or the end of the period of validity. The specified change may then be made to the resulting rows, and rows that are adjacent in time with identical values may be collapsed into a single row.

Abstract: Provided is a system, method, and program for managing read and write requests to a cache to process enqueue and dequeue operations for a queue. Upon receiving a data access request to a data block in a memory, a determination is made as to whether any data block is maintained in a cache line entry in the cache. If so, a cache line entry maintaining the data block is accessed to perform the data access request. A first flag, such as a read flag, associated with the accessed cache line entry is set “on” if the data access request is a read request. Further, if the data access request is a write request to update the data block in the memory, a second flag, such as a write flag, associated with the cache line entry including the data to update may be set “on”. The update data may be data to be enqueued onto a queue, where the queue may be, but is not limited to, a circular buffer in the memory having a head and tail pointer.

Abstract: Mechanisms for improving the efficiency of bus-request scheduling are provided. In a read-write segregation mechanism the type of a selected entry in a buffer is determined. If the type of the selected entry matches the type of the last issued entry, or if there are no further entries in the buffer that match the last issued entry, the request is issued to the system bus. A temporal ordering mechanism associates a request sent to a buffer with an identifier, the identifier designating a time at which the request was originally generated. The request identifier is modified when a prior request is issued, and thereby reflects a history of prior issuances. A request is issued when the historical information recorded in the identifier indicates that the request is the earliest-issued pending request in the buffer. A third mechanism for increasing the efficiency of bus request scheduling in a buffer includes segregating lower priority cache eviction requests in a separate write-out section of the buffer.

Abstract: An information appliance receives streaming information and includes a buffer, a writer module, a reader module and a synchronizer. The buffer has a plurality of storage locations, a logical head, a logical tail and a valid data area between the logical head and the logical tail. The logical head and the logical tail move sequentially through the plurality of storage locations in a first logical direction. The writer module has a write position at the logical head of the buffer. The writer module receives the streaming information and writes the streaming information to the buffer at the write position. The reader module is coupled to the buffer and has a first read position which is temporally movable with respect to the write position. The synchronizer is coupled to the writer module and the reader module and maintains the first read position within the valid data area.

Abstract: Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer management logic 802 is configured to be operable to apply a modifier to a virtual buffer index held in the address storage to derive a modified virtual buffer index and to apply a buffer offset held in the offset storage to the modified virtual buffer index to derive a physical address for addressing a circular buffer. By employing virtual addressing to a buffer index for a circular buffer management, it is possible to make efficient use of memory resources. One or more circular buffers can be located contiguously with respect to each other and/or other data in memory, avoiding fragmentation of the memory. The buffer index forms a pointer for the circular buffer.

Abstract: Data is written into a circular buffer at an address pointed to by a write pointer. A number is written into the address with the data. Each time the circular buffer is traversed by the write pointer this number increments modulo a predetermined number. This number makes the circular buffer appear longer than it really is and can be used to identify underruns. The buffer has application in a segmentation and reassembly device for ATM constant bit rate services.

Abstract: A method and an apparatus for storing data provide data memory in a systematic, cyclical arrangement, provide plural data portals in an arrangement defined by modular arithmetic, and provide sequential, relative movement between the data memory and the data portals. When one or more of the plural portals is selected, data can be input or output in a manner which is predictable, straight-forward, free of scheduling constraints, and very efficient, without contention between the separate portals. Also disclosed are a method and apparatus which provide data memory in a systematic, cyclical arrangement, provide a systematic arrangement of plural data outputs, and provide sequential, relative movement between the data memory and the data outputs. The memory devices of the present invention can be designed so that the memory device circulates data either through or past fixed portals. Alternatively, the data can be stored in fixed locations and the portals moved from location to location.

Abstract: A system LSI has a MPU and a HDC (72) in which the HDC (72) incorporates a CIU (721). The CIU (721) decodes addresses transferred from a CPU (73), reads program codes stored in memories such as a ROM (13) and a SRAM (14) in the HDC (72) when the addresses indicate memory fields in the memories, and outputs the obtained program codes to the CPU (73).

Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.

Abstract: Efficient support of synchronization in parallel processing is supported by methods for building two data structures that are optimal in that they permit simultaneous access to multiple readers and one writer without using any synchronization constructs such as locks and/or any special instructions. The structures rely on atomic read and/or write of some simple integral values to an underlying, actual or emulated, shared memory. No copying is required of any reader or writer. Each structure comprises a first-in-first-out (FIFO), constant-space, circular queue in which each reader and writer tracks shared bookkeeping data such as queue pointers. Readers are impure since they too write bookkeeping data. If a position of interest for access is beyond a boundary defining legitimate access, say trying to read an empty queue or write to a full queue, then access to the position is prevented until legitimization occurs. One of the structures can use the space in its queue to full capacity.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: The present invention provides a stack machine for executing a plurality of instructions one by one. The stack machine comprises an operation folder and an execution unit. The operation folder is used for checking if one or more instructions of a predetermined number of instructions following a specific instruction in a predetermined sequence can be folded with the specific instruction according to a POC folding rule. If they are foldable, these instructions will be combined to form a new instruction. The execution unit is used for executing instructions which cannot be folded by the operation folder or new instructions generated by the operation folder one by one. The instructions are folded to enhance operation efficiency of the stack machine.

Abstract: The inventive state mechanism assigns N+1 tags to N versions of an object stored in N memory areas. Thus, one tag is unused. An additional tag is used as a null or uninitialized tag. The other tags are assigned in a particular precedence order to revisions as they are stored. Thus, each assigned tag, except the null tag, has both a unique predecessor as well as a unique successor tag. The last tag of the sequence is lower in precedence to the first tag of the sequence, and this forms the cyclic relationship. The unused tag is used to determine the tag that is to be assigned to the next revision. The unused tag is also used to determine which revision is the most current revision. The inventive state mechanism is used by a memory management controller in maintaining the revisions.

Abstract: A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data.

Abstract: Systems and methods for constructing and using filtering trees to compare events, data, or other instances of objects defined in an object-oriented schema against one or more query-based definitions. The filtering trees correspond to the logical expressions of one or more query-based definitions, and represent the structure of the computer-executable instructions for comparing events with the definitions. The filtering trees can be traversed so as to simultaneously compare the parameters of an event against multiple logical expressions. The filtering tree is traversed in a top to bottom cascading fashion until a leaf node is encountered in a process that is conceptually equivalent to processing the logical operations associated with the nodes. When a leaf node is encountered, an ordered set of logical values associated with the leaf node indicates which, if any, of the definitions are satisfied by the event.