Abstract: A large FIFO memory device has its total available memory capacity partitioned into memory sections. The partitions are in the form of programmable delimiters in order to determine flexibly the size of the memory sections.

Abstract: A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously and handling the interactions between the queues of the cache levels. The cache unit includes a non-blocking cache receiving data access requests from a functional unit in a processor, and a miss queue storing entries corresponding to data access requests not serviced by the non-blocking cache. A victim queue stores entries of the non-blocking cache which have been evicted from the non-blocking cache, while a write queue buffers write requests into the non-blocking cache. Controller logic is provided for controlling interaction between the miss queue and the victim queue. Controller logic is also provided for controlling interaction between the miss queue and the write queue. Controller logic is also provided for controlling interaction between the victim queue and the miss queue for processing cache misses.

Abstract: A method and an apparatus for operating a circulating memory that can be addressed by a write pointer and/or a read pointer are disclosed. The method and the apparatus are distinguished by the fact that a jump of the write pointer and/or of the read pointer from the end of the memory to the beginning of the memory and/or vice versa is signaled.

Abstract: The present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit suspends operation of the stack cache and causes the spill control unit to store the valid data words in the slow memory unit or data cache unit. After the valid data in the stack cache are saved, the overflow/underflow unit equates the cache bottom pointer to the optop pointer.

Abstract: A system provides a write buffer with random access snooping capability. A random access write buffer includes a write buffer controller and a random access memory (RAM) containing a content addressable memory (CAM) address store and a random access memory data store. The CAM compares an input write address from a producer to the addresses present in the address store. If the input write address is "related" to an address present in the address store, the CAM detects an address hit. The indication of an address hit is provided to the write buffer controller which signals the data store to store the input write data in the existing rank of the data store associated with the "related" address detected by the CAM. The CAM also detects whether an input read address provided by a producer to a consumer is "related" to an address in the address store.

Abstract: An apparatus and method for an improved stack comprises an advantageous indexing scheme and stack arrangement allowing more efficient performance of stack operations. The most-recently-used stack item appears at the top of the stack and the least-recently-used item is at the bottom of the stack. Values in between the top and bottom items are ordered from top to bottom with succeedingly less recently used items. An indexing scheme is used to indirectly reference locations of the stack items in the stack. A set of registers is used to reference the locations of the stack items in an embedded memory array. The registers function as pointers to the memory array locations. To promote an item to the top of the stack, the item is identified as the most-recently-used and the contents of the other registers are changed to specify the new locations, e.g. these pointers are shifted down one.

Abstract: In accordance with the preferred embodiment of the present invention, a first-in-first out queue includes a buffer for storing data. A write pointer indicates a next position for data to be written into the buffer from an external interface. An input pointer indicates a next position for data to be read out to processing circuitry. An output pointer indicates a next position for data which has been processed by the processing circuitry to be returned to the buffer. A read pointer indicates a next position for data to be read out of the buffer to the external interface.

Abstract: A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is added to the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is empty. Data elements are removed from the queue in the order in which they were stored (first-in-first-out) and a manner that allows multiple, concurrent access to the queue. When the queue is accessed to remove a data element the element is first tested. If it is non-zero, the removal process continues; if zero, the queue is considered empty. The management of the queue permits dynamic re-sizing (i.e., making the queue larger or smaller) while data elements are being added and/or removed.

Abstract: Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than or equal to the write address. When the write address for the FIFO queue is less than the read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than the write address plus a maximum depth of the FIFO queue. A first read transaction of the first transaction size from the FIFO queue is performed only when the first condition flag is true.

Abstract: The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow.

Abstract: The present invention provides an improved disc drive. In one embodiment of the present invention a disc drive capable of spinning a disc, which contains more than one type of data is disclosed. A first type of data is associated with a first speed, and a second type of data is associated with a second speed that is faster than the first speed. The disc drive includes a drive mechanism, which may spin the compact disc at the first and second speeds and retrieve data from the compact disc at either speed. The disc drive also includes an elastic buffer, which is in communication with the drive mechanism. The buffer receives data from the drive mechanism at a variable input data rate and outputs data at a variable output data rate. Whereby when the drive mechanism spins the compact disc at the second speed the buffer may receive the first type of data without causing the drive mechanism to slow down to the first speed, and the buffer may output the first type of data at the variable output data rate.

Abstract: A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.

Abstract: An HSP communication system includes a host computer which executes a software portion of an HSP modem and a device containing a digital-to-analog converter (DAC). In response to interrupts, the host executes an update routine that generates and writes samples to a software circular buffer in memory of the host computer. The samples represent amplitudes of an analog signal complying with a desired communication protocol. A direct transfer moves samples from the software circular buffer to a hardware circular buffer the device, and the DAC converts the samples from the hardware circular buffer into an analog communication signal. In an exemplary embodiment, the hardware portion is coupled to a PCI bus in the host computer, and direct transfers are according to the PCI bus master protocol. In environments such as multi-tasking systems, the host may skip interrupts or otherwise not provide new samples when required.

Abstract: A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

Abstract: An initiating processing unit is normally occupied during the programming of flash EEPROMs. The time of occupation becomes ever longer with increasing age and degree of utilization of the flash EEPROMs. Here, the processing unit uses an initiatable interrupt routine, which triggers a programming of the flash EEPROM and is then terminated in order to use the programming to further process a main program at the same time. A timer function in a processing unit is used to trigger an interrupt routine. The interrupt routine checks the initial conditions and in the case when an initial condition has been fulfilled, the programming of the flash EEPROM is triggered, whereupon the execution of the main program continues in the processing unit during the programming.

Abstract: It is possible to continuously obtain the function of FILO for plural sets of data while reducing regions for storing the data. A string of data input from a memory M0 is shifted to a memory M3, and is switched back and read from the memory M0. Consequently, the function of FILO can be obtained for the same string. On the other hand, a string of data input from the memory M3 is shifted to the memory M0, and is switched back and read from the memory M3. Consequently, the function of FILO can also be obtained for the same string. With these two data strings keeping a push-pull relationship each other, the data are shifted among the memories M0 to M3. Therefore, the number of elements of each data string is enough for that of required memories.

Abstract: The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.

Abstract: A circular buffer in a system for processing audio samples wherein the buffer includes a sample window, the length of which is the length of a plurality of samples, the length of the circular buffer is a multiple of the length of the sample window, and the entire sample window is treated as a contiguous linear address space on each iteration of the processing system, that is moved through the physical multiple sample length buffer between iterations of the processing system, and is reset to the beginning every sample window number of iterations of the processing system. The circular buffer substantially reduces the number of address calculations in processing systems where every buffer position is addressed on every iteration and where circular addressing is not provided in hardware.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: The present invention keeps track of available elements in a list of elements available to a given device for processing from an index and count mechanism. Such an index and count mechanism provides an index that indicates a starting element in the list of elements that is available to the given device for processing. Such an index and count mechanism also provides a count that indicates a subsequent number of elements, from the starting element in the list of elements, that are available to the given device for processing. A first index register and a second index register alternately keep track of a last available element in the list of elements available to be processed by the given device until the last available element is a very last element in the list of elements.

Abstract: If consecutive read or write requests imposed on a DASD are of the same type and bear a defined sequential logical address relationship (pure sequential, near sequential), then a circular buffered data path using a pair of a synchronously managed read/write ports respectively coupling either a cyclic, concentric, multitracked storage medium or a cyclic, spiral-tracked storage medium and a device interface can continue data streaming unabated. Otherwise, the path would ordinarily have to be disabled and reconnected using a control microprocessor in respect of any random sequence of requests.

Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.

Abstract: A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.

Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.

Abstract: Each of a plurality of FIFO has (1) a low region indicating a minimum number of words for FIFO storage, (2) a burst count indicating the number of words involved in each transfer to such FIFO and (3) a high region where a word count transfer into the FIFO is not initiated. However, a burst count transfer initiated before the beginning of a FIFO high region may be completed in the FIFO high region. Each FIFO is initially filled from a memory by a memory controller to the low FIFO region. Upon word transfer from each FIFO, the memory controller establishes a priority to provide an additional burst count to the FIFO low region. When the memory controller is otherwise idle and the number of words in such FIFO is in a region intermediate the FIFO low and high regions, a burst count for each FIFO may be transferred into the intermediate FIFO region. The memory controller and each FIFO respectively remember the number of words transferred into and from such FIFO.

Abstract: In a method and apparatus for improving data integrity using a ring buffer, a ring buffer is formed by at least one of the memory areas of a non-volatile read-write memory being administered by a pointer counter such that a ring buffer that can be read out and written is produced in a non-volatile read-write memory. The ring buffer composed of a number of memory cells needed for conventional operation, expanded by one additional memory cell, and a cyclical pointer counter. The oldest dataset is overwritten in a write operation, and whereby the pointer counter is incremented after the new dataset was written into a memory cell in which the oldest dataset was previously located, so that the pointer of the aforementioned pointer counter now points to a memory cell having what is now an oldest dataset that can be overwritten in the next write operation.

Abstract: Disclosed is a computer system having a ring buffer arrangement which includes a plurality of sub-rings and a main ring. Each of the sub-rings includes a plurality of buffer memories and the main ring includes a plurality of the sub-rings. A main write pointer and a main read pointer are provided for the main ring in order to indicate a sub-ring for which data writing and data reading are currently being performed respectively. A sub-write pointer and a sub-read pointer are provided for each sub-ring in order to indicate, for the sub-ring, a buffer memory for which data writing and data reading are currently being executed respectively. Since the total size of the double ring buffer is large, not all of the buffer memories can be resident in physical memory. However, since the number of buffer memories included in a single sub-ring is relatively small, one sub-ring can be resident in the physical memory.

Abstract: A control unit (112) makes different judgments on the end address, depending on whether 1-word access or 2-word access, based on a post-update signal (507) and a 2-word access signal (508) which are internally generated and a coincidence signal (511) on the high-order 14 bits and another coincidence signal (512) on the bit 14 which are outputted from a comparator (158), and outputs a judgment result to a selector (155) as a selection signal (510). The selector (155) selects one of an output from an ALU (153) and an output from a latch (159) (the MOD.sub.-- S register 156) based on the selection signal (510). Having this structure, a data processor which enables access with modulo addressing in two different data-units can be provided.

Abstract: A buffer monitor includes a first counter for counting bits of incoming data as they arrive at a data buffer that stores and then forwards the incoming data. Each bit of outgoing data resets the first counter's count. If its count reaches a first limit before being reset by an outgoing data bit, the first counter asserts an alarm. The buffer monitor also includes a second counter for counting bits of outgoing data as they depart the buffer. Each bit of incoming data resets the second counter's count. If its count reaches a second limit level before being reset by an incoming data bit, the second counter asserts an alarm. The first counter will sound an alarm when the buffer fails to forward output data after having received a substantial amount of input data. The second counter will assert an alarm when the buffer has forwarded a substantial amount of output data without having received any input data.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: A portable radio telephone apparatus and including a first memory and a second memory for storing variable length records and validity confirmation indicators, indicating confirmed or unconfirmed validity, associated with each record, and memory defragmentation for identifying a first record in the first memory which is adjacent an available memory fragment; providing a second record in the second memory which is a duplicate of the first record having its validity confirmation indicator set to unconfirmed validity; setting the validity confirmation indicator of the second record to confirmed validity; setting the validity confirmation indicator of the first record to unconfirmed validity; providing a third record in the first memory at the location of said available memory fragment having its validity confirmation indicator set to unconfirmed validity; setting the validity confirmation indicator of the third record to confirmed validity; and setting the validity confirmation indicator of the second record to

Abstract: A space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory. The method and floor plan allow for a significant reduction in the physical area required for a buffer memory of any given size that is fabricated on integrated circuit. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage call be fabricated using much less chip area per bit than the first and third memory stages.

Abstract: A receiving buffer control system comprises a memory having a buffer area serving as a receiving buffer, data being applied to the memory via a bus, a write pointer indicating a write address of the buffer area, and a read pointer indicating a read address of the buffer area. An overrun/underrun detection circuit detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation.