Accessing Dynamic Storage Device Patents (Class 711/111)
  • Patent number: 12259812
    Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Brian Toronyi
  • Patent number: 12248702
    Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.
    Type: Grant
    Filed: January 7, 2023
    Date of Patent: March 11, 2025
    Assignee: SK hynix Inc.
    Inventors: Tae Ho Lim, Ie Ryung Park, Dong Sop Lee, Youn Won Park, Jae Min Jang
  • Patent number: 12248343
    Abstract: Aspects of the embodiments are directed to a rack server that includes a rack server chassis; a plurality of backplane printed circuit boards (PCBs) coupled to the rack server chassis, each backplane PCB comprising a plurality of cantilevered beams, each cantilevered beam of the plurality of cantilevered beams comprising a receiver slot to receive a server element; and a serial attached small computer serial interface (SAS) expander circuit element residing on each backplane PCB, the SAS expander circuit element electrically connected to the receiver slot of each cantilevered beam of the plurality of cantilevered beams. The rack server comprises a 5 RU height.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: March 11, 2025
    Assignee: Hyve Solutions Corporation
    Inventors: Jayarama Narayan Shenoy, Chiaming Liu, Chihwei Lee, John Will Wallerich, Robert Michael Kinstle, III, ChungTa Huang, Yung-Ning Mo, Chia-Yung Lin, Hsuanju Shen
  • Patent number: 12242853
    Abstract: A compute channel having a compute pipeline of compute stages can be configured using a configuration pipeline with a control table and a datapath table. The control table stores control entries corresponding to respective microoperations, and each control entry includes control information for the compute channel. A datapath table stores datapath configuration entries corresponding to respective microoperations, and each datapath configuration entry has a datapath configuration that includes computational circuit block configurations to configure respective computational circuit blocks in the compute pipeline of the compute channel. Control logic can issue a microoperation to the compute channel by configuring the compute channel according to the control information of the microoperation obtained from the control table, and by inputting the datapath configuration of the microoperation obtained from the datapath table into the configuration pipeline of the compute channel.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: March 4, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Paul Gilbert Meyer, Ron Diamant, Sundeep Amirineni
  • Patent number: 12231500
    Abstract: One example method includes performing, in a global environment that includes a central node and edge nodes that are able to communicate with each other, by the central node, operations including: sampling optimal information from the edge nodes concerning a state of the global environment, the edge nodes being grouped into a plurality of cluster structures based on the optimal information, updating a global map of the global environment, based on the optimal information, updating an information retrieval cost, using the state of the global environment to orchestrate placement and execution of one or more tasks and actions in the global environment, using the updated global map, information retrieval cost, tasks and actions to update an attention mechanism operable to control retrieval of next optimal information, and selecting next optimal information for retrieval.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: February 18, 2025
    Assignee: Dell Products L.P.
    Inventors: Werner Spolidoro Freund, Paulo Abelha Ferreira, Julia Drummond Noce
  • Patent number: 12216914
    Abstract: A memory system includes a memory device including a first memory block used for power-loss data protection and a controller coupled to the memory device. The controller includes a hardware layer and a firmware layer. The hardware layer checks whether at least one write data entry belongs to a programmable range in the memory device after power loss occurs, determines whether a logical address associated with the at least one write data entry is repeated, and programs the at least one write data entry in the first memory block.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: February 4, 2025
    Assignee: SK hynix Inc.
    Inventors: Jin Pyo Kim, Ju Hyun Kim, Jong Soon Park, Woong Sik Shin, Woo Young Yang
  • Patent number: 12216525
    Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: February 4, 2025
    Inventors: Luca Porzio, Alessandro Orlando, Danilo Caraccio, Roberto Izzi
  • Patent number: 12210476
    Abstract: A storage cluster with disaggregated compute resources and storage memory is provided. The storage cluster includes a plurality of blades coupled as the storage cluster, each of at least a subset of the plurality of blades having solid-state storage memory therein. The storage cluster includes a switch that direct network-connects a plurality of processors, as compute resources in the plurality of blades, and the solid-state storage memory in each of the at least a subset of the plurality of blades, wherein the compute resources and the solid-state storage memory are disaggregated in the storage cluster.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: January 28, 2025
    Assignee: PURE STORAGE, INC.
    Inventors: Yuhong Mao, Hari Kannan
  • Patent number: 12198755
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: January 14, 2025
    Assignee: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Takayuki Akamine
  • Patent number: 12197733
    Abstract: Systems, apparatuses, and methods related to memory system refresh management are described herein. In an example, a refresh operation can be performed on a set of memory cells in a memory device. The memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The refresh operation can include receiving a mode register write command. The refresh operation can include writing mode register data associated with the mode register write command. The refresh operation can be performed on the set of memory cells at an address location indicated by the written mode register data.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: January 14, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yang Lu, Kang-Yong Kim
  • Patent number: 12175073
    Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N?1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: December 24, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Varun Agrawal, Niti Madan
  • Patent number: 12164485
    Abstract: Techniques for optimizing project data storage are disclosed. An example system includes processors and memories communicatively coupled with the processors storing a trained machine learning (ML) model, a nesting data module, a project database, and instructions that cause the processors to: receive a first data category corresponding to a project, execute the trained ML model to determine a predicted data category mapping for the first data category, execute the nesting data module to: input the first data category into a first table having a first file size, collapse the first table with a second table that includes a second data category that is related to the first data category to generate a nested table, and store the nested table in the project database. The nested table has a file size that is less than a combined file size of the first table and the second table.
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: December 10, 2024
    Assignee: Northspyre, Inc.
    Inventors: William Sankey, Matthew Phinney
  • Patent number: 12153817
    Abstract: An apparatus includes at least one processing device configured to identify one or more logical storage devices each accessible in at least first and second storage systems, to detect one or more input-output (IO) operations associated with an offload application programming interface (API) of at least one of the first and second storage systems, to clone each such detected IO operation, and to send resulting respective first and second instances of each cloned IO operation to respective ones of the first and second storage systems. The first and second instances of each cloned IO operation are tagged prior to being sent to respective ones of the first and second storage systems so as to allow each of the first and second storage systems to separately determine that the other one of the first and second storage systems has been sent a corresponding instance of the cloned IO operation.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: November 26, 2024
    Assignee: Dell Products L.P.
    Inventors: Owen Crowley, Peniel Charles, Amit Pundalik Anchi
  • Patent number: 12153582
    Abstract: A database management system identifies a required column which is required for executing the query, reads out data of the identified required column from a storage device, and executes the query based on the data of the required column. When reading out the data of the required column, the database management system preferentially reads out the data of the required column from a high-speed storage device storing the data of the required column among a memory, a second storage, and a first storage, stores, in the memory, data of the second data size unit including the data of the required column used for executing the query, and, when the data of the required column is read out from the first storage, stores the data of the second data size unit in the memory and stores the read-out data of the first data size unit in the second storage.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: November 26, 2024
    Assignee: HITACHI, LTD.
    Inventors: Yoshiki Kurokawa, Satoru Watanabe, Norifumi Nishikawa, Kazuhiko Mogi
  • Patent number: 12147348
    Abstract: Operational information in a storage system is collected regarding storage media storage tiers, devices, drives, tracks on drives, and logical storage layers, to determine an estimated amount of time it will take to write data from cache to the intended drive when a new write operation arrives at the storage system. This information is then used to decide which type of cache is most optimal to store the data for the write operation, based on the estimated amount of time it will take to write data out from the cache. By allocating cache slots from a faster cache to write operations that are expected to quickly be written out to memory, and allocating cache slots from the slower cache to write operations that are expected to take more time to be written out to memory, it is possible to increase the availability of the cache slots in the faster cache.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: November 19, 2024
    Assignee: Dell Products, L.P.
    Inventor: John Creed
  • Patent number: 12056386
    Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: August 6, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Ying Gao, Boris Feigin, Hari Kannan, Igor Ostrovsky, Jeffrey Tofano
  • Patent number: 12056066
    Abstract: A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeongho Lee, Younho Jeon, Daehui Kim, Heehyun Nam
  • Patent number: 12046292
    Abstract: A method of using boot-time metadata in a storage system is provided. The method includes writing a fragmentation stride to a solid-state storage device of the storage system, the fragmentation stride defining a granularity on which fragmentation of erase blocks of the solid-state storage device occurs. The method includes allocating portions of erase blocks for at least one process in the storage system, in accordance with the fragmentation stride and writing boot up metadata at offsets that are based on the fragmentation stride, in the solid-state storage device.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: July 23, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Radek Aster, Andrew R. Bernat, Boris Feigin, Ronald Karr, Robert Lee
  • Patent number: 12039474
    Abstract: A method for selecting storage locations for storage of data. According to a placement policy, a file is stored in a database comprising a plurality of storage locations. The method includes determining a query for a copy comprising policy constraints in the placement policy and storage location constraints. The method includes extracting one or more data attributes of the file. The method includes determining an attribute set for each storage location including the data attributes and the storage location attributes for each storage location. The method includes identifying a set of one or more candidate storage locations for storage of the copy of the file by evaluating the attribute set for each storage location against the query. The method includes selecting a candidate storage location from the set and providing the copy of the file to the selected candidate storage location for storage.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 16, 2024
    Assignee: Uber Technologies, Inc.
    Inventors: Alexey Pavlenko, Jakob Holdgaard Thomsen, Dron Rathore
  • Patent number: 12032443
    Abstract: Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: July 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sandeep Krishna Thirumala, Lingming Yang, Amitava Majumdar, Nevil Gajera
  • Patent number: 12019521
    Abstract: Backing up logical data from a storage system to a backup system includes accessing data on the storage system corresponding to logical file structures of data stored on the storage system, using machine learning to ascertain file access patterns and frequency of file backups, determining backup data based on the logical file structure of data stored on the storage system and the file access patterns and frequency of file backups, and directly transferring data corresponding the backup data from the storage system to the backup system. The logical file structures may be provided by file metadata. The file metadata may include at least one of: a VTOC (volume table of contents), an IXVTOC (indexed VTOC), VSAM (virtual storage access method) information, a VVDS (VSAM volume data set), file attributes, and/or catalog data. The file attributes may include management class information for each of the files.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 25, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Brett A. Quinn
  • Patent number: 12020731
    Abstract: Provided is a system, method, and computer program product for minimizing high resolution tape directory (HRTD) recovery time when a HRTD is invalid. A tape drive may load a tape in the tape drive. In response to receiving a write command or a read command at a beginning of tape (BOT) position, the tape drive may execute the write command or the read command without performing HRTD recovery. In response to receiving the write command or the read command at a position other than the BOT position, the tape drive may determine if the HRTD is valid. In response to determining the HRTD is not valid, the tape drive may clear a timer.
    Type: Grant
    Filed: June 18, 2023
    Date of Patent: June 25, 2024
    Assignee: International Business Machines Corporation
    Inventors: Tsuyoshi Miyamura, Setsuko Masuda
  • Patent number: 11972148
    Abstract: Example storage systems, storage devices, and methods provide proactive management of storage operations using thermal states. Host storage requests are received and used to determine storage commands for a data storage device. For each storage command, a temperature index value corresponding to an estimated change in thermal state for executing the storage command may be determined. The storage commands are allocated to command queues based on the thermal index values and then executed from the command queues by the data storage device without triggering thermal throttling of storage commands.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11971857
    Abstract: A selected data chunk associated with an object is determined to be sent to a destination. A chunk compression grouping storing the selected data chunk associated with the object is identified. The identified chunk compression grouping includes a plurality of data chunks compressed together. A data content version that includes the selected data chunk associated with the object to be provided to the destination is determined from a plurality of data content versions based at least in part on a metric associated with the identified chunk compression grouping.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 30, 2024
    Assignee: Cohesity, Inc.
    Inventors: Zhihuan Qiu, Yinzen Hwang
  • Patent number: 11947461
    Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Naga P. Gorti, Guy L. Guthrie, Sanjeev Ghai
  • Patent number: 11934663
    Abstract: A client device includes at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other devices on a network each configured to provide a respective shared cache for the distributed cache. A Non-Volatile Memory express (NVMe) controller of the client device receives a command from a processor to access data in the shared cache and executes a program to use data read from the shared cache or data to be written to the shared cache to perform at least one computational operation. In another aspect, data is accessed in the shared cache using a kernel and data read from the shared cache or data to be written to the shared cache is used to perform at least one computational operation by the kernel.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Marjan Radi
  • Patent number: 11914883
    Abstract: A copy operation is received. The copy operation is of one or more files stored on a linear tape file system. The copy operation is performed in a plurality of units of extents of the one or more files.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: February 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Shinsuke Mitsuma, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Noriko Yamamoto, Atsushi Abe
  • Patent number: 11914558
    Abstract: Systems and methods are provided in order to avoid ingesting the entire contents of one or more data sources. An object may be associated with one or more pieces/fragments of data that can be stored in different data sources. When a request for the object is initiated, a search for those pieces/fragments of data can be performed. Nodes associated with each data source may generate data queries appropriate for its corresponding data source, retrieve, and if needed transform the data into an object-based data structure. Any pieces/fragments of data that have been discovered and retrieved can be joined, e.g., by an application programming interface server, and forwarded to a requesting client or application. In this way, only data relevant to the object is obtained. Moreover, object versioning can be employed so that the most up-to-date data is obtained.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 27, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: Peter Wilczynski, Alexander Ryan, Allen Chang, Daniel Cervelli, Julie Tibshirani, Timothy Wilson
  • Patent number: 11909807
    Abstract: In embodiments of the present invention, a processor executing a web browser detects a first request including a Hypertext Transfer Protocol (HTTP) request conveyed by the web browser to a first server for a web page including browser-executable code for a web-based application, and a response received from the first server including the requested browser-executable code, wherein the first HTTP request includes a first Uniform Resource Locator (URL). In the browser-executable code, a second request to a second server for a web resource and including a second URL is identified, and the second URL in the browser-executable code is modified so as to reference a third server. The first URL is modified so as to reference a fourth server, and the modified browser-executable code is stored on the fourth server so as to be referenced by the modified first URL.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 20, 2024
    Assignee: DEMOSTACK, INC.
    Inventors: Gonen Tiberg, Aaron Bar Hakim, Ben Sterenson, Rotem Maya Dantess, Gilad Avidan, Yehonatan Ernest Friedman
  • Patent number: 11886724
    Abstract: A computer-implemented method according to one approach includes copying data stored on a Linear Tape File System (LTFS)-based storage system to blocks of a Random Access Nonvolatile Memory (RANVM) drive. The data is copied in units of the blocks of the drive. The method further includes constructing file metadata so that the copied data on the drive is accessible as one or more files. A computer program product according to another approach includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a controller to cause the controller to perform the foregoing method. A system according to another approach includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to perform the foregoing method.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Shinsuke Mitsuma, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Noriko Yamamoto, Sosuke Matsui, Atsushi Abe
  • Patent number: 11809731
    Abstract: A tool for tape library hierarchical storage management. The tool mounts a tape cartridge to a tape drive to satisfy a recall request. The tool determines there is available tape capacity on the tape cartridge to migrate data from a migration queue during recall operations. The tool sends a locate end of data (EOD) command to the tape drive. The tool receives a longitudinal position (LPOS) range returned from the tape drive. The tool determines the migration queue is within the LPOS range. The tool writes data from the migration queue to the tape cartridge within the LPOS range.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Noriko Yamamoto, Hiroshi Itagaki, Tsuyoshi Miyamura, Tohru Hasegawa, Shinsuke Mitsuma, Atsushi Abe
  • Patent number: 11789880
    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: October 17, 2023
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Emily P. Chung, Frank T. Hady, George Vergis
  • Patent number: 11768637
    Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel. The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: September 26, 2023
    Inventors: Kihwan Seong, Donguk Park
  • Patent number: 11762795
    Abstract: The methods and systems may provide a scalable round-robin arbiter tree that performs round-robin arbitration for a plurality of requests received from a set of requestors. The round-robin arbiter may stack a plurality of round-robin cells in stages where an output of a first stage of round-robin cells is an input to a next stage of round-robin cells. The round-robin arbiter may transform an arbitration state at each stage of the arbitration and propagate the arbitration state into the next stage for arbitration. The arbitration state from the final stage round-robin cell is fed back to the first stage of the round-robin cells and used in a subsequent arbitration round.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 19, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Shu-Yi Yu, Nicolas Mellis
  • Patent number: 11748201
    Abstract: A versioned file system comprises a set of structured data representations. At a first time, an interface creates and exports to a cloud data store a first structured data representation corresponding to a first version of the local file system. The first structured data representation is an XML tree having a root element, one or more directory elements associated with the root element, and one or more file elements associated with a given directory element. Upon a change within the file system, the interface creates and exports a second structured data representation corresponding to a second version of the file system. The second structured data representation differs from the first structured data representation up to and including the root element of the second structured data representation. The interface continues to generate and export the structured data representations to the data store.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: September 5, 2023
    Assignee: Nasuni Corporation
    Inventors: Robert S. Mason, Jr., Andres Rodriguez
  • Patent number: 11688431
    Abstract: In one aspect of tape repositioning management in accordance with the present description, in response to loading a tape in a tape drive, mounting the tape linear tape file system (LTFS) is initiated including reading an index partition on the tape to extract metadata for mounting the tape LTFS, and prior to accessing a data area of the tape in response to any application access request, the tape is repositioned within a data partition to read a vHRTD (virtual High Resolution Tape Directory) recorded in an EOD (End of Data) portion such as an EOD data set, for example, of the data partition. The EOD portion is read to retrieve the vHRTD to facilitate application requested accesses to the tape. In one embodiment, repositioning and stopping the tape at the beginning of the data partition after reading the index partition containing metadata is bypassed.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: June 27, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tsuyoshi Miyamura, Atsushi Abe, Setsuko Masuda
  • Patent number: 11687240
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for data compression. The method includes: comparing the size of a first data packet to be compressed with a first threshold size; if the size of the first data packet is greater than the first threshold size, determining at least two second data packets from the first data packet, wherein the size of each second data packet is less than a second threshold size; and respectively compressing the at least two second data packets. In this way, the delay of data compression can be shortened.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: June 27, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Tao Chen, Geng Han, Bing Liu
  • Patent number: 11681626
    Abstract: A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: June 20, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Shiho Nakahara, Takahide Yoshikawa
  • Patent number: 11675509
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to open a first block family associated with the memory device; assign a first cursor of a plurality of cursors of the memory device to the first block family; responsive to programming a first block associated with the first cursor, associate the first block with the first block family; open, while the first block family is open, a second block family associated with the memory device; assign a second cursor of the plurality of cursors of the memory device to the second block family; and responsive to programming a second block associated with the second cursor, associate the second block with the second block family.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shane Nowell, Michael Sheperek, Larry J Koudele, Bruce A Liikanen, Steve Kientz
  • Patent number: 11650746
    Abstract: Systems, methods and apparatus of intelligent write-amplification reduction for data storage devices configured on autonomous vehicles. For example, a data storage device of a vehicle includes: one or more storage media components; a controller configured to store data into and retrieve data from the one or more storage media components according to commands received in the data storage device; an address map configured to map between: logical addresses specified in the commands received in the data storage device, and physical addresses of memory cells in the one or more storage media components; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized data placement scheme. The controller is configured to adjust the address map according to the optimized data placement scheme.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Robert Richard Noel Bielby
  • Patent number: 11644998
    Abstract: A method for managing distributed storage implemented in a server includes obtaining files to be stored from a user; performing processing for distribution on the files to be stored; determine a storage requirement of the files to be stored, wherein the storage requirement can comprise file storage and object storage; storing the distributed files into a plurality of storage areas through a distributed storage unit when the storage requirement of the files to be stored is determined to be the file storage; and storing the distributed files into the plurality of storage areas through a distributed storage unit and an object storage unit when the storage requirement of the files to be stored is determined to be the file storage.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 9, 2023
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chia-Chun Wu
  • Patent number: 11621019
    Abstract: A system may include one or more tape drives. A front portion of the one or more tape drives may be exposed to allow access to one or more respective tape cartridges of each of the one or more tape drives. The system may include one or more servers. The one or more servers may control the one or more tape drives. The system may include one or more ports communicatively connected to the one or more tape drives. Each of the one or more ports may respectively be associated with a specific sensor. Each of the specific sensors may record a specific datum. The system my include one or more power supplies.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: David Harper, Gregory Goodman
  • Patent number: 11614880
    Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 28, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ying Gao, Boris Feigin, Hari Kannan, Igor Ostrovsky, Jeffrey Tofano
  • Patent number: 11604697
    Abstract: Systems, methods, and circuitries are provided for supporting distributed erasure coding in a shared file system. In one example, a method is provided to be performed by an initiator device configured to read and write data in files stored in a plurality of storage nodes that are controlled by a file management system. The method includes generating a stripe by identifying data to be stored in a storage system; dividing the data into K data segments; and performing an erasure encoding operation on the K data segments to generate a parity segment, wherein the stripe includes the K data segments and the parity segment. The method includes requesting, from the file management system, respective memory allocations in the storage devices for storing respective segments of the stripe; and transmitting, to each of the plurality of storage nodes, a respective instruction to store a respective data or parity segment in the memory allocation on the respective storage device.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 14, 2023
    Assignee: Quantum Corporation
    Inventor: Ben Jarvis
  • Patent number: 11580036
    Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: February 14, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ilan Pardo, Shahaf Shuler, George Elias, Nizan Atias, Adi Maymon
  • Patent number: 11573723
    Abstract: A method of managing extents of a file system having a protection pool includes collecting and initializing physical extent manager (PEM) metadata, using a PEM daemon thread. The PEM is configured to run on each of a number of nodes. The method also includes creating a request queue, using the PEM daemon thread, for all requests submitted to the PEM. The method also includes scanning the request queue, using a PEM worker thread, to handle incoming requests submitted to the PEM. The method also includes listening for multicast messages, using a PEM multicast listener thread, to be handled by the PEM worker thread.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 7, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Paul Nehse, Michael Thiels, Devendra Kulkarni
  • Patent number: 11573864
    Abstract: Automatically managing database applications, including identifying, by a management extension, an SQL server host connected to a storage system, wherein the SQL server host comprises an SQL server managing an SQL database supported by the storage system; identifying, by the management extension, the SQL database supported by the storage system based on the identified SQL server host; and scheduling, by the management extension, a backup of the SQL database.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 7, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Ahmed Azmy Hassan, Hesham Anan, Daniele Braga Pecanha, Aoxi Yao, Robert Barker, Jr.
  • Patent number: 11561695
    Abstract: In a storage system such as a SAN, NAS, or storage array that implements hierarchical performance tiers based rated drive access latency, on-drive compression is used on data stored on a first tier and off-drive compression is used on data stored on a second tier. Off-drive compression is more processor intensive and may introduce some data access latency but reduces storage requirements. On-drive compression is performed at or near line speed but generally yields lower size reduction ratios than off-drive compression. On-drive compression may be implemented at a higher performance tier whereas off-drive compression may be implemented at a lower performance tier. Further, space saving realized from on-drive compression may be applied to over-provisioning.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 24, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: James M Guyer
  • Patent number: 11561703
    Abstract: In an approach to adaptive tape calibration criteria based on the number of dead tracks, the number of rewrite occurrences for each dead track on a tape drive is determined. Responsive to detecting that a head is in a dead track state, the number of dead tracks is stored on the tape drive. A calibration threshold is determined, where the calibration threshold includes the number of dead track rewrites and the calibration reference value for a specific tape drive type. Responsive to the number of rewrite occurrences exceeding the calibration threshold while writing a data set, a calibration of the tape drive.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Tsuyoshi Miyamura, Keisuke Tanaka, Ernest Stewart Gale
  • Patent number: 11514057
    Abstract: A method of implementing object tagging framework starts with the processor receiving a tag creation command including a tag name. In response to the tag creation command, the processor creates a current tag. The processor then receives an association command, the tag name and a source object identifier. The processor determines a source object associated with the source object identifier. The source object includes a tag value. The processor associates the current tag with the source object. The processor receives a replication command including the source object and a target object. The processor causes replication of the source object to the target object that comprises replicating the current tag with the tag name and the tag value in the source object to the target object. Other embodiments are also described herein.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: November 29, 2022
    Assignee: Snowflake Inc.
    Inventors: Artin Avanes, Khalid Zaman Bijon, Yujie Li, Zheng Mi, Subramanian Muralidhar, David Schultz