Caching Patents (Class 711/113)
  • Patent number: 12067276
    Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 20, 2024
    Inventors: Frank F. Ross, Matthew A. Prather
  • Patent number: 12061791
    Abstract: A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory and a controller. The controller is configured to determine if a retrim is needed for the data storage device. In accordance with a determination that the retrim is needed, the controller is configured to identify a time to initiate a new trim on the data storage device, and cause the new trim on the data storage device at the time identified.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: August 13, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Eran Erez, Joseph R. Meza, Dylan B. Fairchild
  • Patent number: 12056055
    Abstract: A data processing device and related products are provided. The data processing device includes: a decoding unit, a discrete address determining unit, a continuous data caching unit, a data read/write unit, and a storage unit. Through the data processing device, the processing instruction may be decoded and executed, and the discrete data may be transferred to a continuous data address, or the continuous data may be stored to a plurality of discrete data addresses. As such, a vector computation of the discrete data and vector data restoration after the vector computation may be implemented, which may simplify a processing process, thereby reducing data overheads. In addition, according to the embodiments of the disclosure, when the discrete data is read, by caching a storage address corresponding to a read request, a read request of each piece of data may be merged to read one or more pieces of discrete data, thereby improving reading efficiency of the data.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: August 6, 2024
    Assignee: ANHUI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xuyan Ma, Jianhua Wu, Shaoli Liu, Xiangxuan Ge, Hanbo Liu, Lei Zhang
  • Patent number: 12045168
    Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 12032825
    Abstract: A computer-implemented method for altering a current position in a Data Partition of a tape at which the tape transitions to a DATA_FULL state is disclosed. The computer-implemented method includes determining a size of a last Index appended to the Data Partition of the tape. The computer-implemented method further includes altering, based on the size of the last Index appended to the Data Partition of the tape, the current position in the Data Partition of the tape at which the tape transitions to DATA_FULL state to a new position in the DATA Partition of the tape at which the tape transitions to the DATA_FULL state, wherein the DATA_FULL state is a state on the tape in which only metadata write operations are permitted in the Data Partition.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: July 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Atsushi Abe, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Noriko Yamamoto, Shinsuke Mitsuma, Sosuke Matsui
  • Patent number: 12019554
    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: June 25, 2024
    Assignee: VMware LLC
    Inventors: Irina Calciu, Andreas Nowatzyk, Isam Wadih Akkawi, Venkata Subhash Reddy Peddamallu, Pratap Subrahmanyam
  • Patent number: 12001503
    Abstract: A server receives a first hypertext transfer protocol (HTTP) from a client device requesting for content associated with a webpage. The server retrieves a plurality of cache keys associated with respective sets of application metadata identified in the first HTTP request from an application metadata database and transmits the cache keys to the client device. The server receives a second HTTP request from the client device identifying one or more cache keys that are not stored in a local HTTP cache of the client device. The server device retrieves the sets of application metadata corresponding to the missing cache keys from the application metadata database and transmits the application metadata to the client device.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: June 4, 2024
    Assignee: ServiceNow, Inc.
    Inventors: Kapeel Sharadrao Sable, Carl Solis, Bojan Beran, Kyle James Barron-Kraus
  • Patent number: 11989126
    Abstract: Systems, methods, and computer readable media for tracking memory deltas at a cache line granularity. The method includes receiving a base address for a physical memory region, receiving a list of empty log memory buffers associated with a delta logging session, and responsive to determining that a cache line associated with the physical memory region may be in a modified state, storing the modified cache line and metadata associated with the modified cache line in an active log memory buffer referenced by the list of empty log memory buffers. The method also includes determining that the active log memory buffer is full and appending a flag to the active log memory buffer, thereby marking the active log memory buffer as a full log memory buffer. The method also includes storing a list of full log memory buffers, wherein the list is visible to a host processor.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventor: David Boles
  • Patent number: 11983421
    Abstract: In some examples, a system causes execution, in each respective storage node of a cluster of storage nodes, of a respective frontend service that provides a frontend to a client over a network for access by the client of a storage volume accessible by the cluster of storage nodes. The system obtains node-specific configuration data portions from a configuration data repository, the node-specific configuration data portions being for respective storage nodes of the cluster of storage nodes, and sends the node-specific configuration data portions to the respective frontend services for configuring the frontend services.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: May 14, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Xiaokang Sang, Tao Jin
  • Patent number: 11947489
    Abstract: A new snapshot of a storage volume is created by instructing computing nodes to suppress write requests. Once pending write requests from the computing nodes are completed, storage nodes create a new snapshot for the storage volume by allocating a new segment to the new snapshot and finalizes and performs garbage collection with respect to segments allocated to the previous snapshot. Subsequent write requests to the storage volume are then performed on the segments allocated to the new snapshot. A segment maps segments to a particular snapshot and metadata stored in the segment indicates storage volume addresses of data written to the segment. The snapshots may be represented by a storage manager in a hierarchy that identifies an ordering of snapshots and branches to clone snapshots.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 2, 2024
    Assignee: Robin Systems, Inc.
    Inventors: Dhanashankar Venkatesan, Partha Sarathi Seetala, Gurmeet Singh
  • Patent number: 11940876
    Abstract: A method includes identifying traits associated with a number of storage units of a storage network to produce identified traits. The method further includes determining a plurality of sets of storage pool traits based on the identified traits, where a first set of storage pool traits of the plurality of sets of storage pool traits has a common trait of the identified traits. The method further includes selecting a plurality of groups of storage units from the number of storage units based on the plurality of sets of storage pool traits. The method further includes selecting a storage unit from each of the plurality of groups of storage units in accordance with a selection approach to produce a storage set of selected storage units. The method further includes utilizing the storage set of selected storage units for storing data in the storage network.
    Type: Grant
    Filed: April 30, 2023
    Date of Patent: March 26, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Teague S. Algie, Jason K. Resch
  • Patent number: 11893280
    Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jason Duong, Fangfang Zhu, Jiangli Zhu, Juane Li, Chih-Kuo Kao
  • Patent number: 11861175
    Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Radu Ioan Stoica, Aaron Daniel Fry, Nikolas Ioannou, Nikolaos Papandreou, Roman Alexander Pletka, Charalampos Pozidis, Jenny L Brown
  • Patent number: 11863810
    Abstract: A method for media content streaming includes: determining, from a plurality of media content items, multiple predicted media content items and multiple playback positions, based on history data of a user; transcoding a portion of each of the multiple predicted media content items to generate multiple passive adaptive streamlets for each of the multiple predicted media content items at different bitrates; receiving a command to start playback of a first predicted media content item selected from the multiple predicted media content items; outputting a first passive adaptive streamlet selected from the multiple passive adaptive streamlets of the first predicted media content item; while outputting the first passive adaptive streamlet, requesting, receiving, and transcoding a second portion of the first predicted media content item to generate an active adaptive streamlet of the first predicted media content item; immediately following outputting the first passive adaptive streamlet, outputting the active adapt
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 2, 2024
    Assignee: DISH Network Technologies India Private Limited
    Inventors: Deepak Sharma, Vimalraj Ganesan
  • Patent number: 11816203
    Abstract: An anti-malware system monitors the emulation of a suspicious program in a sandbox environment. The anti-malware system determines that the suspicious program is attempting to access a restricted area of memory (e.g., an executable instruction in the restricted area). Rather than stop the emulation, the anti-malware system can temporarily pause the emulation of the suspicious program. During this pause, the anti-malware system can determine whether the suspicious program is containable within the sandbox environment. If the anti-malware system determines that the emulation of the executable instruction is safe (e.g., that the program is containable), the anti-malware system will resume emulation. If the anti-malware system determines that the emulation of the executable instruction is not safe, the anti-malware system may shut down emulation.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: November 14, 2023
    Assignee: Malwarebytes Inc.
    Inventors: Jason Neal Raber, Mickael Roger
  • Patent number: 11803468
    Abstract: A data storage system can have one or more hosts connected to a data storage subsystem with the host having a host processor and the data storage subsystem having a controller. Write back data generated at the host triggers the host processor to allocate a cache location in the data storage subsystem where the generated data is subsequently stored. The generated write back data is written in a non-volatile destination address as directed by the controller prior to waiting for a secondary event with the generated data stored in both the cache location and the non-volatile destination address. Detection of the secondary event prompts the controller to signal the host processor that the cache location is free for new data.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 31, 2023
    Assignee: Seagate Technology LLC
    Inventors: Phillip R. Colline, Michael Barrell, Richard O. Weiss, Mohamad H. El-Batal
  • Patent number: 11740816
    Abstract: A data storage node includes a plurality of compute nodes that allocate portions of local memory to a shared cache. The shared cache is configured with mirrored and non- mirrored segments that are sized as a function of the percentage of write IOs and read IOs in a historical traffic workload profile specific to an organization or storage node. The mirrored and non-mirrored segments are separately configured with pools of data slots. Within each segment, each pool is associated with same-size data slots that differ in size relative to the data slots of other pools. The sizes of the pools in the mirrored segment are set based on write IO size distribution in the historical traffic workload profile. The sizes of the pools in the non-mirrored segment are set based on read IO size distribution in the historical traffic workload profile.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: August 29, 2023
    Assignee: Dell Products L.P.
    Inventors: Ramesh Doddaiah, Malak Alshawabkeh, Kaustubh Sahasrabudhe
  • Patent number: 11716406
    Abstract: Methods and systems for caching data for resources using a shared cache are described herein. The data may be stored in a configuration service, in the resources, or in the shared cache. The data stored in the configuration service may be modified. The data stored in the resources and in the shared cache may be updated according to the modified data in the configuration service. The data stored in the configuration service, in the resources, or in the shared cache may be used based on an operation mode.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: August 1, 2023
    Assignee: Citrix Systems, Inc.
    Inventors: Feng Huang, Duncan Spencer Gabriel, Simon Frost, Ross Large
  • Patent number: 11681437
    Abstract: A computer-implemented method for altering a position on a tape at which the tape transitions to a DATA_FULL state is disclosed. The computer-implemented method further includes determining, after a file is written to a Data Partition of the tape, a size of an Index representing metadata associated with the file. The computer-implemented method further includes altering, based on the size of the Index representing metadata associated with the file, a position in the Data Partition of the tape at which the tape transitions to the DATA_FULL state.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Atsushi Abe, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Noriko Yamamoto, Shinsuke Mitsuma, Sosuke Matsui
  • Patent number: 11645409
    Abstract: A method for distributed and private symmetric searchable encryption includes receiving encrypted data, creating a search index for one or more servers based on the encrypted data using a distributed point function (DPF), splitting the encrypted data into a number of portions based on the number of servers, and partitioning the servers into two or more groups. The method also includes updating the search index based on the splitting and the partitioning, transmitting the split encrypted data to the servers based on the updated search index, verifying the transmitted data using data not transmitted to the server, and determining, based on the verifying, whether any server deviated from an assigned protocol.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 9, 2023
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Vipin Singh Sehrawat
  • Patent number: 11635902
    Abstract: A storage device which is connected to a host using a virtual memory includes a solid state drive that receives a streaming access command including a logical block address (LBA) list and a chunk size, and prefetches stream data requested according to the LBA list and the chunk size from a nonvolatile memory device without an additional command. The prefetched stream data is sequentially loaded onto a buffer, and an in-storage computing block accesses a streaming region registered on the virtual memory to sequentially read the stream data loaded onto the buffer in units of the chunk size. The buffer is mapped onto a virtual memory address of the streaming region.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duckho Bae, Dong-Uk Kim, Jaehong Min, Yong In Lee, Jooyoung Hwang
  • Patent number: 11586545
    Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: February 21, 2023
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Andreas Nowatzyk, Isam Wadih Akkawi, Venkata Subhash Reddy Peddamallu, Pratap Subrahmanyam
  • Patent number: 11567867
    Abstract: A controller controls a memory device. The controller includes a buffer buffering one or more data chunks received from a host until the one or more data chunk is stored in the memory device, and a processor sorting and storing, according to data types of the one or more data chunks, the one or more data chunks buffered in the buffer in a plurality of memory regions of the memory device in a normal operation, the plurality of memory regions respectively corresponding to a plurality of data types. In response to a sudden power-off (SPO), the processor generates map data indicating a relationship between the one or more data chunks and the plurality of memory regions, generates a data string by merging the one or more data chunks, and stores the data string and the map data in a temporal memory region of the memory device.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Hungyung Cho
  • Patent number: 11556464
    Abstract: A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngmoon Kim, Dong-Min Kim, Jeong-Woo Park
  • Patent number: 11539669
    Abstract: Systems and methods for providing policy-controlled communication over the Internet are provided. A system may include a client endpoint function configured to execute on a client device while coupled to a first VPN tunnel, a service endpoint function that operates a remote service of a plurality of remote services, and a mid-link server coupled to the first VPN tunnel and a second VPN tunnel. The mid-link server may include an inspection component that analyzes network packet traffic in accordance with a plurality of policies. The inspection component may inspect the network packet traffic for specific content and provide instructions to a router component and/or a mediation component of the mid-link server. The instructions may be a function of at least one policy that applies to the specific content.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 27, 2022
    Assignee: Netskope, Inc.
    Inventors: Victor Ronin, David Goldschlag, Vadim Tarnavsky, Kevin Eugene Sapp
  • Patent number: 11526303
    Abstract: A multi-tiered data storage system for building management system (BMS) data includes a plurality of data stores including a first data store and a second data store. The system further includes a data access router configured to provide a consistent endpoint for the BMS data to an application that provides or consumes the BMS data regardless of whether the BMS data is stored in the second data store or the first data store, obtain a requested data object of the BMS data from the second data store in response to a determination that the requested data object is available in the second data store, and obtain the requested data object from the first data store in response to a determination that the requested data object is not available in the second data store.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 13, 2022
    Assignee: Johnson Controls Tyco IP Holdings LLP
    Inventors: Carol T. Tumey, Michael F. Jaeger
  • Patent number: 11520488
    Abstract: A consistency group is defined to include a set of required devices on a set of storage systems. Write patterns on each of the required devices are monitored and write patterns on each of the other devices on the set of storage systems is monitored. Pairs of devices are formed, in which each pair includes one required device and one other device. Write patterns of the pairs of devices are compared to determine respective percentage coordinated write probabilities for pairs of devices. Write patterns of the pairs of devices are also compared to determine ratios of write operations for pairs of devices. A coordinate write probability above a threshold, or a determined ratio of write operations that occurs sufficiently frequently, is interpreted as an indication that one of the other devices should be included in the consistency group. A learning process is trained and used to analyze the write patterns.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 6, 2022
    Assignee: Dell Products, L.P.
    Inventors: Peter Callewaert, Dennis Trulli, Jr.
  • Patent number: 11520702
    Abstract: The present invention discloses a method and a system for managing cache memory. The system comprising a processor is configured to receive datasets from one or more applications, segregate the received datasets into one or more data blocks, identify a checkpoint from previously created checkpoints stored in a virtual cache corresponding to the one or more data blocks, wherein the checkpoints are previously created based on frequency of repetition of each of the one or more data blocks and association between the each of the one or more data blocks, recall a sequence of previously stored data blocks from main memory based on the identified checkpoint, and send the sequence of previously stored data blocks to the one or more applications for execution, thereby managing cache memory.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 6, 2022
    Assignee: Wipro Limited
    Inventors: Rishav Das, Sourav Mudi
  • Patent number: 11513708
    Abstract: Disclosed deduplication techniques at a distributed data storage system guarantee that space reclamation will not affect deduplicated data integrity even without perfect synchronization between components. By understanding certain “behavioral” characteristics and schedule cadences of backup operations that generate backup copies received at the distributed data storage system, data blocks that are not re-written by subsequent backup copies are pro-actively aged, while promoting continued retention of data blocks that are re-written. An expiry scheme operates with block-level granularity. Each unique deduplicated data block is given an expiry timeframe based on the block's arrival time at the distributed data storage system (i.e., when a backup copy supplies the block) and further based on backup frequencies of the various virtual disks referencing a unique system-wide identifier of the block, which is based on the block's hash value. Communications between components are kept to an as-needed basis.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 29, 2022
    Assignee: Commvault Systems, Inc.
    Inventors: Bharat Pundalik Naik, Xiangyu Wang, Avinash Lakshman
  • Patent number: 11513691
    Abstract: Systems and methods are disclosed for providing parallel data transfer. In certain embodiments, a data storage device includes a non-volatile memory and a controller configured to: receive a command from a host to obtain a file stored in the non-volatile memory; determine a plurality of channels available between the host and the data storage device; dynamically divide the file into a plurality of chunks based at least in part on the plurality of channels; perform load balancing to determine a first chunk of the plurality of chunks to be sent over a first channel of the plurality of channels and at least a second chunk of the plurality of chunks to be sent over a second channel of the plurality of channels; and simultaneously transmit the first chunk over the first channel and the second chunk over the second channel.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niraj Srimal, Adarsh Sreedhar, Rakshit Tikoo, Aditya Gadgil
  • Patent number: 11513738
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to embodiments of the present disclosure, a memory system may determine whether the memory system is in a read-intensive state; when determined that the memory system is in the read-intensive state, process a write request received from a host using at least one first type memory block among the plurality of memory blocks, and migrate data stored in a second type memory block to the at least one first type memory block; and set a number of bits that can be stored in a memory cell included in the first type memory block to be less than a number of bits that can be stored in a memory cell included in the second type memory block.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyeong Ju Na
  • Patent number: 11500566
    Abstract: Disclosed deduplication techniques at a distributed data storage system guarantee that space reclamation will not affect deduplicated data integrity even without perfect synchronization between components. By understanding certain “behavioral” characteristics and schedule cadences of backup operations that generate backup copies received at the distributed data storage system, data blocks that are not re-written by subsequent backup copies are pro-actively aged, while promoting continued retention of data blocks that are re-written. An expiry scheme operates with block-level granularity. Each unique deduplicated data block is given an expiry timeframe based on the block's arrival time at the distributed data storage system (i.e., when a backup copy supplies the block) and further based on backup frequencies of the various virtual disks referencing a unique system-wide identifier of the block, which is based on the block's hash value. Communications between components are kept to an as-needed basis.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 15, 2022
    Assignee: Commvault Systems, Inc.
    Inventors: Bharat Pundalik Naik, Xiangyu Wang, Avinash Lakshman
  • Patent number: 11500560
    Abstract: One example method includes defining a configuration of SCM, receiving a stream of IOs from a client, analyzing the stream of IOs and, based on the analyzing, estimating future IO behavior of the client, and based on estimated future IO behavior of the client, reconfiguring one or more parameters of the configuration of the SCM to define an updated configuration of the SCM, and the updated configuration of the SCM enables an improvement in IO performance relative to an IO performance of the configuration of the SCM.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: November 15, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Parmeshwr Prasad, Rahul Deo Vishwakarma
  • Patent number: 11500583
    Abstract: A storage device including: a nonvolatile memory device including a first, second and third area; and a controller to receive a first write command including a first logical block address from a host, to receive first data corresponding to the first logical block address in response to the first write command, and store the first data in the nonvolatile memory device, when the first write command includes area information, the controller stores the first data in the first area or the second area based on the area information, when the first write command does not include the area information, the controller stores the first data in the third area, each of the first area and the second area includes memory cells each storing “n” bits (n being a positive integer), and the third area includes memory cells each storing “m” bits (m being a positive integer greater than n).
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsoo Cho, Dong-Min Kim, Kyoung Back Lee
  • Patent number: 11487666
    Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11467833
    Abstract: A processor having an instruction set including a load-store instruction having operands specifying, from amongst the registers in at least one register file, a respective destination of each of two load operations, a respective source of a store operation, and a pair of address registers arranged to hold three memory addresses, the three memory addresses being a respective load address for each of the two load operations and a respective store address for the store operation. The load-store instruction further includes three stride operands each specifying a respective stride value for each of the two load addresses and one store address, wherein at least some possible values of each stride operand specify the respective stride value by specifying one of a plurality of fields within a stride register in one of the one or more register files, each field holding a different stride value.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 11, 2022
    Assignee: Graphcore Limited
    Inventors: Alan Graham Alexander, Simon Christian Knowles, Mrudula Chidambar Gore
  • Patent number: 11467904
    Abstract: A storage system including a storage controller and a plurality of storage drives generates parity data from data. Data and parity data configure a stripe. A plurality of stripes configure a parity group allocated with a plurality of storage drives to store the parity group. A first parity group allows the number of storage drives allocated to the parity group to be equal to the number of data pieces configuring each stripe. A second parity group allows the number of storage drives allocated to the parity group to be larger than the number of data pieces configuring each stripe and allows data for each stripe to be distributed and stored in different combinations of storage drives. When the first parity group is converted to the second parity group, a storage drive is added so that it is allocated to the parity group. Data is moved to ensure a free area.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 11, 2022
    Assignee: HITACHI, LTD.
    Inventors: Takeru Chiba, Hiroki Fujii, Yoshiaki Deguchi
  • Patent number: 11449422
    Abstract: There are provided a memory controller for managing meta data and an operating method of the memory controller. The memory controller includes: a buffer memory for storing meta data used to control an operation of a memory device; and a central processing unit for updating the meta data stored in the buffer memory whenever the operation of the memory device is controlled. The central processing unit may transmit the meta data stored in the buffer memory to a host at a first frequency, and transmit the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Seok Jun Lee
  • Patent number: 11442865
    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: September 13, 2022
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Andreas Nowatzyk, Isam Wadih Akkawi, Venkata Subhash Reddy Peddamallu, Pratap Subrahmanyam
  • Patent number: 11438432
    Abstract: A machine-implemented method for controlling transfer of at least one data item from a data cache component, in communication with storage using at least one relatively higher-latency path and at least one relatively lower-latency path, comprises: receiving metadata defining at least a first characteristic of data selected for inspection; responsive to the metadata, seeking a match between said at least first characteristic and a second characteristic of at least one of a plurality of data items in the data cache component; selecting said at least one of the plurality of data items where the at least one of the plurality of data items has the second characteristic matching the first characteristic; and passing the selected one of the plurality of data items from the data cache component using the relatively lower-latency path.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: September 6, 2022
    Assignee: METASWITCH NETWORKS LTD
    Inventors: Jim Wilkinson, Jonathan Lawn
  • Patent number: 11429530
    Abstract: A data storage device may include: a nonvolatile memory configured to store L2P (Logical to Physical) map data and user data; and a controller configured to determine whether read commands which are sequentially transferred from a host device correspond to a backward sequential read, increase a backward sequential read count when the read commands are backward sequential read, set a pre-read start logical block address (LBA) and a length according to a preset condition, when the backward sequential read count is equal to or greater than a reference value, and load an L2P map of the corresponding LBA and user data corresponding to the L2P map from the nonvolatile memory in advance.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventor: Seok Jun Lee
  • Patent number: 11422728
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage devices, for data processing and storage. One of the methods includes maintaining, by a storage system, a data log file in a source storage device of the storage system. The storage system identifies one or more characteristics of the data log file and one or more characteristics of the source storage device, and determines a migration metric of the data log file based on the one or more characteristics of the data log file and the one or more characteristics of the source storage device. The storage system determines whether to migrate the data log file according to the migration metric. In response to determining to migrate the data log file, the storage system migrates the data log file from a source location in the source storage device to a destination storage device.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 23, 2022
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Shikun Tian
  • Patent number: 11422934
    Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Andrew Roberts
  • Patent number: 11422903
    Abstract: Techniques are provided for maintaining and recomputing reference counts in a persistent memory file system of a node. Primary reference counts are maintained for pages within persistent memory of the node. In response to receiving a first operation to link a page into a persistent memory file system of the persistent memory, a primary reference count of the page is incremented before linking the page into the persistent memory file system. In response to receiving a second operation to unlink the page from the persistent memory file system, the page is unlinked from the persistent memory file system before the primary reference count is decremented. Upon the node recovering from a crash, the persistent memory file system is traversed in order to update shadow reference counts for the pages with correct reference count values, which are used to overwrite the primary reference counts with the correct reference count values.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 23, 2022
    Assignee: NetApp Inc.
    Inventors: Ananthan Subramanian, Matthew Fontaine Curtis-Maury, Vinay Devadas
  • Patent number: 11409657
    Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Andrew Roberts
  • Patent number: 11403218
    Abstract: A system includes first and second redundant controllers, and at least one logical volume accessible to the first and second redundant controllers. The system also includes metadata fields associated with the at least one logical volume. The metadata fields include a first age field configured to store a first age value associated with the first controller and a second age field configured to store a second age value associated with the second controller. The first age value and the second age value are employed to provide an indication of whether cache data for the at least one logical volume is valid. The system further includes a processor configured to update the first and second age values in the respective first and second age fields.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 2, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ritvik Viswanatha, Kishan Gelli, Joseph Skazinski
  • Patent number: 11392320
    Abstract: A method and apparatus for providing accurate command aging in a data storage device. A host provides multiple doorbell requests for the same command queue and a timestamp is saved for each request. When the storage device fetches the commands associated with the requests, the commands are all given the value of the timestamp associated with the requests and placed into the command queue and the aging algorithm of the storage device ages the commands. In an alternate embodiment, the commands may be assigned timestamps based on statistical values such as an average value, between the first and last doorbell request timestamps.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 19, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 11372574
    Abstract: A method is provided for managing availability of runtime asset data used by client applications hosted on workstations of an industrial system, the method including distributing runtime asset data about assets of the industrial system received at the plurality of workstations among runtime asset data caches associated with the client applications. At least a portion of locally stored runtime asset data stored on a local runtime asset data cache is replicated and stored remotely on the runtime asset data cache associated with another client application. The locally stored runtime asset data is periodically evaluated to determine if it is up-to-date, and in response to determining it is not up-to-date, the locally stored runtime asset data is updated by requesting and retrieving a replicated and updated version of the locally stored runtime asset data from the runtime asset data cache remotely storing the replicated version.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: June 28, 2022
    Assignee: Schneider Electric Systems USA, Inc.
    Inventors: Mallikarjuna Munugoti, James P. McIntyre, Sameer Kondejkar, Padmaja Bodanapu
  • Patent number: 11372764
    Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method also maintains, for the data element, a read access count that is incremented each time a data element is read in the cache. The method removes the data element from the higher performance portion of the cache in accordance with a cache demotion algorithm. If the write access count is below a first threshold and the read access count is above a second threshold, the method places the data element in the lower performance portion. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson
  • Patent number: RE49418
    Abstract: According to one embodiment, an information processing apparatus includes a storage device, a volatile memory, and a processor. The storage device includes a controller, a first nonvolatile storage module, and a second nonvolatile storage module whose access speed is higher than an access speed of the first nonvolatile storage module. The processor is configured to execute an operating system and a cache driver that are loaded into the volatile memory. The cache driver uses at least part of an area in the second nonvolatile storage module as a cache for the first nonvolatile storage module.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 14, 2023
    Assignee: KIOXIA Corporation
    Inventor: Takehiko Kurashige