Instruction Data Cache Patents (Class 711/125)
  • Patent number: 11507640
    Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 22, 2022
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Jinhua Tao, Tian Zhi, Shaoli Liu, Tianshi Chen, Yunji Chen
  • Patent number: 11487545
    Abstract: A processor branch prediction circuit employs back-invalidation of prediction cache entries based on decoded branch instructions. The execution information of a previously executed branch instruction is obtained from a prediction cache entry and compared to generated decode information in an instruction decode circuit. Execution information of branch instructions stored in the prediction cache entry is updated in response to a mismatch of the execution information and the decode information of the branch instruction. Existing branch prediction circuits invalidate prediction cache entries of a block of instructions when the block of instructions is invalidated in an instruction cache. As a result, valid branch instruction execution information may be unnecessarily discarded. Updating prediction cache entries in response to a mismatch of the execution information and the decode information of the branch instruction maintains the execution information in the prediction cache.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: November 1, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Daren E. Streett, Rami Mohammad Al Sheikh, Michael Scott McIlvaine, Richard W. Doing, Robert Douglas Clancy
  • Patent number: 11481330
    Abstract: Methods, systems, and devices for cache architectures for memory devices are described. For example, a memory device may include a main array having a first set of memory cells, a cache having a second set of memory cells, and a cache delay register configured to store an indication of cache addresses associated with recently performed access operations. In some examples, the cache delay register may be operated as a first-in-first-out (FIFO) register of cache addresses, where a cache address associated with a performed access operation may be added to the beginning of the FIFO register, and a cache address at the end of the FIFO register may be purged. Information associated with access operations on the main array may be maintained in the cache, and accessed directly (e.g., without another accessing of the main array), at least as long as the cache address is present in the cache delay register.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Nicola Del Gatto
  • Patent number: 11481328
    Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 25, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Alexandros Daglis, Paolo Faraboschi, Qiong Cai, Gary Gostin
  • Patent number: 11409539
    Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer, Chris Baronne
  • Patent number: 11379381
    Abstract: A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Mi Seon Han, Yun Jeong Mun, Young Pyo Joo
  • Patent number: 11341117
    Abstract: System and methods for evicting and inserting eviction an entry for a deduplication table are described.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 24, 2022
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Joseph S. Hasbani, John Martin Hayes, Ethan L. Miller, Cary A. Sandvig
  • Patent number: 11334384
    Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment burst mode are disclosed. A scheduler queue assignment unit receives a dispatch packet with a plurality of operations from a decode unit in each clock cycle. The scheduler queue assignment unit determines if the number of operations in the dispatch packet for any class of operations is greater than a corresponding threshold for dispatching to the scheduler queues in a single cycle. If the number of operations for a given class is greater than the corresponding threshold, and if a burst mode counter is less than a burst mode window threshold, the scheduler queue assignment unit dispatches the extra number of operations for the given class in a single cycle. By operating in burst mode for a given operation class during a small number of cycles, processor throughput can be increased without starving the processor of other operation classes.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: May 17, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alok Garg, Scott Andrew McLelland, Marius Evers, Matthew T. Sobel
  • Patent number: 11301251
    Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 12, 2022
    Assignee: SiFive, Inc.
    Inventors: Joshua Smith, Krste Asanovic, Andrew Waterman
  • Patent number: 11294678
    Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 5, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew T. Sobel, Donald A. Priore, Alok Garg
  • Patent number: 11249762
    Abstract: An apparatus and method are provided for handling incorrect branch direction predictions. The apparatus has processing circuitry for executing instructions, branch prediction circuitry for making branch direction predictions in respect of branch instructions, and fetch circuitry for fetching instructions from an instruction cache in dependence on the branch direction predictions and for forwarding the fetched instructions to the processing circuitry for execution. A cache location buffer stores cache location information for a given branch instruction for which accuracy of the branch direction predictions made by the branch prediction circuitry is below a determined threshold. The cache location information identifies where within the instruction cache one or more instructions are stored that will need to be executed in the event that a subsequent branch direction prediction made for the given branch instruction is incorrect.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 15, 2022
    Assignee: Arm Limited
    Inventors: Houdhaifa Bouzguarrou, Guillaume Bolbenes, Thibaut Elie Lanois
  • Patent number: 11243767
    Abstract: A caching device, an instruction cache, a system for processing an instruction, a method and apparatus for processing data and a medium are provided. The caching device includes a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port. The is configured to write cache data into a set storage address in the first queue and/or the second queue; the read port is configured to read all cache data from the first queue and/or the second queue at one time; the press-in port is configured to press cache data into the first queue and/or the second queue; the first pop-up port is configured to pop up cache data from the first queue; and the second pop-up port is configured to pop up cache data from the second queue.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 8, 2022
    Assignee: Beijing Baidu Netcom Science and Technology Co., Ltd.
    Inventors: Chao Tang, Xueliang Du, Yingnan Xu, Kang An
  • Patent number: 11237730
    Abstract: A method for improving cache hit ratios for selected volumes within a storage system is disclosed. In one embodiment, such a method includes monitoring I/O to multiple volumes residing on a storage system. The storage system includes a cache to store data associated with the volumes. The method determines, from the I/O, which particular volumes of the multiple volumes would benefit the most if provided favored status in the cache. The favored status provides increased residency time in the cache to the particular volumes compared to volumes not having the favored status. The method generates a list of the particular volumes and transmits the list to the storage system. The storage system, in turn, provides increased residency time to the particular volumes in accordance with their favored status. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Beth A. Peterson, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11112774
    Abstract: A numerical controller determines whether or not block prefetching from a program is sufficient based on whether at least one block subsequent to a predetermined reference block, which exists after a running block of the program and is needed to execute the reference block, has been prefetched or not. If the determination result is that prefetching is not sufficient, block prefetching from the program is performed.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 7, 2021
    Assignee: Fanuc Corporation
    Inventor: Nobuhito Oonishi
  • Patent number: 11108833
    Abstract: A method and devices for handling crossed-invite situations in set-up of IP-based sessions. A local device receives an incoming session invite after sending an outgoing session invite before the outgoing session invite has been accepted. It then determines that the incoming session invite was sent by the remote device to which the outgoing session invite is also addressed. The method includes determining a remote device priority value from identifying information contained in the incoming session invite, comparing the remote device priority value with a local device priority value to determine whether the remote device or the local device is higher priority and, if the remote device is higher priority, canceling the outgoing session invite and displaying an incoming call answer screen for the incoming session invite, and if the local device is higher priority, waiting for cancelation of the incoming session invite and acceptance of the outgoing session invite.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 31, 2021
    Assignee: BlackBerry Limited
    Inventors: Bechir Trabelsi, Andrew Michael Allen, Kevin N. Chen, Lawrence Edward Kuhl
  • Patent number: 11099995
    Abstract: Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the hierarchical arrangement of memory. Examples include circuitry for a processor receiving a prefetch request from a core of the processor to prefetch data from the first level to the second level. The prefetch request indicating an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Michael Klemm, Thomas Willhalm
  • Patent number: 11080195
    Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 3, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
  • Patent number: 11048440
    Abstract: A memory system includes a memory device having a plurality of memory blocks and a subcommand storage circuit, and a memory controller for controlling the memory device, wherein the memory device is capable of being in one or more of a ready state, a first busy state, and a second busy state, and wherein the subcommand is stored in the subcommand storage circuit when the subcommand is received from the memory controller in the first busy state and the subcommand is executable after the first busy state is released, and the subcommand stored in the subcommand storage circuit is executed after the memory device is changed to the ready state.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung-Won Bae, Jun-Hyuk Lee, Deung-Kak Yoo, Min-Kyu Lee
  • Patent number: 11042315
    Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Christopher E. Cox, Navneet Dour, Asaf Rubinstein, Israel Diamand
  • Patent number: 11044140
    Abstract: Embodiments of the present disclosure provide a method and an apparatus for serialization and deserialization of a message structure. The method for serialization includes: acquiring a message structure, and pre-processing the message structure to generate a corresponding target version number, wherein message structures with different contents correspond to different version numbers, and the message structure is a structure of status information transmitted by a server to a client; serializing information to be transmitted to obtain a corresponding byte stream, wherein the information to be transmitted carries data of the status information and the target version number; and transmitting the byte stream to the client.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 22, 2021
    Assignee: MICROFUN CO., LTD
    Inventors: Chi Gao, Guangrong Su, Yingjie Han
  • Patent number: 11042462
    Abstract: Identifying computer program execution characteristics for determine relevance of pattern instruction executions to determine characteristics of a computer program. Filters are utilized to determine which subsequent occurrences of execution of at least one computer instruction are relevant to a counter based on execution characteristics of the at least one computer instruction where the counter counts the subsequent occurrences of execution of at least one computer instruction following prior executions of the same at least one computer instruction.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Thomas Sofia, Peter Sutton, Robert W. St. John, Matthias Klein
  • Patent number: 11030073
    Abstract: Techniques are provided for redundant execution by a better processor for intensive dynamic profiling after initial execution by a constrained processor. In an embodiment, a system of computer(s) receives a request to profile particular runtime aspects of an original binary executable. Based on the particular runtime aspects and without accessing source logic, the system statically rewrites the original binary executable into a rewritten binary executable that invokes telemetry instrumentation that makes observations of the particular runtime aspects and emits traces of those observations. A first processing core having low power (capacity) performs a first execution of the rewritten binary executable to make first observations and emit first traces of the first observations. Afterwards, a second processing core performs a second (redundant) execution of the original binary executable based on the first traces.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 8, 2021
    Assignee: Oracle International Corporation
    Inventors: Sam Idicula, Kirtikar Kashyap, Arun Raghavan, Evangelos Vlachos, Venkatraman Govindaraju
  • Patent number: 10997066
    Abstract: A storage device includes a descramble module configured to descramble at least a portion of a read command, which includes logical block address (LBA) information and first meta information, into first signature information and first physical address (PA) information, for accessing a flash memory. A compare module is provided, which is configured to compare the first signature information against stored signature information to thereby determine an equivalency or discrepancy therebetween. An access module is provided, which is configured to use the first PA information to access a data region of the flash memory, upon determination of the equivalency by said compare module.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 4, 2021
    Inventors: Dong-Woo Kim, Jae Sun No, Song Ho Yoon, Kyoung Back Lee, Wook Han Jeong
  • Patent number: 10990159
    Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 27, 2021
    Assignee: Apple Inc.
    Inventors: Bernard Joseph Semeria, John H. Mylius, Pradeep Kanapathipillai, Richard F. Russo, Shih-Chieh Wen, Richard H. Larson
  • Patent number: 10963399
    Abstract: A memory system may include a storage device and a controller. The storage device may include a non-volatile memory device. The controller may include a device memory. The controller may control operations of the non-volatile memory device in accordance with a request of a host device. wherein the controller includes a map data management circuit configured to cache one or more segments from a plurality of map segment groups stored in the storage device, each segment having information including a reference count and mapping relationships between logical addresses and physical addresses, detect, among the one or more cached segments, an upload target segment in which the reference count is greater than a predetermined count and transmit, when a predetermined number or greater of upload target segments are detected within a first map segment group, the predetermined number or greater of upload target segments to the host device.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 10896044
    Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 19, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marius Evers, Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Arunachalam Annamalai, Donald A. Priore, Douglas R. Williams
  • Patent number: 10891135
    Abstract: A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 12, 2021
    Inventors: Paul E. Kitchin, Nicholas Humphries, Ken Yu Lim, Ryan Hensley
  • Patent number: 10860324
    Abstract: An apparatus and method are provided for making predictions for branch instructions. The apparatus has a prediction queue for identifying instructions to be fetched for execution, and branch prediction circuitry for making predictions in respect of branch instructions, and for controlling which instructions are identified in the prediction queue in dependence on the predictions. During each prediction iteration, the branch prediction circuitry makes a prediction for a predict block comprising a sequence of M instructions. The branch prediction circuitry comprises a target prediction storage having a plurality of entries that are used to identify target addresses for branch instructions that are predicted as taken, the target prediction storage being arranged as an N-way set associative storage structure comprising a plurality of sets. Each predict block has an associated set within the target prediction storage.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Arm Limited
    Inventors: Houdhaifa Bouzguarrou, Guillaume Bolbenes, Eddy Lapeyre, Luc Orion
  • Patent number: 10853224
    Abstract: Indexing and searching a bit-accurate trace for arbitrary length/arbitrary alignment values in traced thread(s). Indexing includes, while replaying a plurality of trace segments, identifying a set of n-grams for each trace segment that exist in processor data influx(es) and/or store(s) to a processor cache that resulted from replay of the trace segment. An index data structure, which associates each identified n-gram with trace location(s) at or in which the n-gram was found, is then generated. The index data structure thus associates unique n-grams with prior execution time(s) at or during which the traced thread(s) read or wrote the n-gram. Searching an indexed trace includes identifying n-grams in a query and using the index data structure to determine trace location(s) where these n-grams were seen during indexing. A query response is generated after using trace replay to locate particular execution time(s) and memory location(s) at which the n-grams occurred.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 1, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Jordi Mola
  • Patent number: 10776261
    Abstract: A storage apparatus managing method, applied to a first storage apparatus and a second storage apparatus coupled to an electronic apparatus, wherein the first storage apparatus comprises a local registering region and a global registering region, comprising: (a) receiving a read request indicating reading a target data unit from the second storage apparatus; (b) confirming whether the global registering region has the target data unit; (c) if yes, reading the target data unit from the global registering region, if not, confirming whether the local registering region has the target data unit; and (d) reading the target data unit from the local registering region if the local registering region has the target data unit, reading the target data unit from the second storage apparatus if the local registering region does not have the target data unit.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: September 15, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Chao-Yu Lin
  • Patent number: 10754775
    Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: NVIDIA Corporation
    Inventors: Jay Gupta, Gosagan Padmanabhan, Devesh Mittal, Kaushal Agarwal
  • Patent number: 10747668
    Abstract: A shared cache memory can be logically partitioned among different workloads to provide isolation between workloads and avoid excessive resource contention. Each logical partition is apportioned a share of the cache memory, and is exclusive to a respective one of the workloads. Each partition has an initial size allocation. Historical data can be collected and processed for each partition and used to periodically update its size allocation.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 18, 2020
    Assignee: VMWARE, INC.
    Inventors: Zhihao Yao, Tan Li, Sunil Satnur, Kiran Joshi
  • Patent number: 10719448
    Abstract: A cache is presented. The cache comprises a tag array configured to store one or more tag addresses, a data array configured to store data acquired from a dynamic random access memory device, and a cache controller. The cache controller is configured to: receive a cache access request; determine, based on an indication associated with the cache access request, a cache access policy; and perform an operation to the tag array and to the data array based on the determined cache access policy.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 21, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Xiaowei Jiang
  • Patent number: 10719442
    Abstract: An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Ren Wang, Raanan Sade, Yipeng Wang, Tsung-Yuan Tai, Sameh Gobriel
  • Patent number: 10713054
    Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 14, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Thomas Cloqueur, Anthony Jarvis
  • Patent number: 10657063
    Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 19, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yen-Ju Lu, Chao-Wei Huang
  • Patent number: 10621092
    Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Fernando Latorre, Josep M. Codina, Enric Gibert Codina, Pedro Lopez, Carlos Madriles, Alejandro Martinez Vincente, Raul Martinez, Antonio Gonzalez
  • Patent number: 10599439
    Abstract: Provided are a method and apparatus for processing a very long instruction word (VLIW) instruction. The method includes acquiring a calculation allocation instruction including information regarding whether the VLIW instructions are allocated to a plurality of slots; updating a database including the information regarding whether the VLIW instructions are allocated to the plurality of slots based on the acquired calculation allocation instruction; and allocating at least one VLIW instruction to each of the plurality of slots based on the updated database.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-kwan Suh, Suk-jin Kim, Do-hyung Kim, Tai-song Jin
  • Patent number: 10599334
    Abstract: Improved techniques for memory expansion are provided. A storage volume is opened on a storage device attached to a computing system, and the storage volume is configured as extended memory. A number of hardware threads available in the computing system are determined, and a number of contexts equal to the determined number of hardware threads are generated. Each context is assigned to one of the hardware threads. It is further determined that a first hardware thread has requested a first page that has been paged to the storage volume, where the first hardware thread is assigned a first context. A synchronous input output (I/O) interface is accessed to request that the first page be moved to memory, based on the first context. While the first page is being moved to memory, a priority of the first hardware thread is reduced.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sanket Rathi, Bruce Mealey
  • Patent number: 10592215
    Abstract: Building a unikernel is disclosed. Code is retrieved from a code repository. One or more unikernel build configuration options are identified. The code is analyzed to determine portions of an operating system required to execute the code. The code is compiled with the determined portions of the operating system into a unikernel that is deployable on a virtual machine to execute the code.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: March 17, 2020
    Assignee: NanoVMs, Inc.
    Inventor: Ian Eyberg
  • Patent number: 10572334
    Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: February 25, 2020
    Assignees: ARM Limited, The Regents of the University of Michigan
    Inventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
  • Patent number: 10572430
    Abstract: An integrated circuit may include a printed circuit board and multiple processor sockets on the printed circuit board. Each of the multiple processor sockets is operable to receive a microprocessor and a programmable device. When a microprocessor is placed in a processor socket, that microprocessor may communicate with memory dual in-line memory modules (DIMMs). When a programmable device is placed in a processor socket, that programmable device may first be configured using a configuration DIMM and may then communicate with memory DIMMs during normal operation. The configuration DIMM may include multiple options for configuring the programmable device and may also provide additional management functions specifically tailored to the programmable device.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: David Browning, Brandon Courtney, John Eley
  • Patent number: 10554795
    Abstract: The present application discloses an uplink transmission method, including: generating, by a media access control (MAC) layer of a first device, MAC information, then generating a first primitive carrying the MAC information, and sending the first primitive to an adjacent higher layer of the MAC layer of the first device; receiving, by the adjacent higher layer of the MAC layer of the first device, the first primitive, then generating an adjacent higher layer message carrying the MAC information, and sending the adjacent higher layer message to an adjacent higher layer of a MAC layer of a second device; and receiving, by the adjacent higher layer of the MAC layer of the second device, the adjacent higher layer message, then generating a second primitive carrying the MAC information, and sending the second primitive to the MAC layer of the second device.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 4, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chen Dong, Tong Jiang, Qiang Li
  • Patent number: 10553296
    Abstract: A memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; a read/write circuit including a plurality of page buffers coupled to the plurality of bit lines; a power supply circuit suitable for generating voltages to be applied to the memory cell array and the read/write circuit; and a control circuit suitable for receiving a read command and an address signal from an external device, and controlling the memory cell array, the read/write circuit and the power supply circuit based on the read command and the address signal.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae-Hoon Kim
  • Patent number: 10528472
    Abstract: A computer implemented method for saving cache access power is suggested. The cache is provided with a set predictor logic for providing a generated set selection for selecting a set in the cache, and with a set predictor cache for pre-caching generated set indices of the cache. The method comprises further: receiving a part of a requested memory address; checking, in the set predictor cache, whether the requested memory address is already generated; in the case, that the requested memory address has already been generated: securing that the set predictor cache is switched off; issuing the pre-cached generated set index towards the cache; and securing that only that part of the cache is switched on that is associated with the pre-cached generated set index.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter
  • Patent number: 10503507
    Abstract: A method, computer readable medium, and system are disclosed for inline data inspection. The method includes the steps of receiving, by a load/store unit, a load instruction and obtaining, by an inspection circuit that is coupled to the load/store unit, data specified by the load instruction. Additional steps include determining that the data equals zero and transmitting the data and a predicate signal to the load/store unit, wherein the predicate signal indicates that the data equals zero. Alternative additional steps include computing a predicate value based on a comparison between the data and a threshold value and transmitting the data and the predicate value to the load/store unit, wherein the predicate value is asserted when the data is less than the threshold value and is negated when the data is not less than the threshold value.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 10, 2019
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey Michael Pool, Andrew Kerr, John Tran, Ming Y. Siu, Stuart Oberman
  • Patent number: 10503661
    Abstract: Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan, Colin Beaton Verrilli
  • Patent number: 10467014
    Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 5, 2019
    Assignee: CRYPTOGRAPHY RESEARCH, INC.
    Inventors: William C. Moyer, Jeffrey W. Scott
  • Patent number: 10439923
    Abstract: Approaches described relate to the management of messages in an electronic environment. In particular, various approaches provide for analyzing messages of different message types to efficiently process those messages in a service environment, such as a multi-tenant environment. The messages can include one or more message fields, allowing for a plurality of different message types. The messages can be analyzed to identify known message types, and processing of messages of the same type can be expedited, e.g., by more quickly deserializing that message using cached message offset information associated with that message type. For example, a message that includes message data and an identifier can be received. The identifier can be matched to an entry associated with the identifier and message offset information.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 8, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Ryan M. Pruden
  • Patent number: 10402349
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 3, 2019
    Assignee: ARM Limited
    Inventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris