Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

Abstract: Methods and systems for solid state drives are provided, including assigning a first shared namespace to a first instance and a second instance of a storage operating system for enabling write access to the first instance to a first zone of a first portion of a flash storage system, and write access to the second instance to a second zone of the first portion; using a first exclusive namespace by the first instance to store metadata at a first segment of a second portion of the flash storage system; using a second exclusive namespace by the second instance to store metadata at a second segment of the second portion of the flash storage system; and providing read only access to the first instance and the second instance to a second zone of the first portion using the first namespace.

Abstract: Systems, methods, and computer readable storage mediums for blockchain logging of volume-level events in a storage system. Blockchain logging of volume-level event includes receiving, by a storage controller, a storage operation directed to a storage volume; detecting, by the storage controller, that the storage operation is a volume-level event associated that affects the volume as a whole; and updating a blockchain ledger to include information describing the volume-level event, wherein the information comprises data describing a host associated with the event.

Abstract: Workload planning with quality-of-service (‘QoS’) integration, including: determining, for each of a plurality of entities, one or more QoS thresholds associated with the entity; determining, for each of the plurality of entities, one or more resource utilization levels associated with the entity; and determining, in dependence upon the one or more QoS thresholds associated with the plurality of entities, the one or more resource utilization levels associated with the plurality of entities, and one or more overprovisioning factors associated with the storage system, a risk factor that identifies the likelihood that one or more system resources will be overconsumed by the plurality of entities.

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

Abstract: An application-specific integrated circuit (ASIC) and method are provided for executing a memory-hard algorithm requiring reading generated data. A processor or state machine executes one or more steps of the memory-hard algorithm and requests the generated data. At least one specialized circuit is provided for generating the generated data on demand in response to a request for the generated data from the processor. Specific embodiments are applied to memory-hard cryptographic algorithms, including Ethash and Equihash.

Abstract: A data communication device includes: a fixed value memory that stores a fixed value; a received data memory that stores received data inputted through a bus; an output data memory that stores output data; a comparison determination unit that outputs a comparison determination result signal indicating a determination result of comparing the fixed value and a value of the received data; a data output unit that has a first state of outputting the output data to the bus and a second state of not outputting the output data to the bus; a command analyzing unit that outputs a data output control signal based on a command; and an output controller that outputs a control signal for controlling the data output unit to enter the first state or the second state based on the comparison determination result signal and the data output control signal.

Abstract: A storage area network architecture and a method for storing data in the storage area network architecture are disclosed. For example, the storage area network architecture comprises a first layer of servers, the first layer of servers comprising a plurality of file receiving servers, a second layer of servers, the second layer of servers comprising a plurality of file sharing servers in communication with the first layer of servers and a third layer of servers, the third layer of servers comprising a plurality of storage servers in communication with the second layer of servers.

Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Abstract: A network device may receive one or more packets, and may determine a flow control parameter, a rate limiting parameter, and a statistical sampling parameter associated with a slow counter. The network device may determine whether the flow control parameter satisfies a first threshold, whether the rate limiting parameter satisfies a second threshold, and whether the statistical sampling parameter satisfies a third threshold. The network device may identify a counter event associated with one of the one or more packets, and may selectively assign the counter event to a fast counter when at least one of the first threshold, the second threshold, or the third threshold being satisfied, or to the slow counter when none of the first threshold, the second threshold, and the third threshold being satisfied.

Abstract: Data resiliency in a cloud-based storage system, including: receiving, for storage within a first tier of cloud storage of the cloud-based storage system, one or more segments of data; generating, for each of one or more shards of data of the one or more segments of data, self-describing information for recoverability of the one or more shards of data; and storing, within a second tier of cloud storage of the cloud-based storage system, both the one or more shards of data and the generated self-describing information for recoverability of the one or more shards of data.

Abstract: A data collection server includes a communicator, a use frequency estimator, and a data saver. The communicator receives device data from a device. The use frequency estimator estimates use frequency of the device data received by the communicator. The data saver stores the device data in, among a plurality of storage servers corresponding to different levels of use frequency, one of the plurality of storage servers that corresponds to the use frequency estimated by the use frequency estimator.

Abstract: A system and method for delivery of an online course, customized to a student based on captured student's actions in interacting with the course is disclosed. The actions are compared to actions of others, where the actions of others are correlated with known learning results. In part, such comparison involves tagged content and the tagging process is also a part of the present invention.

Abstract: Techniques are disclosed relating to controlling cache replacement. In some embodiments, search control circuitry is configured to perform multiple searches of a data structure (e.g., page table walks) where searches traverse multiple links between elements of the data structure. In some embodiments, a traversal cache caches traversal information that is usable by searches to skip one or more links traversed by one or more prior searches. In some embodiments, tracking control circuitry stores tracking information in a first entry, where the tracking information indicates a location in the traversal cache at which prior traversal information for a first search is stored. In some embodiments, replacement control circuitry selects, based on the tracking information in the first entry of the tracking control circuitry, an entry in the traversal cache for new traversal information generated by the first search (which may include selecting the first entry to override a default replacement policy).

Abstract: A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

Abstract: Techniques for optimizing snapshot changed blocks metadata querying are described. A method of optimizing snapshot changed blocks metadata querying comprises receiving a request to identify one or more changed blocks of a block storage volume in a storage service of a provider network, identifying at least one changed cluster of blocks of the storage volume, the at least one cluster of blocks comprising a plurality of blocks of the storage volume, and identifying at least one changed block from the plurality of blocks associated with the at least one changed cluster.

Abstract: An audio processing device for speech recognition is provided, which includes a memory circuit, a power spectrum transfer circuit, and a feature extraction circuit. The power spectrum transfer circuit is coupled to the memory circuit, reads frequency spectrum coefficients of time-domain audio sample data from the memory circuit, generates compressed power parameters by performing a power spectrum transfer processing and a compressing processing according to the frequency spectrum coefficients, and writes the compressed power parameters into the memory circuit. The feature extraction circuit is coupled to the memory circuit, reads the compressed power parameters from the memory circuit, generates an audio feature vector by performing mel-filtering and frequency-to-time transfer processing according to the compressed power parameters. The bit width of the compressed power parameters is less than the bit width of the frequency spectrum coefficients.

Abstract: Techniques involve: determining, according to a received request for creating a stripe in a storage system, a type of the stripe; acquiring a first workload distribution corresponding to the determined type, wherein the first workload distribution describes the distribution, among a first number of storage devices, of multiple extents in a set of stripes of this type in the storage system; selecting a set of extents from the first number of storage devices based on the first workload distribution, so that the distribution, among the first number of storage devices, of the selected set of extents and the multiple extents in the set of stripes of this type satisfies a preset distribution condition associated with the type; and using the selected set of extents to create the requested stripe based on a stripe creation rule associated with the type. The stripes can be managed in a more effective manner.

Abstract: A system includes a memory system and a processor of a first processing system including a processor core, a direct memory access controller, and a communication interface. The processor core is configured to execute a plurality of instructions to configure the direct memory access controller to trigger a transmitter interrupt upon transmitting a first synchronization message through the communication interface to a second processing system, configure the direct memory access controller to trigger a receiver interrupt upon receiving a second synchronization message from the second processing system, determine a time difference between triggering of the transmitter interrupt and the receiver interrupt, and adjust a synchronization skew of a real-time scheduler based on the time difference to tune real-time synchronization between the first processing system and the second processing system.

Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

Abstract: An optical line terminal (OLT) (1) includes an interface (I/F) board (2) configured to communicate with an external apparatus, a graphics processing unit (GPU) (4) configured to perform a first process, and a central processing unit (CPU) (3) configured to control the I/F board (2) and the GPU (4).

Abstract: This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.

Abstract: One or more techniques and/or computing devices are provided for data synchronization. For example, an in-flight log may be maintained to track storage operations that are received by a first storage node, but have not been committed to both first storage of the first storage node and second storage of a second storage node that has a replication relationship, such as a disaster recovery relationship, with the first storage node. A dirty region log may be maintained to track regions within the first storage that have been modified by storage operations that have not been replicated to the second storage. Accordingly, a catchup synchronization phase (e.g., asynchronous replication by a resync scanner) may be performed to replicate storage operations (e.g., replicate data within dirty regions of the first storage that were modified by such storage operations) to the second storage until the first storage and the second storage are synchronized.

Abstract: A communication system includes an information acquisition unit that acquires information (road information), a type identifying unit that identifies the type of the information acquired by the information acquisition unit, a storage unit (vehicle storage unit, server storage unit) that stores relationship information that associates the type of the information with the transmission direction of the information, and a direction identifying unit that identifies the transmission direction of the information acquired by the information acquisition unit based on the identification result by the type identifying unit and the relationship information stored in the storage unit (vehicle storage unit, server storage unit).

Abstract: One embodiment facilitates data compression. During operation, the system receives, by a host computing device, a request to write a first set of data. The system writes the first set of data to a first storage device of a storage component. A storage component controller performs compression on the first set of data to obtain compressed data. The controller transmits, to a file system component of the host computing device, metadata associated with the compressed data. The file system component inserts in a journal an entry based on the metadata associated with the compressed data. The system writes, by the controller, the compressed data to a second storage device of the storage component, thereby enhancing performance of the host computing device by reducing a number of data transfers involved in compressing and writing of the first set of data.

Abstract: Processing of commands at a graphics processor are controlled by receiving input data and generating a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory, and submitting the command to a queue for later processing at the graphics processor. Subsequent to submitting the command, but before the write to external memory has been completed, further input data is received and it is determined that the buffer of data does not need to be written to external memory. The graphics processor is then signalled to prevent at least a portion of the write to external memory from being performed for the command.

Abstract: A system includes a memory system and a processor of a first processing system including a processor core, a direct memory access controller, and a communication interface. The processor core is configured to execute a plurality of instructions to configure the direct memory access controller to trigger a transmitter interrupt upon transmitting a first synchronization message through the communication interface to a second processing system, configure the direct memory access controller to trigger a receiver interrupt upon receiving a second synchronization message from the second processing system, determine a time difference between triggering of the transmitter interrupt and the receiver interrupt, and adjust a synchronization skew of a real-time scheduler based on the time difference to tune real-time synchronization between the first processing system and the second processing system.

Abstract: According to an embodiment, power demands of a computing device or component thereof may be stabilized by performing redundant operations during periods of otherwise low power demand. In so doing, the current load of the device/component remains relatively stable, potentially greatly reducing voltage droops and overshoots. This can reduce the peak voltage and peak power rating of the device/component. In certain embodiments, such as in network switches and routers, the redundant operations may include queries against a content addressable memory (CAM), such as a ternary content addressable memory (TCAM). Moreover, in an embodiment the queries may be designed to always, or at least be highly likely to, miss the entries in the CAM, thereby ensuring maximum power usage. In another embodiment, the redundant operations include read operations on a random access memory (RAM). In other embodiments, redundant operations may be performed with respect to other power-intensive subsystems.

Abstract: An apparatus and method are provided for controlling allocation of information into a cache storage. The apparatus has processing circuitry for executing instructions, and for allowing speculative execution of one or more of those instructions. A cache storage is also provided having a plurality of entries to store information for reference by the processing circuitry, and cache control circuitry is used to control the cache storage, the cache control circuitry comprising a speculative allocation tracker having a plurality of tracking entries. The cache control circuitry is responsive to a speculative request associated with the speculative execution, requiring identified information to be allocated into a given entry of the cache storage, to allocate a tracking entry in the speculative allocation tracker for the speculative request before allowing the identified information to be allocated into the given entry of the cache storage.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A method and system for policy class based data migration. Specifically, the method and system disclosed herein entail dynamically changing policy classes with which any given data migration may be associated while the given data migration is transpiring. In transitioning between policy classes, different levels of resources, available to different policy classes, respectively, may be allocated to supporting the given data migration.

Abstract: The invention is generally directed to systems and methods of automatically tuning big data workloads across various cloud platforms, the system being in communication with a cloud platform and a user, the cloud platform including data storage and a data engine. The system may include: a system information module in communication with the cloud platform; a static tuner in communication with the system information module; a cloud tuner in communication with the static tuner and the user; and an automation module in communication with the cloud tuner. Methods may include extracting information impacting or associated with the performance of the big data workload from the cloud platform; determining recommendations based at least in part on the information extracted; iterating through different hardware configurations to determine optimal hardware and data engine configuration; and applying the determined configuration to the data engine.

Abstract: Disclosed are various embodiments for identifying devices that are part of a network. Devices are modeled based on physical characteristics. Devices are classified or device communications can be verified.

Abstract: Embodiments of the present disclosure a method, device and computer program product for storage management. The method comprises: determining, from a storage system, a plurality of storage areas corresponding to a plurality of files; selecting, from the plurality of storage areas, a pair of first storage area and second storage area, both the first storage area and the second storage area having non-empty available space; moving at least part of data stored in used space of the first storage area to available space of the second storage area; and in response to determining that the used space of the first storage area becomes empty after the moving, releasing the first storage area. In this way, the storage space can be effectively released and the storage efficiency is accordingly improved.

Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.

Abstract: Apparatus and associated methods for implementing atomic instructions for copy-XOR of data. An atomic-copy-xor instruction is defined having a first operand comprising an address of a first cacheline and a second operand comprising an address of a second cacheline. The atomic-copy-xor instruction, which may be included in an instruction set architecture (ISA) of a processor, performs a bitwise XOR operation on copies of data retrieved from the first cacheline and second cacheline to generate an XOR result, and replaces the data in the first cacheline with a copy of data from the second cacheline when the XOR result is non-zero.

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Abstract: A temporary page is allocated in which pages are loaded into main memory and having associated physical disk storage. The temporary page is also flagged as being temporary. Subsequently, a savepoint is initiated for the database so that, during the savepoint, the temporary page can be modified without acquiring a consistent change while preventing other non-temporary pages from being modified. Later, the savepoint can be finalized to enable the database to be rolled back to a point in time corresponding to the savepoint as part of a recovery process.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: Techniques for optimizing write IO bandwidth and latency in an active-active clustered system using storage object affinity to a single node. The active-active clustered system can include at least a primary storage node and a secondary storage node that maintain their own journals. The respective journals are directly accessible to both storage nodes. The journals are synchronized for each page or entity of a storage object when a storage IO request is issued to a storage node to which the storage object does not have affinity. Such synchronization is performed in the framework of acquiring a lock on the entity of the storage object during internode communications. To facilitate recovery from a disaster, data loss, and/or data corruption, transaction IDs associated with storage IO operations are employed to facilitate identification of the most up-to-date reference or description information for a given data or metadata page of a storage object.

Abstract: Various embodiments for managing data stored in a tiered data storage environment, by a processor device, are provided. A data file is proactively migrated from a lower tier to a higher tier of the tiered data storage environment by using a multidimensional algorithm adopting an actual frequency of access of the data file to gauge a slope of a predicted frequency of access of the data file. The data file is migrated from the lower tier to the higher tier only if each of a plurality of criteria of the multidimensional algorithm is satisfied.

Abstract: The disclosed computer-implemented method for automatic storage tiering may include (1) receiving characteristics of previous accesses to storage system objects stored in a data storage system including multiple storage tiers, (2) generating, based on the characteristics of previous accesses to the storage system objects, a model that predicts characteristics of future accesses to the storage system objects, (3) selecting, based on the model, a next storage tier of the multiple storage tiers for each of the storage system objects, and (4) relocating at least some of the storage system objects from a current storage tier to the next storage tier selected for each of the at least some of the storage system objects. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for removing stale messages from a storage controller is disclosed. In one embodiment, such a method includes querying, by a host system, a storage controller to determine ownership of a lock on the storage controller. The host system receives, in response to the query, information indicating that the lock has been granted to the host system. This allows the host system to treat the lock as being granted even though the host system has not received a “lock granted” message from the storage controller. Before using the lock, the host system sends, to the storage controller, an instruction to clear any stale messages on the storage controller related to the lock. A corresponding system and computer program product are also disclosed.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.

Abstract: Use of a survival queue to manage a container-based flash cache is disclosed. In various embodiments, a corresponding survival time is associated with each of a plurality of containers stored in a flash cache, each container comprising a plurality of data blocks. The survival time may be determined based at least in part on a calculated proportion of relatively recently accessed data blocks associated with the container is associated with the container. A container to evict from the flash cache is selected based at least in part on a determination that the corresponding survival time of the selected container has expired.

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: According to some embodiments, so-called “NS-Tree” indexes may be used to calculate whether all (or a portion) of two independent tables are consistent. The NS-Tree indexes may be comprised of various elements, e.g., a synchronization time, a primary key, a hash of the complete record itself, and an aggregate value associated with each index entry (e.g., an accumulated XOR value). At any point in the index, an entry may possess the accumulated aggregate value of all key entries in the table up to that point. That aggregate value may be used to validate data consistency with another table(s) maintaining the same index. Due to the unique composition of the NS-Tree index, users can also validate two data sets within a ‘sub-range’ of the entire data set. According to other embodiments, NS-Tree indexes may also be applied to two different clusters of nodes by applying the NS-Trees at a ‘federated’ level.

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.