Hierarchical Memories Patents (Class 711/117)
  • Patent number: 10409517
    Abstract: Embodiments of the present disclosure provide a device for data backup comprising: a secondary backup device coupled to a primary backup device, the secondary backup device further comprising: data segmentation unit operable to divide target data to be backed up into a plurality of data segments; data fingerprint generation unit operable to generate a corresponding data fingerprint for each data segment from a plurality of data segments, and providing the data fingerprint to the primary backup device for backing up the target data at the primary backup device, wherein the data fingerprint is a mapped data segment of a length less than a corresponding data segment length.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 10, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Colin Yong Zou, Kun Wang, Sean Cheng Ye, Junping Frank Zhao, Man Lv
  • Patent number: 10409512
    Abstract: A method of operating a storage controller which is included in a data storage device and initializes at least one main memory of the data storage device includes: transmitting, by a processor of the storage controller, a first indication signal for indicating initialization of the main memory of the data storage device to a first memory initialization device; generating, by a register of the first memory initialization device, a selection signal corresponding to the first indication signal, and outputting, by a memory set of the first memory initialization device, a first initialization signal to the main memory in response to the selection signal to initialize the main memory.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong Kim
  • Patent number: 10402571
    Abstract: Technologies for de-duplicating encrypted content include fragmenting a file into blocks on a computing device, encrypting each block, and storing each encrypted block on a content data server with associated keyed hashes and member identifications. The computing device additionally transmits each encrypted block with an associated member encryption key and member identification to a key server. As part of the de-duplication process, the content data server stores only one copy of the encrypted data for a particular associated keyed hash, and the key server similarly associates a single member encryption key with the keyed hash. To retrieve the file, the computing device receives the encrypted blocks with their associated keyed hashes and member identifications from the content data server and receives the corresponding member decryption key from the key server. The computing device decrypts each block using the member decryption keys and combines to blocks to generate the file.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Alex Nayshtut, Omer Ben-Shalom, Terry H. Yoshii
  • Patent number: 10379761
    Abstract: According to certain aspects, a system can include a client computing device configured to: in response to user interaction, store an identifier associated with a first tag in association with a first file; and in response to instructions to perform a secondary copy operation, forward the first file, a second file, and the identifier associated with the first tag. The system may also include a secondary storage controller computer(s) configured to: based on a review of the identifier associated with the first tag, identify the first file as having been tagged with the first tag; electronically obtain rules associated with the first tag; perform on the first file at least a first secondary storage operation specified by the rules associated with the first tag; and perform on the second file at least a second secondary storage operation, wherein the first and second secondary storage operations are different.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 13, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Manas Bhikchand Mutha, Pavan Kumar Reddy Bedadala, Vinit Dilip Dhatrak, Christopher A. Alonzo
  • Patent number: 10346302
    Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 10303365
    Abstract: Fingerprints of data portions are distributed in a balanced manner across active controllers of a data storage system, and may be done so in such a manner that, when a new active controller is added to the system, fingerprint ownership and movement between pre-existing active controllers, and active controllers overall, is minimized When a new active controller is added to the system and fingerprints are redistributed, no fingerprint ownership may be re-assigned between pre-existing active controllers and no fingerprints may be moved between pre-existing active controllers, for example, between local memories of the active controller.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: May 28, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Peng Wu, Bin Dai, Rong Yu
  • Patent number: 10303466
    Abstract: A technology is described for embedding a semantic annotation in operation code. An example method may include creating an executable package file that includes operation code obtained from a source executable package file. The operation code may be analyzed to identify a program element included in the operation code that is associated with a semantic annotation. The semantic annotation may then be inserted into the operation code relative to the program element associated with the semantic annotation. The executable package file may be executed, launching a program, and the semantic annotation may be evaluated during execution of the program to retrieve semantic context obtained from the ontological data referenced by the semantic annotation. The semantic context may be processed, causing execution behavior of the program to be analyzed in relation to the program element included in the operation code.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 28, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Alexander Francis Karman, Christian-Damien Jowel Laguerre, Michael Foley, Alexander Scott Boyce
  • Patent number: 10296232
    Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage system is presented. The data storage system includes data storage devices comprising media for storage and retrieval of data. The data storage system includes a host interface configured to receive service level selections indicated by a host system for service level control of the one or more data storage devices. The data storage system includes a storage control system configured to operate the one or more data storage devices according to the service level selections.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 21, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Paul Dunn
  • Patent number: 10284486
    Abstract: In accordance with an embodiment, described herein is a system and method for resource isolation and consumption in an application server environment. The system can provide, at one or more computers, including an application server environment executing thereon, a plurality of resources which can be used within the application server environment, and one or more partitions, wherein each partition provides an administrative and runtime subdivision of a domain. The system can also configure a resource consumption management module to monitor each partition's usage of the plurality of resources. The resource consumption management module can comprise at least one member of the group consisting of resource reservations, resource constraints, and resource notifications.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: May 7, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Sivakumar Thyagarajan, Jagadish Ramu, Kshitiz Saxena, Rahul Srivastava, Lawrence Feigen, Naman Mehta, Prasad Subramanian
  • Patent number: 10275220
    Abstract: An arithmetic processing device includes: a decode circuit configured to decode instructions; an execution control circuit configured to hold the instructions decoded by the decode circuit and to output the held instructions in an executable order; an instruction transfer circuit configured to sequentially transfer the instructions sequentially output by the execution control circuit; an instruction generation circuit configured to output, to the instruction transfer circuit, an individual instruction generated from a combined instruction in a case where one of the instructions transferred by the instruction transfer circuit is the combined instruction obtained by combining individual instructions; and an arithmetic execution circuit configured to execute the individual instruction transferred by the instruction transfer circuit.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Sota Sakashita
  • Patent number: 10268499
    Abstract: The amount of host real storage provided to a large guest storage buffer is controlled. This control is transparent to the guest that owns the buffer and is executing an asynchronous process to update the buffer. The control uses one or more indicators to determine when additional host real storage is to be provided.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Damian L. Osisek, Donald W. Schmidt, Phil C. Yeh
  • Patent number: 10261791
    Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian R. Prasky, David A. Schroter, Chung-Lung K. Shum, Corey C. Stappenbeck
  • Patent number: 10261866
    Abstract: Restoring a data processing system. Files on one or more storage devices of a data processing system are backed up to magnetic tape recording media. Metadata associated with the backed up files is recorded, including magnetic tape identification and tape location for each backed up file. Files on the one or more storage devices are identified that meet a selection policy for files required for rapid restoration of the data processing system. An index list is generated of the identified files and their associated magnetic tape metadata. The index list is sorted by magnetic tape identification and magnetic tape location. In response to a request to restore the data processing system, the identified files on the sorted index list are restored in magnetic tape identification and magnetic tape location sort order. Operation of the restored data processing system is then begun in accordance with the restored files.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, Sosuke Matsui, Tsuyoshi Miyamura, Terue Watanabe, Noriko Yamamoto
  • Patent number: 10254961
    Abstract: A computer-implemented method for managing a memory control unit includes receiving a command at the memory control unit. The command includes a command type that either requires or does not require buffering resources. The method further includes determining, via the memory control unit, a number of available memory tags from a first set of memory tags that are associated with the buffering resources. The method includes determining, via the memory control unit, a number of available memory tags from a second set of memory tags that are not associated with the buffering resources. The method also includes dynamically adjusting, via the memory control unit, assignment of memory tags for use in the second set of memory tags based on the command type, the number of available memory tags from the first set of memory tags, and the number of available memory tags from the second set of memory tags.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glenn D. Gilda, Mark R. Hodges
  • Patent number: 10248353
    Abstract: A method for dynamically freeing storage space in a tiered storage system includes reading attribute values associated with data sets residing on a first storage tier. The method compares characteristics of the data sets to the attribute values to determine which initial data sets qualify to be moved from the first storage tier to a second storage tier. The method further determines whether movement of the initial data sets creates a desired amount of free space on the first storage tier. In the event the movement does not create the desired amount of free space, the method modifies the attribute values, determines which additional data sets qualify to be moved from the first storage tier to the second storage tier, and recalculates the amount of free space that would be generated. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew E. Deiss, David C. Reed, Esteban Rios, Max D. Smith
  • Patent number: 10241724
    Abstract: Generating a virtual storage area network (VSAN) is disclosed. From the perspective of a customer's virtual machine, the VSAN is a logical network of storage devices that provide features that are typically associated with a physical storage access network, such as block level data storage; logical disk arrays; tape libraries; optical jukeboxes; quality of service; disk mirroring, backup and restoration services; archival and retrieval of archived data; data migration from one virtual storage device to another; sharing of data among different virtual machines in a network; and the incorporation of virtual subnetworks.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 26, 2019
    Assignee: Skytap
    Inventors: Bradley M. Schick, Bulat Shelepov, Nikolai Slioussar
  • Patent number: 10235103
    Abstract: A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 19, 2019
    Assignee: XITORE, INC.
    Inventors: Mike Hossein Amidi, Fariborz Frankie Roohparvar
  • Patent number: 10216458
    Abstract: The assignment of data storage resources in a data storage arrangement having a plurality of pools, where each pool includes a plurality of data storage resources arranged in tiers, can be optimized. A gap analysis can be performed for each tier of each pool to determine that tier's excess capacity or demand. The effect of switching data storage resources between tiers of different pools can be modeled to determine the effect of the switch on excess capacity and demand. An improved arrangement of data storage resources in the tiers can be determined that reduces excess capacity and demand, from the modeling of the effect of switching data storage resources between pools. At least one data storage resource can be switched from the tier of the first pool to the tier of the second pool to match the determined improved arrangement of data storage resources.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventor: Pierre Sabloniere
  • Patent number: 10203746
    Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device monitors the thermal profile of the device, where the device executes a plurality of tasks that utilizes a central processing unit of the device. In addition, the plurality of tasks includes a high QoS task and a low QoS process. If the thermal profile of the device exceeds a thermal threshold, the device increases a first CPU throttling for the low QoS task and maintains a second CPU throttling for the high QoS task. The device further executes the low QoS task using the first CPU utilization with the first processing core of the CPU by selectively forcing an idle of the low QoS task during an execution window. In addition, the device executes the high QoS task using the second CPU throttling with a second processing core of the CPU.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 12, 2019
    Assignee: Apple Inc.
    Inventor: Derek R. Kumar
  • Patent number: 10203909
    Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngkwang Yoo, Youngjin Cho, Han-Ju Lee, JinHyeok Choi
  • Patent number: 10191877
    Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Manjari Kulkarni, Akshay G. Pethe, Sean O. Stalley, Mahesh Wagh, Debendra Das Sharma
  • Patent number: 10185653
    Abstract: An integrated system for transactionally managing main memory and storage devices derived from the interfaces and methodologies historically associated with dynamic memory allocation. The methodology has a wide range of applicability including areas such as hardware storage devices (i.e. firmware), operating system internals (i.e. file systems) and end-user software systems.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 22, 2019
    Inventors: Michael Andrew Brian Parkes, Gregory Michael Parkes
  • Patent number: 10168919
    Abstract: A storage apparatus includes a plurality of storage devices, and a control unit for providing a predetermined storage area of the plurality of storage devices to the host computer as a virtual volume group including one or more virtual volumes. The control unit configures one or more data sets having one or more redundancy levels from the plurality of storage devices, provides a storage area of a storage pool including the plurality of data sets to a part of a storage area of the virtual volume, limits a combination of the storage devices configuring the data sets to be assigned to the virtual volume to a given number of combinations of two combinations or more, uniformly distributes the storage devices, and uses a given number of different combinations of the storage devices to be assigned to the virtual volume in units of the virtual volume group.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 1, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Akutsu, Mikio Fukuoka, Eijyu Katsuragi
  • Patent number: 10156996
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, and a controller which writes a first data table including a first data group including a first logical address corresponding to a first physical and a first count value and a second data group including a second logical address corresponding to a second physical address and a second count value, to the volatile memory, reads the first data table when a third logical address is requested to be read, compares the first count value and the second count value with each other, and rewrites the first data group or the second data group to a third data group including a third logical address based on a result of the comparison.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hideki Hayakawa, Takumi Watanabe
  • Patent number: 10152487
    Abstract: A cloud storage system stores data objects from different customers. Each customer has their own encryption key to encrypt the data objects for storage and the key is not shared. To deduplicate the data objects, a set of base fingerprints associated with a set of base data objects is stored. A first fingerprint associated with a data object from a customer is compared with a base fingerprint. The first and base fingerprints are generated by applying an identical fingerprinting algorithm to unencrypted versions of the data objects. If the fingerprints match, the first fingerprint is associated with a base data object corresponding to the matching base fingerprint, and the data object from the customer is not stored. If the fingerprints do not match, the data object from the customer is stored.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 11, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Kedar Shrikrishna Patwardhan, Scott Ogata
  • Patent number: 10153979
    Abstract: Described herein are techniques enabling the prioritization of network traffic in a distributed processing system. Information may be received regarding a plurality of flows, each flow configured to travel from one node to another node in the distributed processing system. Each flow may comprise a segment of at least one job. A priority associated with each flow may be identified. A flow table modification message for each flow may be generated. The flow table modification message can include a timeout value and a priority value consistent with the priority associated with the flow.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 11, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Mark Brian Mozolewski, Carlos Villarreal, Sumanth M Sathyanarayana, Michael R Smith
  • Patent number: 10152248
    Abstract: Systems and methods for efficiently protecting data within a distributed storage system using erasure coding. Unnecessary network traffic can be eliminated by scheduling executing erasure coding tasks on storage nodes that have local copies of data. Encoding may be performed in parallel by multiple nodes to reduce elapsed encoding time.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 11, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Maxim Trusov, Ivan Tchoub, Gregory Skripko, Vladimir Prikhodko
  • Patent number: 10146469
    Abstract: A technique for performing storage tiering in a data storage system includes monitoring storage demands over time to generate a time-based record of storage demands. Based on the time-based record, the data storage system makes predictions of future demand and proactively performs storage tiering based on the predictions. The technique therefore readies the data storage system for predictable changes in demand, such that, should those changes occur, the data storage system is already configured to manage them efficiently.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: December 4, 2018
    Assignee: EMC IP Holding Company, LLC
    Inventors: Aleksei Alexandrovich Polkovnikov, Sergey Alexandrovich Alexeev
  • Patent number: 10133576
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 10133515
    Abstract: Processing within a computing environment that supports pageable guests is facilitated. Processing is facilitated in many ways, including, but not limited to, associating guest and host state information with guest blocks of storage; maintaining the state information in control blocks in host memory; enabling the changing of states; and using the state information in management decisions. In one particular example, the guest state includes an indication of usefulness and importance of memory contents to the guest, and the host state reflects the ease of access to memory contents. The host and guest state information is used in managing memory of the host and/or guests.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ingo Adlung, Jong Hyuk Choi, Hubertus Franke, Lisa C. Heller, William A. Holder, Ray Mansell, Damian L. Osisek, Randall W. Philley, Martin Schwidefsky, Gustav E. Sittmann, III
  • Patent number: 10114748
    Abstract: A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors. The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection. The output atomic response transaction is based on first state information.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 30, 2018
    Assignee: NXP USA, Inc.
    Inventor: Sanjay R. Deshpande
  • Patent number: 10095286
    Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device manages a thermal profile of the device by adjusting a throttling a central processing unit execution of a historically high energy consuming task. In this embodiment, the device monitors thermal level of the thermal profile of the device, the device is executing a plurality of tasks that utilize a plurality of processing cores of the device. If the thermal level of the device exceeds a thermal threshold, the device identifies one of the plurality of tasks as a historically high energy consuming task, and throttles this historically high energy consuming task by setting a force idle execution time for the historically high energy consuming task. The device further executes the plurality of tasks.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 9, 2018
    Assignee: Apple Inc.
    Inventor: Derek R. Kumar
  • Patent number: 10067885
    Abstract: In one embodiment, a computer-implemented method includes inserting a set of accessed objects into a cache, where the set of accessed objects varies in size. An object includes a set of object components, and responsive to receiving a request to access the object, it is determined that the object does not fit into the cache given the set of accessed objects and a total size of the cache. A heuristic algorithm is applied, by a computer processor, to identify in the set of object components one or more object components for insertion into the cache. The heuristic algorithm considers at least a priority of the object compared to priorities of one or more objects in the set of accessed objects. The one or more object components are inserted into the cache.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Avrilia Floratou, Uday B. Kale, Nimrod Megiddo, Fatma Ozcan, Navneet S. Potti
  • Patent number: 10048868
    Abstract: Systems, apparatuses and methods may provide for identifying a first block and a second block, wherein the first block includes a first plurality of cache lines, the second block includes a second plurality of cache lines, and the second block resides in a memory-side cache. Additionally, each cache line in the first plurality of cache lines may be compressed with a corresponding cache line in the second plurality of cache lines to obtain a compressed block that includes a third plurality of cache lines. In one example, the second block is replaced in the memory-side cache with the compressed block if the compressed block satisfies a size condition.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Alaa R. Alameldeen, Glenn J. Hinton, Blaise Fanning, James J. Greensky
  • Patent number: 10049053
    Abstract: An external storage resource pool associated with federated tiered storage is associated with at least one performance tier based on evaluated performance of the external storage resource pool. Performance of the external pool may be evaluated in terms of service level expectations or service level objectives. Workload pattern analysis or performance probability curves may be used to classify the external storage resource pool. Workload distribution may be determined by a margin analysis algorithm that matches workloads and storage resource pool performance characteristics.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 14, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Malak Alshawabkeh, Owen Martin, Xiaomei Liu, Sean Dolan, Hui Wang
  • Patent number: 9986282
    Abstract: Supplemental network services are synchronized with a program using the program's audio signal. A synchronization method employs local caching of portions of a fingerprint database to manage network services for identifying which programs a user's mobile device is exposed to and the timing of events within the program. The system enables background recognition and synchronization of network services in a way that consumes less device power and bandwidth.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 29, 2018
    Assignee: Digimarc Corporation
    Inventors: Brian T. MacIntosh, Tony F. Rodriguez, Ravi K. Sharma, Matthew M. Weaver
  • Patent number: 9965217
    Abstract: According to an aspect of the presently disclosed subject matter, there is provided a system for managing data in a storage system, the system including a storage layer which provides storage resource, and a snapshot layer that includes: a volume-version data structure, a chunk-version data structure and a IO handler.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 8, 2018
    Assignee: Kaminario Technologies Ltd.
    Inventors: Eyal Gordon, Benny Koren, Yedidia Atzmony, Doron Tal, Shachar Fienblit, Ilan Steinberg
  • Patent number: 9959121
    Abstract: A register file bypass controller in communication with a set of one or more bypass registers, the register file bypass controller configured to receive a register file bypass request; determine whether to grant the register file bypass request; determine whether data identified by the register file bypass request is present in the set of one or more bypass registers in response to determining to grant the register file bypass request; determine a selected bypass register in the set of one or more bypass registers in response to determining the data identified by the register file bypass request is not present in the set of one or more bypass registers; determine to store the data identified by the register file bypass request in the selected bypass register; and notify an execution unit to cancel instruction execution associated with the data identified by the register file bypass request.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 1, 2018
    Assignee: International Business Machines Corporation
    Inventors: Christopher M. Abernathy, Mary D. Brown, Sundeep Chadha, Dung Q. Nguyen
  • Patent number: 9933948
    Abstract: According to one embodiment, a tiered storage system includes a tiered storage device and a computer. The computer uses the tiered storage device, and includes a file system and a correction support unit. If an access request from an application is a write request to request overwriting of data, the file system executes a copy-on-write operation. The correction support unit causes the storage controller to carry over an access count manacled by the storage controller and associated with the logical block address of a copy source in the copy-on-write operation, to an access count associated with the logical block address of a copy destination in the copy-on-write operation.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: April 3, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventors: Shouhei Saitou, Shinya Ando
  • Patent number: 9922031
    Abstract: A system and method are provided for processing directory service operations. The system includes a client device communicatively coupled to one or more directory servers. Each directory server includes a communications interface, a storage mechanism, and an evaluation module. According to an exemplary embodiment, the storage mechanism is a non-persistent storage mechanism which increases read and write performance. When a directory server receives a directory service operation, it determines whether it is capable of processing the operation, and if so, processes it with respect to its non-persistent storage mechanism.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: March 20, 2018
    Assignee: CA, Inc.
    Inventors: Richard Hans Harvey, Benjamin Michael Gardiner
  • Patent number: 9892039
    Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 13, 2018
    Assignee: Oracle International Corporation
    Inventors: Mark Luttrell, David Smentek, Ramaswamy Sivaramakrishnan, Serena Leung
  • Patent number: 9778845
    Abstract: Disclosed herein is a file management system that includes an unformatted raw data area storing a plurality of raw data files at respective locations within the unformatted raw data area. The storage medium also includes a formatted partitioned area that includes a plurality of partitions each associated with a different file system. Each partition includes a plurality of metadata files each corresponding with one of the plurality of raw data files. Each metadata file includes metadata regarding the corresponding one of the plurality of raw data files.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: October 3, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhang Yang, Wang Hongming, Tatsuya Hirai
  • Patent number: 9767025
    Abstract: Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to reduce stalls during write operations. The WDI state is a dataless state with guaranteed write permissions. When a first processor of the multiprocessor system makes a write request for a first cache entry of a first cache, the WDI state associated with the first cache entry includes write permissions for the write to directly proceed to one or more higher levels of memory in the shared memory, such that delays associated with obtaining write permissions is reduced at the first cache. The WDI state is treated as an invalid state for a read request to the first cache entry by the first processor.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Dana M. Vantrease
  • Patent number: 9753862
    Abstract: A data processing system includes an upper level cache memory and a lower level cache memory employing different replacement policies. The lower level cache memory provides a respective one of a plurality of counters for each of a plurality of cache lines in a particular congruence class. The lower level cache memory initializes a counter value for a cache line in the particular congruence class that was castout from the upper level cache memory based on an indication of whether the cache line was accessed in the upper level cache memory following installation in the upper level cache memory. The lower level cache memory selects a victim cache line from among the plurality of cache lines in the particular congruence class for eviction from the lower level cache memory by reference to counter values of the plurality of counters.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bernard C. Drerup, Guy L. Guthrie, Jeffrey A. Stuecheli, Phillip G. Williams
  • Patent number: 9749419
    Abstract: A method includes sending a set of check request messages to a set of storage units. A first check request message of the set of check request messages includes a first group of slice names that includes a first slice name from each of a plurality of sets of slice names, and the plurality of sets of slices names corresponds to a plurality of sets of encoded data slices. The method further includes receiving, by a first storage unit, the first check request message, determining a first group of slice information, and sending first check response message, where the first check response message includes the first group of slice information. The method further includes interpreting the first check response message in light of the first group of slice names to identify one or more encoded data slices of the plurality of sets of encoded data slices in need of rebuilding.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch, Zachary J. Mark, Ilya Volvovski, Greg Dhuse
  • Patent number: 9740565
    Abstract: A request is received to determine a consistent point of data stored in a file system of a storage system having storage units. In response to the request, a prime dependency list is retrieved from a first prime segment stored in a first storage unit, the prime dependency list including information identifying at least a second prime segment stored in a second storage unit. The first and second prime segments are identified by a first prime segment identifier (ID) and a second prime segment ID, respectively, which collectively identify a prime representing a first consistent view of the file system. The consistent point of data is determined based the prime segments listed in the prime dependency list, where the consistent point of data represents a file system state at a point in time for restoration of the file system back to a prior known state.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 22, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Soumyadeb Mitra, Windsor W. Hsu
  • Patent number: 9728080
    Abstract: A personal digital key (e.g., which can be carried by a human) contains a memory having different service blocks. Each service block is accessible by a corresponding service block access key. As the personal digital key (PDK) moves around, it is detected by sensors. The sensors report position data, thus enabling location tracking of the PDK. The sensors also provide a data path to various applications. An application that has access to a service block access key can therefore access the corresponding service block on the PDK. The sensors themselves may also contain service block access keys.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: August 8, 2017
    Assignee: Proxense, LLC
    Inventors: David L. Brown, John J. Giobbi
  • Patent number: 9728270
    Abstract: A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 8, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Susumu Takahashi
  • Patent number: 9727263
    Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 8, 2017
    Assignee: VIOLIN MEMORY, INC.
    Inventor: Jon C. R. Bennett
  • Patent number: 9720831
    Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 1, 2017
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah