Caching Patents (Class 711/118)
  • Patent number: 12026093
    Abstract: A data storage system has a CPU data bus for reading and writing data to data accelerators. Each data accelerator has a controller which receives the read and write requests and determines whether to read or write a local cache memory in preprocessed form or an attached accelerator memory which has greater size capacity based on entries in an address translation table (ATT) and saves data in a raw unprocessed form. The controller may also include an address translation table for mapping input addresses to memory addresses and indicating the presence of data in preprocessed form.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: July 2, 2024
    Assignee: Ceremorphic, Inc.
    Inventors: Lizy Kurian John, Venkat Mattela, Heonchul Park
  • Patent number: 12013756
    Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala, Nevil Gajera
  • Patent number: 11966333
    Abstract: Systems and methods of the present disclosure enable intelligent dynamic caching of data by accessing an activity history of historical electronic activity data entries associated with a user account, and utilizing a trained entity relevancy machine learning model to predict a degree of relevance of each entity associated with the historical electronic activity data entries in the activity history based at least in part on model parameters and activity attributes of each electronic activity data entry. A set of relevant entities are determined based at least in part on the degree of relevance of each entity. Pre-cached entities are identified based on pre-cached entity data records cached on the user device, and un-cached relevant entities from the set of relevant entities are identified based on the pre-cached entities. The cache on the user device is updated to cache the un-cached entity data records associated with the un-cached relevant entities.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Capital One Services, LLC
    Inventors: Shabnam Kousha, Lin Ni Lisa Cheng, Asher Smith-Rose, Joshua Edwards, Tyler Maiman
  • Patent number: 11947795
    Abstract: A storage system and related method are for operating solid-state storage memory in a storage system. Zones of solid-state storage memory are provided. Each zone includes a portion of the solid-state storage memory. The zone has a data write requirement for the zone for reliability of data reads. The storage system adjusts power loss protection for at least one zone. The adjusting is based on the data write requirement for the zone and responsive to detecting a power loss.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew R. Bernat, Brandon Davis, Mark L. McAuliffe, Zoltan DeWitt, Benjamin Scholbrock, Phillip Hord, Ronald Karr
  • Patent number: 11940909
    Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sriramakrishan Govindarajan, Mihir Narendra Mody, Prithvi Shankar Yeyyadi Anantha
  • Patent number: 11934330
    Abstract: Examples described herein relate to an offload processor to receive data for transmission using a network interface or received in a packet by a network interface. In some examples, the offload processor can include a packet storage controller to determine whether to store data in a buffer of the offload processing device or a system memory after processing by the offload processing device. In some examples, determine whether to store data in a buffer of the offload processor or a system memory is based on one or more of: available buffer space, latency limit associated with the data, priority associated with the data, or available bandwidth through an interface between the buffer and the system memory. In some examples, the offload processor is to receive a descriptor and specify a storage location of data in the descriptor, wherein the storage location is within the buffer or the system memory.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Patrick G. Kutch, Andrey Chilikin
  • Patent number: 11935623
    Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 19, 2024
    Assignee: MONTAGE TECHNOLOGY (KUNSHAN) CO.
    Inventors: Yibo Jiang, Leechung Yiu, Christopher Cox, Robert Xi Jin, Lizhi Jin, Leonard Datus
  • Patent number: 11914906
    Abstract: Methods related to pre-processing a print job are disclosed. In an example method thereof, it is determined whether a document file is loaded in an application for the print job. Identifying information for the document file is retrieved. A data set obtained from the identifying information is sent to a print manager. A print history for the document file is updated responsive to the data set. The print job includes: pre-rendering of the document file into a document image; and caching of the document image. Print settings of the print job are associated with the document file. The print settings are tracked to provide criteria data to identify frequency of use of the document file.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: February 27, 2024
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Neil-Paul Payoyo Bermundo, Mohamed Al Sayed Mostafa
  • Patent number: 11916787
    Abstract: A system, process, and computer-readable medium for updating an application cache using a stream listening service is described. A stream listening service may monitor one or more data streams for content relating to a user. The stream listening service may forward the content along with time-to-live values to an application cache. A user may use an application to obtain information regarding the user's account, where the application obtains information from a data store and/or cached information from the application cache. The stream listening service, by forwarding current account information, obtained from listening to one or more streams, to the application cache, reduces traffic at the data store by providing current information from the data stream to the application cache.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Capital One Services, LLC
    Inventors: Prateek Gupta, Samuel Wu, Zachary Wyman, Ramiro Ordonez
  • Patent number: 11880262
    Abstract: Power consumption can be reduced by preventing a memory image from being destaged to a nonvolatile memory device. For example, a system can determine, subsequent to a computing device being in a first power mode and having a memory image stored in a first nonvolatile memory device that performs a caching function, that the computing device is in a second power mode that is a higher power mode than the first power mode. The system can, in response to determining that the computing device is in the second power mode, generate a first command to store the memory image in a volatile memory device and prevent the memory image from being stored in a second nonvolatile memory device. The system can, in response to generating the first command, store the memory image in the volatile memory device.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: January 23, 2024
    Assignee: RED HAT, INC.
    Inventors: Gabriel BenHanokh, Adam Kupczyk
  • Patent number: 11868872
    Abstract: In one example, an apparatus comprises: a direct memory access (DMA) descriptor queue that stores DMA descriptors, each DMA descriptor including an indirect address; an address translation table that stores an address mapping between indirect addresses and physical addresses; and a DMA engine configured to: fetch a DMA descriptor from the DMA descriptor queue to the address translation table to translate a first indirect address of the DMA descriptor to a first physical address based on the address mapping, and perform a DMA operation based on executing the DMA descriptor to transfer data to or from the first physical address.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 9, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Ilya Minkin, Ron Diamant, Kun Xu
  • Patent number: 11860783
    Abstract: Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, Yevgeniy Bak, Lisa Ru-feng Hsu
  • Patent number: 11836092
    Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: December 5, 2023
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Bo Fu, Chi-Chun Lai, Jie Chen, Dishi Lai, Jian Wu, Cheng-Yun Hsu, Qian Cheng
  • Patent number: 11829292
    Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: November 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Norris Geng, Richard Senior, Gurvinder Singh Chhabra, Kan Wang
  • Patent number: 11775046
    Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 3, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Oluleye Olorode, Mehrdad Nourani
  • Patent number: 11726704
    Abstract: A solid-state drive having an integrated circuit comprising a controller that is configured to determine, for data transferred between a host interface of the integrated circuit and nonvolatile semiconductor storage device interface of the integrated circuit, the availability of an internal buffer of the integrated circuit to transparently accumulate the transferred data, and (i) if the internal buffer is available, accumulate the data from target nonvolatile semiconductor storage devices or the host in the internal buffer, or (ii) if the internal buffer is not available, accumulate the data unit from the target nonvolatile semiconductor storage devices or the host in an external buffer communicatively coupled to the controller, wherein the external buffer is external to the integrated circuit. The controller then provides the accumulated data to the respective interfaces to furnish a read or write request from the host.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventors: Nigel Horspool, Julien Margetts
  • Patent number: 11726783
    Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marko Scrbak, Mahzabeen Islam, John Kalamatianos, Jagadish B. Kotra
  • Patent number: 11720479
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: August 8, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 11720499
    Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 8, 2023
    Assignees: Advanced Micro Devices, Inc., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Fataneh Ghodrat, Stephen W. Somogyi, Zhenhong Liu
  • Patent number: 11709636
    Abstract: Nonsequential readahead for deep learning training that includes: receiving an indication of a list of batch storage locations for a batch of data objects; prefetching, for each storage location in the list of batch storage locations, storage content corresponding to the batch of data objects; and storing the storage content corresponding to the batch of data objects within a cache accessible to an artificial intelligence workflow.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: July 25, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Emily Potyraj, Bennett Amodio
  • Patent number: 11687461
    Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: June 27, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Norris Geng, Richard Senior, Gurvinder Singh Chhabra, Kan Wang
  • Patent number: 11687456
    Abstract: An electronic device that handles memory accesses includes a memory and a processor that supports a plurality of streams. The processor acquires a graph that includes paths of operations in a set of operations for processing instances of data through a model, each path of operations including a separate sequence of operations from the set of operations that is to be executed using a respective stream from among the plurality of streams. The processor then identifies concurrent paths in the graph, the concurrent paths being paths of operations between split points at which two or more paths of operations diverge and merge points at which the two or more paths of operations merge. The processor next executes operations in each of the concurrent paths using a respective stream, the executing including using memory coloring for handling memory accesses in the memory for the operations in each concurrent path.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 27, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mei Ye
  • Patent number: 11681621
    Abstract: Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Arm Limited
    Inventor: Alexander Klimov
  • Patent number: 11675527
    Abstract: A memory system may include: a nonvolatile memory device suitable for storing user data and meta data of the user data; and a controller suitable for uploading at least some of the meta data to a host. When the size of a free space of a storage space of the host, allocated to store the uploaded meta data, is equal to or less than a preset value, the controller may upload hot meta data to the host according to the number of normal read requests received from the host and the ratio of the normal read requests.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 13, 2023
    Assignee: SK hynix Inc.
    Inventor: Kwang Su Kim
  • Patent number: 11669867
    Abstract: A mobile terminal including: a memory having a plurality of applications stored therein; an application management module configured to receive application information corresponding to the respective applications, and generate status information of the applications, corresponding to the application information; and a controller configured to determine execution history information of the applications through the status information provided from the application management module, wherein the application management module includes: an application information collection unit configured to collect cache data size information of the respective applications at preset time intervals; and a comparison unit configured to generate the status information of the applications by comparing the cache data size information of the applications, collected by the application information collection unit, to reference values corresponding to the respective applications.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 6, 2023
    Assignee: NHN Corporation
    Inventors: Daebeom Lee, Joon Sung Park, Joon Ho Lee, Donghun Kwon, Jun Sung Kim
  • Patent number: 11663131
    Abstract: An operating method of a system-on-chip includes outputting a prefetch command in response to an update of mapping information on a first read target address, the update occurring in a first translation lookaside buffer storing first mapping information of a second address with respect to a first address, and storing, in response to the prefetch command, in a second translation lookaside buffer, second mapping information of a third address with respect to at least some second addresses of an address block including a second read target address.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: May 30, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seongmin Jo, Youngseok Kim, Chunghwan You, Wooil Kim
  • Patent number: 11663138
    Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 30, 2023
    Assignee: Rambus Inc.
    Inventors: Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
  • Patent number: 11630775
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a platform update request to update data item information associated with a first version of a data item cached in a shared cache memory. The embodiment may further operate by transmitting a cache update request to update the data item information of the first version of the data item cached in the shared cache memory, and isolating the first version of the data item cached in the shared cache memory based on a collection of version specific identifiers and a version agnostic identifier associated with the data item.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 18, 2023
    Assignee: Roku, Inc.
    Inventor: Bill Ataras
  • Patent number: 11625326
    Abstract: In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: April 11, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Frank R. Dropps
  • Patent number: 11609855
    Abstract: A processing device identifies a portion of data in a cache memory to be written to a managed unit of a separate memory device and determines, based on respective memory addresses, whether an additional portion of data associated with the managed unit is stored in the cache memory. The processing device further generates a bit mask identifying a first location and a second location in the managed unit, wherein the first location is associated with the portion of data and the second location is associated with the additional portion of data, and performs, based on the bit mask, a read-modify-write operation to write the portion of data to the first location in the managed unit of the separate memory device and the additional portion of data to the second location in the managed unit of the separate memory device.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu
  • Patent number: 11599415
    Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: March 7, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
  • Patent number: 11550728
    Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 10, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Derrick Allen Aguren, Eric H. Van Tassell, Gabriel H. Loh, Jay Fleischman
  • Patent number: 11537530
    Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 27, 2022
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Bo Fu, Chi-Chun Lai, Jie Chen, Dishi Lai, Jian Wu, Cheng-Yun Hsu, Qian Cheng
  • Patent number: 11537328
    Abstract: An apparatus and a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: December 27, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Wei Wu
  • Patent number: 11537567
    Abstract: A database management system for controlling prioritized transactions, comprising: a processor adapted to: receive from a client module a request to write into a database item as part of a high-priority transaction; check a lock status and an injection status of the database item; when the lock status of the database item includes a lock owned by a low-priority transaction and the injection status is not-injected status: change the injection status of the database item to injected status; copy current content of the database item to an undo buffer of the low-priority transaction; and write into a storage engine of the database item.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 27, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: David Dominguez
  • Patent number: 11526456
    Abstract: A method and a system for filtering process I/O operations are provided herein. The system may include: a memory component configured to store computer implementable instructions; and, a processor configured to implement the computer implementable instructions, such that the system is arranged to: determine that a process is queued for initiation on the system; correlate the process with one or more predefined policies; and filter the process by blocking or permitting the process from completing I.O operations on the system according to the one or more predefined policies, wherein the computer implementable instructions are implemented in a kernel-mode of the system.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: December 13, 2022
    Assignee: CYNET SECURITY LTD
    Inventors: Eyal Gruner, Aviad Hasnis, Mathieu Wolf, Igor Lahav, Avi Cashingad, Tomer Gavish
  • Patent number: 11526448
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Zhe Wang, Alaa R. Alameldeen, Yi Zou, Gordon King
  • Patent number: 11521294
    Abstract: A mechanism is described for facilitating dynamic merging of atomic operations in computing devices. A method of embodiments, as described herein, includes facilitating detecting atomic messages and a plurality of slot addresses. The method further includes comparing one or more slot addresses of the plurality of slot addresses with other slot addresses of the plurality of slot addresses to seek one or more matched slot addresses, where the one or more matched slot addresses are merged into one or more merged groups. The method may further include generating one or more merged atomic operations based on and corresponding to the one or more merged groups.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 6, 2022
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Altug Koker, Abhishek R. Appu, Balaji Vembu
  • Patent number: 11513969
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. An example method includes receiving a request to store data in a persistent memory device and a non-persistent memory device via an input/output (I/O) device; redirecting the request to store the data to logic circuitry in response to determining that the request corresponds to performance of a hierarchical memory operation; storing in a base address register associated with the logic circuitry, logical address information corresponding to the data responsive to receipt of the redirected request; asserting, by the logic circuitry, an interrupt signal on a hypervisor, the interrupt signal indicative of initiation of an operation to be performed by the hypervisor to control access to the data by the logic circuitry; and writing, based at least in part, on receipt of the redirected request, the data to the persistent memory device and the non-persistent memory device substantially concurrently.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Vijay S. Ramesh
  • Patent number: 11500777
    Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: November 15, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Oluleye Olorode, Ramakrishnan Venkatasubramanian
  • Patent number: 11494314
    Abstract: Systems, apparatuses, and methods may provide for an eventually-consistent distributed caching mechanism for database systems. As an example, the system may include a recently updated objects (RUO) manager, which may store object identifiers of recently updated objects and RUO time-to-live values of the object identifiers. As servers read objects from the cache or write objects into the cache, the servers may also check the RUO manager to determine if the object has been updated recently enough to be at risk of being stale or outdated. If so, the servers may invalidate the object stored at the cache as it may be stale, which results in eventual consistency across the distributed database system.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: November 8, 2022
    Assignee: Comcast Cable Communications, LLC
    Inventors: Christopher Orogvany, Mark Perry, Bradley W. Jacobs
  • Patent number: 11487653
    Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Qing Liang
  • Patent number: 11487660
    Abstract: A storage device communicates with a host including a host memory. The storage device includes a semiconductor memory device and a device memory. The semiconductor memory device includes a plurality of non-volatile memory cells. The device memory stores validity information of host performance booster (HPB) sub-regions included in each of HPB regions cached in the host memory. The storage device determines to deactivate at least one HPB region among the HPB regions cached in the host memory based on the validity information included in the device memory, and transfers a message recommending to deactivate the determined HPB region to the host.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hoon Seok
  • Patent number: 11467983
    Abstract: Access control request parameter interleaving may be implemented that supports user-configurable and host-configurable processing stages. A request may be received and evaluated to determine whether user-configured interleaving, host-configured interleaving, or both user-interleaving and host-interleaving are applied. For applied interleaving, two different portions of a request parameter may be swapped.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 11, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A Volpe, Mark Banse
  • Patent number: 11470131
    Abstract: Executable code comprising a local file system is stored at a collaboration system server for downloading. The remote collaboration system responds to a message from a user device to download the local file system. The local file system to be downloaded is configured to operate on the user device so as to issue requests from the user device to perform an initial access to server-side collaboration data. The collaboration system responds to such requests by predicting interests of the user, which predictions are used to retrieve additional server-side collaboration data. The additional server-side collaboration data is sent to the user device and stored on the user device in an area for locally-stored collaboration system information. The user provides search terms for searching the locally-stored collaboration system information, and results are displayed on the user device. The results are displayed without the need to perform additional communications with remote collaboration system.
    Type: Grant
    Filed: July 7, 2018
    Date of Patent: October 11, 2022
    Assignee: Box, Inc.
    Inventors: Advait Karande, Tanooj Luthra, Ritik Malhotra
  • Patent number: 11456972
    Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 27, 2022
    Assignee: INTEL CORPORATION
    Inventors: Keith Underwood, Karl Brummel, John Greth
  • Patent number: 11436325
    Abstract: Provided is an analysis apparatus including a first storage device configured to store data, and a processing circuitry that is configured to control the own apparatus to function as: a dispatcher that is communicably connected to an analysis target device that performs operational processing by use of a processor and a memory unit, and generates collection target data for reproducing at least part of a state of the operational processing in the analysis target device, in accordance with data being transmitted and received between the processor and the memory unit; a data mapper that assigns, to one or more areas included in the collection target data, tag information for identifying the area; and a data writer that saves the one or more areas into the first storage device in accordance with a first policy defining a procedure of saving the collection target data into the first storage device.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 6, 2022
    Assignee: NEC CORPORATION
    Inventors: Masato Yamane, Yuki Ashino, Yoichiro Morita, Masafumi Watanabe
  • Patent number: 11429548
    Abstract: Methods, systems, and computer program products for high-performance cluster computing. Multiple components are operatively interconnected to carry out operations for high-performance RDMA I/O transfers over an RDMA NIC. A virtual machine of a virtualization environment initiates a first I/O call to an HCI storage pool controller using RDMA. Responsive to the first I/O call, a second I/O call is initiated from the HCI storage pool controller to a storage device of an HCI storage pool. The first I/O call to the HCI storage pool controller is implemented through a first virtual function of an RDMA NIC that is exposed in the user space of the virtualization environment. Prior to the first RDMA I/O call, a contiguous unit of memory to use in an RDMA I/O transfer is registered with the RDMA NIC. The contiguous unit of memory comprises memory that is registered using non-RDMA paths such as TCP or iSCSI.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: August 30, 2022
    Inventors: Hema Venkataramani, Felipe Franciosi, Gokul Kannan, Sreejith Mohanan, Alok Nemchand Kataria, Raphael Shai Norwitz
  • Patent number: 11429942
    Abstract: A method includes receiving a communication identifying a remote database and a first value stored in the remote database that is being transferred to a first entity by a second entity. That first value is capable of being modified by the second entity. Modification of the first value stored in the remote database by the second entity is prevented by identifying an application programming interface allowing operations to be performed on the remote database, and using that API to transfer the first value so as to be associated with one or more other identifiers unknown to the second entity. After modification of the first value stored by the second entity is prevented, a transfer of a second value to a database record associated with the second entity is triggered. Related systems and applications of the method and those systems are also disclosed.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 30, 2022
    Assignee: The Toronto-Dominion Bank
    Inventor: Michael Pronski
  • Patent number: 11429525
    Abstract: In various embodiments, a predictive assignment application computes a forecasted amount of processor use for each workload included in a set of workloads using a trained machine-learning model. Based on the forecasted amounts of processor use, the predictive assignment application computes a performance cost estimate associated with an estimated level of cache interference arising from executing the set of workloads on a set of processors. Subsequently, the predictive assignment application determines processor assignment(s) based on the performance cost estimate. At least one processor included in the set of processors is subsequently configured to execute at least a portion of a first workload that is included in the set of workloads based on the processor assignment(s).
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 30, 2022
    Assignee: NETFLIX, INC.
    Inventors: Benoit Rostykus, Gabriel Hartmann