Caching Patents (Class 711/118)
  • Patent number: 11403222
    Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: August 2, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai
  • Patent number: 11403176
    Abstract: A system, method and apparatus for storing metadata in a metadata store in a robust and efficient manner including receiving a request from a client to perform a data transaction, updating a key-value pair in a metadata store based on the request, entering the data transaction in a transaction log, updating a read cache with the key-value pair, and replicating the last transaction log entry in at least one other storage node in the metadata store.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Frederik Jacqueline Luc De Schrijver, Joris Custers, Carl Rene D'Halluin
  • Patent number: 11403225
    Abstract: A prefetcher, an operating method of the prefetcher, and a processor including the prefetcher are provided. The prefetcher includes a prefetch address generating circuit, an address tracking circuit, and an offset control circuit. The prefetch address generating circuit generates a prefetch address based on first prefetch information and an offset amount. The address tracking circuit stores the prefetch address and a plurality of historical prefetch addresses. When receiving an access address, the offset control circuit updates the offset amount based on second prefetch information, the access address, the prefetch address, and the historical prefetch addresses, and provides the prefetch address generating circuit with the updated offset amount.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: August 2, 2022
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Xianpei Zheng, Zhongmin Chen, Qi Li
  • Patent number: 11392503
    Abstract: An apparatus and method for tagged memory management.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 19, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ron Gabor, Raanan Sade, Igor Yanover, Assaf Zaltsman, Tomer Stark
  • Patent number: 11392382
    Abstract: Micro-operations (?ops) are allocated into a ?op cache by dividing, by a micro branch target buffer (?BTB), instructions into a first basic block in which the instructions are executed by a processing device and the first basic block corresponds to an edge of the instructions being executed by the processing device. The ?BTB allocates the first basic block to an inverted basic block queue (IBBQ) and the IBBQ determines that the first basic block fits into the ?op cache. The IBBQ allocates the first basic block to the ?op cache based on a number of times the edge of the instructions corresponding to the first basic block is repeatedly executed by the processing device.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 19, 2022
    Inventor: James David Dundas
  • Patent number: 11392515
    Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dionisio Minopoli, Daniele Balluchi
  • Patent number: 11372830
    Abstract: Various technologies described herein pertain to interactive data splitting. A program for splitting an input column of an input data set into multiple output columns can be synthesized based on input-only examples. The program can further be generated based on various user input; thus, the user input can guide the synthesis of the program. Moreover, the program can be executed on the input data set to split the input column of the input data set into the multiple output columns.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 28, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Mohammad Raza, Sumit Gulwani, Ranvijay Kumar, Euan Peter Garden, Chairy Chiu Ying Cheung, Daniel Galen Simmons
  • Patent number: 11366760
    Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Abdelhakim Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin, Jung Sheng Hoei
  • Patent number: 11360901
    Abstract: Provided are a method and apparatus for managing a page cache for multiple foreground applications. A method of managing a page cache includes identifying an application accessing to data stored in storage; allocating a page used by the application for the accessed data to a page cache; setting a page variable corresponding to a type of the identified application to the allocated page; and managing demoting of the allocated page based on the set page when the allocated page is a demoting target.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: June 14, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Young Ik Eom, Jong Gyu Park
  • Patent number: 11347645
    Abstract: Managing a cache memory in a storage system includes maintaining a queue that stores data indictive of the read requests for a particular logical storage unit of the storage system in an order that the read requests are received by the storage system, receiving a read request for a particular page of the particular logical storage unit, and removing a number of elements in the queue and resizing the queue in response to the queue being full. Managing the cache memory also includes placing data indicative of the read request in the queue, determining a prefetch metric that varies according to a number of adjacent elements in a sorted version of the queue having a difference that is less than a predetermined value and greater than zero, and prefetching a plurality of pages that come after the particular page sequentially if the prefetch metric is greater than a predefined value.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinicius Gottin, Jonas F. Dias, Hugo de Oliveira Barbalho, Romulo D. Pinho, Tiago Calmon
  • Patent number: 11347514
    Abstract: Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 31, 2022
    Assignee: Apple Inc.
    Inventors: Deepak Limaye, Brian R. Mestan, Gideon N. Levinsky
  • Patent number: 11340808
    Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • Patent number: 11340810
    Abstract: Methods and apparatus for managing and optimizing data storage devices that include non-volatile memory (NVM) are described. One such method involves deriving a hint for one or more logical block addresses (LBAs) of a storage device based on information received from a host device and/or physical characteristics of the storage device, such as LBAs that are invalidated together; grouping the LBAs into one or more clusters of LBAs based on the derived hint and a statistical analysis of the physical characteristics of the storage devices; allocating available physical block addresses (PBAs) in the storage device to one of the LBAs based on the one or more clusters of LBAs to achieve optimization of a data storage device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 24, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn, Karin Inbar, Rami Rom, Idan Alrod, Eran Sharon
  • Patent number: 11341066
    Abstract: Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: May 24, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Ho Han, Min-Seok Choi, Young-Su Kwon
  • Patent number: 11335383
    Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11327892
    Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • Patent number: 11321315
    Abstract: This disclosure relates to increasing performance of database queries. A proxy server receives an input query string and a parameter value for first parameter name in the query string. The proxy server determines a second parameter name based on the parameter value and different to the first parameter name. The proxy server then determines an output query string based on the input query string. The output query string comprises a filter clause with a field name and a second field value, the second field value of the output query string being based on the second parameter name. The proxy server finally sends the output query string to a database management system to cause the database management system to execute a database query using an execution plan based on the second parameter name in the output query string.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 3, 2022
    Assignee: WiseTech Global Limited
    Inventor: Brett Anthony Shearer
  • Patent number: 11321233
    Abstract: A multi-chip system and a cache processing method are provided. The multi-chip system includes multiple chips. Each chip includes multiple clusters, a crossbar interface, and a snoop system. Each cluster corresponds to a local cache. The crossbar interface is coupled to the clusters and a crossbar interface of another chip. The snoop system is coupled to the crossbar interface and performs unidirectional transmission with the crossbar interface. The snoop system includes a snoop table module and multiple trackers. The snoop table module includes a shared cache, which records a snoop table. Multiple trackers are coupled to the snoop table module, query the snoop table in the shared cache according to a memory access request initiated by one of clusters, and update the snoop table according to a query result. The snoop table corresponds to a storage structure of the local cache corresponding to the clusters in all chips.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 3, 2022
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Yang Shi, Chen Chen, Weilin Wang, Jiin Lai
  • Patent number: 11321248
    Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: May 3, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson
  • Patent number: 11323414
    Abstract: A Domain Name System (DNS) resolver node receives a first DNS query from a first client device. The resolver node determines that it cannot answer the query using its local cache so it performs a recursive query to obtain the answer. The answer is sent to the first client and stored in its local cache. The resolver node further transmits the answer to multiple other resolver nodes that are part of the same cluster so they can update their respective local cache with the information. Upon receiving a message from another resolver node that includes a set of resource record(s) not in its local cache, the resolver node stores that set of resource record(s) in its local cache so that it can locally answer subsequent requests for those resource record(s) locally.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: May 3, 2022
    Assignee: CLOUDFLARE, INC.
    Inventors: Marek Vavrusa, Anbang Wen
  • Patent number: 11310652
    Abstract: The invention relates to a system comprising a mobile device (1), a device (13b) for transmitting information, a device (15) hosting a device registry (14) and a wireless device (3a). The mobile device (1) comprises a receiver, a transmitter, storage means and a processor.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: April 19, 2022
    Assignees: Koninklijke KPN N.V., Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek TNO
    Inventors: Antonius Norp, José Almodóvar Chico, Michael Schenk, Sander de Kievit
  • Patent number: 11301499
    Abstract: Systems and methods are provided for providing an object platform for datasets A definition of an object may be obtained. The object may be associated with information stored in one or more datasets. The information may be determined based at least in part on the definition of the object. The object may be stored in a cache such that the information associated with the object is also stored in the cache. One or more interfaces through which requests to perform one or more operations on the object are able to be submitted may be provided.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 12, 2022
    Assignee: Palantir Technologies Inc.
    Inventors: Rick Ducott, Aakash Goenka, Bianca Rahill-Marier, Tao Wei, Diogo Bonfim Moraes Morant De Holanda, Jack Grossman, Francis Screene, Subbanarasimhiah Harish, Jim Inoue, Jeremy Kong, Mark Elliot, Myles Scolnick, Quentin Spencer-Harper, Richard Niemi, Ragnar Vorel, Thomas Mcintyre, Thomas Powell, Andy Chen
  • Patent number: 11297670
    Abstract: Methods performed by a first sink device, a source device, or a second sink device. The first sink device is connected to a source device via a first communication link and a second sink device via a second communication link, wherein the second sink device is configured to eavesdrop on communications between the first sink device and the source device on the first communication link. The methods include determining an occurrence of a trigger event and modifying an operation of at least one of the first sink device, the second sink device or the source device based at least on the trigger event occurring.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 5, 2022
    Assignee: Apple Inc.
    Inventors: Lei Li, Xiaojun Chen, Camille Chen, Siegfried Lehmann, Vusthla Sunil Reddy, Peter M. Agboh
  • Patent number: 11294816
    Abstract: Techniques are described herein for reducing the number of redundant evaluations that occur when an expression is evaluated against an encoded column vector by caching results of expression evaluations. When executing a query that includes an expression that references columns for which dictionary-encoded column vectors exist, the database server performs a cost-based analysis to determine which expressions (or sub-expressions) would benefit from caching the expression's evaluation result. For each such expression, the database server performs the necessary computations and caches the results for each of the possible distinct input values. When evaluating an expression for a row with a particular set of input codes, a look-up is performed based on the input code combination to retrieve the pre-computed results of that evaluation from the cache.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: April 5, 2022
    Assignee: Oracle International Corporation
    Inventors: Shasank K. Chavan, Dina Thomas, Ajit Mylavarapu, Prashant Gaharwar, Dennis Lui, Sheldon A. K. Lewis
  • Patent number: 11288198
    Abstract: A system includes a line cache, a memory device, and a processing device to execute firmware to detect that a received event is located in an events list, wherein events stored in the events list are associated with critical functions that occur no more than once per a threshold number of days and time out after between 15 microseconds and a predetermined number of hundreds of seconds. The firmware is further to enable access to the line cache and execute a critical function associated with the received event out of an always-loaded area of the line cache.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Meng Wei, Shi Bo Zhang, Tao Xiong
  • Patent number: 11290559
    Abstract: Methods, systems, and devices may be used to support freshness-based processing of requests. Freshness-based processing may involve the service layer examining the age of stored content (e.g., resource representation) that it hosts and determining whether it is fresh enough to satisfy a retrieve or discovery request with a specified freshness requirement. If not fresh, the service layer can contact an application to refresh the content. In addition, freshness-based processing can also involve the service layer examining the semantic state of a command oriented update request to determine whether its state is fresh or not with respect to prior commands processed by the service layer. For example, the service layer may compare stored content associated with controlling a particular application (e.g. door is locked) and against the semantic content of an update request (e.g., unlock door) to determine whether it is the same (e.g., stale) or not (e.g., fresh).
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: March 29, 2022
    Assignee: Convida Wireless, LLC
    Inventors: Dale N. Seed, Gregory S. Sternberg, Quang Ly, Rocco Di Girolamo, Shamim Akbar Rahman, William Robert Flynn, IV, Catalina Mihaela Mladin, Zhuo Chen
  • Patent number: 11277350
    Abstract: Particular embodiments described herein provide for a system for enabling the communication of a large message using multiple network interface controllers (NICs). The system can be configured to determine that a message to communicate to a receiver over a network is above a threshold, determine a plurality of NICs to be used to communicate the message, create a manifest that includes an identifier of each of the plurality of NICs, and communicate the manifest to the receiver using a multi-unit message. In an example, the multi-unit message is communicated using a PUT command and the receiver can analyze the manifest and use a GET command to pull the message from the plurality of NICs.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Murty, Keith D. Underwood, Ravindra Babu Ganapathi, Andrew Friedley, Vignesh Trichy Ravi
  • Patent number: 11269782
    Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Kun Tian, Xiao Zheng, Ashok Raj, Sanjay Kumar, Rajesh Sankaran
  • Patent number: 11269724
    Abstract: A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-Wook Park
  • Patent number: 11263314
    Abstract: The disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring a first access record of the processor to a first memory during a running process, the first access record including reading-operation information; acquiring a second access record of a checking device to a second memory during a replay process, the second access record including first reading-operation information, the first reading-operation information being reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation, and determining, based on the first access record and the second access record, whether or not the processor reads during the running process a memory address that is not any one of addresses included in the second access record.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 1, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Leibo Liu, Ao Luo, Shouyi Yin, Shaojun Wei
  • Patent number: 11256630
    Abstract: This application discloses a cache address mapping method and a related device. The method includes: obtaining a binary file, the binary file including a first hot section; obtaining alignment information of a second hot section, the second hot section is a hot section that has been loaded into a cache, and the alignment information includes a set index of a last cache set occupied by the second hot section; and performing an offset operation on the first hot section based on the alignment information. According to embodiments of the present invention, a problem of a conflict miss of a cache in an N-way set associative structure can be resolved without increasing physical hardware overheads, thereby improving a cache hit rate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 22, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yandong Lv, Jianjiang Ceng
  • Patent number: 11249646
    Abstract: A plurality of pieces of write data are aggregated on a buffer to obtain a segment where the segment exceeds a smallest write size supported by storage. An address on the storage is determined for the segment. Location information and identifier(s) associated with the segment are recorded where the location information points to the storage, as opposed to the buffer, while the write data is being aggregated. When the write data has been aggregated into the segment, the segment is written to the storage wherein the location information remains unchanged in response to the writing to the storage.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 15, 2022
    Assignee: OmniTier Storage, Inc.
    Inventors: Derrick Preston Chu, Suneel Indupuru, Daryl Ng
  • Patent number: 11243960
    Abstract: Various embodiments relate generally to data science and data analysis, computer software and systems, and wired and wireless network communications to interface among repositories of disparate datasets and computing machine-based entities configured to access datasets, and, more specifically, to a computing and data storage platform to implement computerized tools to facilitate expedited queries based on query results generated by disparate computing and database architectures, according to at least some examples. For example, a method may include generating multiple results of queries, storing the multiple results of queries in a memory, and linking each of the multiple results of queries to a portion of data stored in a graph. The method can include receiving data representing a query and accessing data representing quiescent data values to form a query result.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 8, 2022
    Assignee: data.world, Inc.
    Inventors: David Lee Griffith, Shad William Reynolds
  • Patent number: 11243892
    Abstract: A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 8, 2022
    Assignee: ARM LTD.
    Inventor: Steven Douglas Krueger
  • Patent number: 11226944
    Abstract: Concepts and technologies are described herein for cache management. In accordance with the concepts and technologies disclosed herein, the server computer can be configured to communicate with a client device configured to execute a cache module to maintain a cache storing data downloaded from and/or uploaded to the server computer by the client device. The server computer can be configured to receive requests for data stored at the server computer. The server computer can be configured to respond to the request with hashes that correspond to the requested data. The client device can search the cache for the hashes, obtain the data from the cache if the hashes are found, and/or download the data from the server computer if the hashes are not found. The client device also can be configured to update the cache upon uploading the data to the server computer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: January 18, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Miko Arnab Sakhya Singha Bose, Simon Clarke, David Charles Oliver, Malgorzata Anna Malaczek
  • Patent number: 11226902
    Abstract: A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Benjamin Herrenschmidt, Cathy May, Bradly G. Frey
  • Patent number: 11222684
    Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
  • Patent number: 11216375
    Abstract: A data caching circuit and method are provided. The circuit is configured to cache data for a feature map calculated by a neural network, wherein a size of a convolution kernel of the neural network is K*K data, and a window corresponding to the convolution kernel slides at a step of S in the feature map, where K is a positive integer and S is a positive integer, the circuit comprising: a cache comprising K caching units, each caching unit being configured to respectively store a plurality of rows of the feature map, the plurality of rows comprising a corresponding row in every K consecutive rows of the feature map.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 4, 2022
    Assignee: Hangzhou Zhicun Intelligent Technology Co., Ltd.
    Inventors: Qilin Zheng, Shaodi Wang
  • Patent number: 11216422
    Abstract: A universal data management interface (UDMI) system includes a processing system generates a visual interface through which a user can access, manage, and manipulate data on plural different types of remote databases. The UDMI connects to multiple standard database management systems and to allow multiple users to access, manage, and manipulate data within each of the multiple standard database management systems. The UDMI also allows multiple virtual databases that reside in a single database to be available as a network service.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 4, 2022
    Assignee: S. AQUA SEMICONDUCTOR, LLC
    Inventor: Jasmin Cosic
  • Patent number: 11216380
    Abstract: Provided is an operation method of a controller which controls a memory device. The operation method may include: determining a caching order of plural pieces of map data included in a request map segment including request map data; requesting the request map segment from the memory device; marking data in a marking region which is determined based on the caching order; caching, in the caching order, the plural pieces of map data read from the memory device; and acquiring the request map data from the cached data, depending on whether the data stored in the marking region is changed.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11210237
    Abstract: Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11210360
    Abstract: Systems and techniques for edge-cache optimization of personalized webpages are described herein. A request may be received for a web page from a content delivery network. Requests may be received for user fragments, page layout fragments, personalization decisions fragments, and page content fragments. Directives may be generated in response to the requests including user fragment directives, page layout fragment directives, user data storage directives, a set of fixed section directives, and a set of personalized section directives. The generated directives may be used to construct content fragment caching directives for the page fragments. The content fragment caching directives are transmitted to the content delivery network to provide cashing instructions for the page fragments.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 28, 2021
    Assignee: BBY SOLUTIONS, INC.
    Inventors: Sean Godinez, Praveen Kotla, David Adolphson
  • Patent number: 11206302
    Abstract: A method includes: receiving a resource acquisition request of a target resource, and calculating resource identification information included in the resource acquisition request by using a first preset algorithm to obtain a target feature index value; if a resource file corresponding to the target feature index value exists locally, feeding back the resource file corresponding to the target feature index value, and if not, transmitting a data acquisition request of a specified segment of the target resource to a resource server of the target resource; receiving data of the specified segment fed back by the resource server, and calculating the data of the specified segment by using a second preset algorithm to obtain a target content index value; and if a resource file corresponding to the target content index value exists locally, feeding back the resource file corresponding to the target content index value, and if not, transmitting the resource acquisition request to the resource server.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 21, 2021
    Assignee: WANGSU SCIENCE & TECHNOLOGY CO., LTD.
    Inventors: Lijuan Chen, Lipeng Wang
  • Patent number: 11201914
    Abstract: A method for processing a super-hot file includes: receiving a download request for a target file sent by a user client, and adding, into the download request, a cache parameter for indicating whether the target file is a super-hot file; matching an identifier of the target file against a super-hot file identifier library, and determining, according to a matching result, whether the target file is a super-hot file; if the target file is a super-hot file, generating a random identification code, and updating the cache parameter to a cache parameter indicating that the target file is a super-hot file; and determining a download server to which the random identification code is mapped, and forwarding the download request including the updated cache parameter to the download server.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 14, 2021
    Assignee: WANGSU SCIENCE & TECHNOLOGY CO., LTD.
    Inventor: Kai Zhang
  • Patent number: 11200180
    Abstract: Embodiments generally relate to handling of NVMe scatter gather list bit bucket transfers by a data storage device. The data storage device transfers the data associated with the bit bucket transfers to a host or to a controller memory buffer of the data storage device. The data storage device can transfer the data associated with the bit bucket transfers to the host by modifying transaction layer packets (TLPs) to indicate to the host to ignore the data payload of the TLPs.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 11200160
    Abstract: A method for adjusting over provisioning space and a flash device are provided. The flash device includes user storage space for storing user data and over provisioning space for garbage collection within the flash device. The flash device receives an operation instruction, and then performs an operation on user data stored in the user storage space based on the operation instruction. Further, the flash device identifies a changed size of user data after performing the operation. Based on the changed size of data, a target adjustment parameter is identified. Further, the flash device adjusts the capacity of the over provisioning space according to the target adjustment parameter. According to the method, the over provisioning ratio can be dynamically adjusted, thereby, a life of the flash device can be prolonged.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: December 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jianhua Zhou, Po Zhang
  • Patent number: 11194512
    Abstract: A data storage device may include: a nonvolatile memory device; and a controller configured to control a read operation of the nonvolatile memory device, wherein the controller includes: a memory configured to store workload pattern information; and a processor configured to check a workload pattern in a first period based on the workload pattern information, and decide on a read mode to be performed in a second period following the first period, according to the workload pattern of the first period.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Gu Kang, Jin Soo Kim
  • Patent number: 11194755
    Abstract: A method for providing multi-tenancy support for RDMA in a system that includes a plurality of physical hosts. Each physical host hosts a set of data compute nodes (DCNs). The method, at an RDMA protocol stack of the first host, receives a packet that includes a request from a first DCN hosted on a first host for RDMA data transfer from a second DCN hosted on a second host. The method sends a set of parameters of an overlay network that are associated with the first DCN to an RDMA physical network interface controller of the first host. The set of parameters are used by the RDMA physical NIC to encapsulate the packet with an RDMA data transfer header and an overlay network header by using the set of parameters of the overlay network to transfer the encapsulated packet to the second physical host using the overlay network.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 7, 2021
    Assignee: NICIRA, INC.
    Inventors: Shoby Cherian, Tanuja Ingale, Raghavendra Subbarao Narahari Venkata
  • Patent number: 11194725
    Abstract: A cache management system includes a sequentiality determination process configured to determine sequentiality profiles of a workload of IO traces as the workload dynamically changes over time. A learning process is trained to learn a correlation between workload sequentiality and cache pollution, and the trained learning process is used to predict cache pollution before the cache starts to experience symptoms of excessive pollution. The predicted pollution value is used by a cache policy adjustment process to change the prefetch policy applied to the cache, to proactively control the manner in which prefetching is used to write data to the cache. Selection of the cache policy is implemented on a per-LUN basis, so that cache performance for each LUN is individually managed by the cache management system.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 7, 2021
    Assignee: Dell Products, L.P.
    Inventors: Rômulo Teixeira de Abreu Pinho, Hugo de Oliveira Barbalho, Vinicius Michel Gottin, Roberto Nery Stelling Neto, Alex Laier Bordignon, Daniel Sadoc Menasché
  • Patent number: 11194696
    Abstract: Recording a trace of code execution using reserved cache lines in a cache. A computing device comprises processing units and a cache. The cache includes a first plurality of cache lines that each comprise an address portion for storing a memory address within the memory device, and a value portion for storing a value associated with the memory address. The cache also includes a second plurality of reserved cache lines that store a plurality of sets of accounting bits. Each set of accounting bits comprises a plurality of accounting bits and is associated with a different cache line in the first cache lines. Each cache line in the second cache lines stores multiple of the sets of accounting bits. Stored control logic uses the plurality of sets of accounting bits in the second cache lines to track trace logging information for the first cache lines.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola