Abstract: A fractional caching method and an adaptive contents transmitting method using the same are provided. The fractional caching method includes the steps of setting up a divided location for dividing a certain object into two parts, receiving an evict request for acquiring a space in the inside of the cache, when the evict request is transmitted, dividing a plurality of objects stored in the cache into a prefix-Object located in the head of the object and a suffix-Object located in the tail of the object from the divided location, and removing only the suffix-Object of each object, wherein the divided location is set up at a size rate that a size of the prefix-Object is in inverse proportion to the number of the destination types.

Abstract: Embodiments of the present invention provide a system that marks cache lines using shared timestamps. During operation, the system starts a transaction for a thread, wherein starting the transaction involves recording the value of an active timestamp and incrementing a transaction or overflow counter (TO_counter) corresponding to the recorded value. The system then places load-marks on cache lines which are loaded during the transaction. While placing the load-marks, the system writes the recorded value into metadata corresponding to the cache lines. Upon completing the transaction for the thread, the system decrements the TO_counter corresponding to the recorded value and resumes non-transactional execution for the thread without removing the load-marks from cache lines which were load-marked during the transaction.

Abstract: A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache directories are substantially equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these separate cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors. The other cache directory retains only addresses, including addresses of lines LRUed out from the first cache directory and the identity of the processor using the data. Thus by this expedient, only the directory known to be backed by system cached data will be evaluated for system cache memory data.

Abstract: A web server and a shared caching server are described for serving dynamic content to users of at least two different types, where the different types of users receive different versions of the dynamic content. A version of the dynamic content includes a validation header, such as an ETag, that stores information indicative of the currency of the dynamic content and information indicative of a user type for which the version of the dynamic content is intended. In response to a user request for the dynamic content, the shared caching server sends a validation request to the web server with the validation header information. The web server determines, based on the user type of the requestor and/or on the currency of the cached dynamic content whether to instruct the shared caching server to send the cached content or to send updated content for serving to the user.

Abstract: Methods and apparatuses enable separate management of shared data structures and shared data objects referenced by the shared data structures. The shared data structures are stored in a first memory, and the shared data structures are separately managed from the referenced shared data objects. The shared data objects can be accessed by the shared data structures via direct and/or indirect reference. A separation agent can detect references to data objects in an application to indicate which data objects are shared and are to be stored in the separate cache.

Abstract: In a multiprocessor non-uniform cache architecture system, multiple CPU cores shares one non-uniform cache that can be partitioned into multiple cache portions with varying access latencies. A placement prediction mechanism predicts whether a cache line should remain in a cache portion or migrate to another cache portion. The prediction mechanism maintains one or more prediction counters for each cache line. A prediction counter can be incremented or decremented by a constant or a variable determined by some runtime information, or set to its maximum or minimum value. An effective placement prediction mechanism can reduce average access latencies without causing cache thrashing among cache portions.

Abstract: A method is provided for optimisation of the management of a server cache for dynamic pages, which may be consulted by client terminals with differing characteristics which requires the provision of discrete versions of a dynamic page in the cache. When a terminal requests a dynamic page, a verification step—for the presence of at least one version of the dynamic page in the cache is carried out, such that if the verification is positive the following complementary steps are carried out: procurement of a set of characteristics specific to the type of client terminal, determination of a subset of necessary characteristics from amongst the specific characteristics for the reproduction of the dynamic page on a client terminal, search, among the version(s) of the dynamic page in the cache for a suitable version using the subset of necessary characteristics and allocation of the suitable version to the client terminal.

Abstract: A storage system includes a storage device, a shared memory, and first and second file server devices that each exclusively manages a respective portion of data stored on the storage device. During operation, the first file server device determines whether the first or second file server device manages data that is subject to the processing of a write command received by the first file server device. When the second file server device manages data that is subject to the processing of the write command, the first file server device transfers only the control data contained in the write command to the second file server device and updates data that is subject to the processing of the write command via the shared memory.

Abstract: A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members and multiple sub-cache memories corresponding to the instruction processing members. Next step is using a first instruction processing member to access a first sub-cache memory. The first instruction processing member will access the rest sub-cache memories when the first instruction processing member does not access the desired data successfully in the first instruction processing member. The first instruction processing member will access the lower level memory unit until the desired data have been accessed, when the first instruction processing member does not access the desired data successfully in the sub-memories. Then, the instruction processing member returns a result.

Abstract: In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is determined which portions of the cache are utilized by the observed process. Utilization of the cache is optimized based on result of the determination of which portions of the cache are utilized by the observed process.

Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

Abstract: In a multi-tenant data sharing environment with shared, customizable data attributes are assigned to requested data and stored in a cache store along with the requested data. For non-customized data designated as system data, one copy is stored in the cache store for use by multiple tenants allowing optimization of memory and performance for each data request/retrieval operation. A “delete sentinel” attribute may be assigned to non-existing data in the cache store enabling notification of requesting tenant(s) without a need to access the tenant data store each time a request for the non-existing data is received.

Abstract: Methods and systems for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores are provided. Embodiments include receiving from a processor core a request to load a cache line in the shared cache; determining whether the shared cache is full; determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.

Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.

Abstract: In a storage system having a first storage control apparatus and a second storage control apparatus, the first storage control apparatus has: a first memory; a second memory; an input/output control unit for data transfer information in the second memory; and a data transfer control unit having a data buffer and a data transfer register for controlling data transfer between the first memory and second storage control apparatus based on the data transfer information read from the second memory and written in the data transfer register. When a second data transfer is controlled while a first data transfer is controlled, the data transfer control unit writes the first data transfer information and data stored in the data buffer into the second memory, reads the second data transfer information from the second memory and writes the second data transfer information into the data transfer register to control the second data transfer.

Abstract: A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back of a specified region can be commanded from a program running on a processor. Programs running on each processor invalidate an input data region of a cache memory with an invalidation command immediately before execution of a program as a processing batch, and write back an output data region of a cache memory to the shared memory with a write back command immediately after execution of a program as a processing batch.

Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.

Abstract: Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread receives a signal from a last thread once the last thread has the reference to the data. The initial thread, in response to the signal, modifies the data and updates changes to the data within the cache and then sends another signal to a next thread, indicating that the next thread may now perform a volatile operation on the data within the cache.

Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize a cache and avoid unnecessary cache thrashing and/or pollution. The color based caching can be monitored to improve memory performance and guarantee Quality-Of-Service of cache utilization.

Abstract: In general, in one aspect, the disclosure describes a method to identify a set of tasks that share data and enqueue the set of tasks with a cluster identification, wherein the cluster identification indicates a cluster of processors that share cache.

Abstract: Systems and methods for partitioning information across multiple storage devices in a web server environment. The system comprises a web server database which includes information related creating a web site. The information is divided into partitions within the database. One of the partitions includes user information and another of the partitions includes content for the web site. Portions of the content for the web site is replicated and maintained within the partition including the user information. Further, a portion of the user information is replicated and maintained in the partition where the content for the web site is maintained. The methods include dividing information into partitions, de-normalizing the received data and replicating the data portions into the various web site locations.

Abstract: One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered.

Abstract: A technique is described for facilitating block level access operations to be performed at a remote volume via a wide area network (WAN). The block level access operations may be initiated by at least one host which is a member of a local area network (LAN). The LAN includes a block cache mechanism configured or designed to cache block data in accordance with a block level protocol. A block level access request is received from a host on the LAN. In response to the block level access request, a portion of block data may be cached in the block cache mechanism using a block level protocol. In at least one implementation, portions of block data in the block cache mechanism may be identified as “dirty” data which has not yet been stored in the remote volume. Block level write operations may be performed over the WAN to cause the identified dirty data in the block cache mechanism to be stored at the remote volume.

Abstract: A cache management system providing improved page latching methodology is described. In one embodiment, for example, a method is described for providing access to data in a multi-threaded computing system, the method comprises steps of: providing a cache containing pages of data in memory of the multi-threaded computing system; associating a latch with each page in the cache to regulate access to the page, the latch allowing multiple threads to share access to the page for read operations and a single thread to obtain exclusive access to the page for write operations; in response to a request from a first thread to read a particular page, determining whether the particular page is in the cache without blocking access by other threads to pages in the cache; if the particular page is in the cache, attempting to obtain the latch for purposes of reading the particular page; and allowing the first thread to read the particular page unless a second thread has latched the particular page on an exclusive basis.

Abstract: A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

Abstract: Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.

Abstract: In a shared memory system, ineffective write operations (“dead stores”) can be handled in a manner to reduce unnecessary consumption of resources. In a shared memory system, when a non-owning processing unit requests data from a shared memory location owned by another processing unit, the memory controller for the shared memory requests a most current copy of the data from the owner processing unit. Instead of the owner processing unit reflexively sending its data to the memory controller, the owner processing unit determines whether the data has been changed, and, if it has not changed, transmits indication of such to the memory controller. Since the data has not changed, then the data at the shared memory location is proper and can be sent to satisfy the requesting processing unit.

Abstract: A system for detecting and breaking up requester starvation, including: a plurality of logic circuits, each of the plurality of logic circuits permitted to access a cache via a plurality of requesters for requesting information from the cache; and a counter for counting a number of times each of the plurality of requestors of each of the plurality of logic circuits has (i) successfully accessed one or more of a plurality of arbitration levels and (ii) has been rejected by a subsequent arbitration level; wherein when the counter reaches a predetermined threshold value, an event is triggered to block a first type of requester from accessing the cache and to permit a second type of requester to access the cache; and wherein the counter is reconfigured to count a predetermined number of cycles before the first type of requester is unblocked from accessing the cache.

Abstract: Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.

Abstract: Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared cache.

Abstract: In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated for holding non-shared data. A non-shared data bank may be designated exclusively for holding non-shared data, so that shared data accesses do not interfere with non-shared accesses to that bank. Also, a shared data bank may be designated exclusively for holding shared data, and one or more banks may be designated for holding both shared and non-shared data. An access control circuit directs shared and non-shared accesses to respective banks based on receiving a shared indication signal in association with the accesses. Further, in one or more embodiments, the access control circuit reconfigures one or more bank designations responsive to a bank configuration signal.

Abstract: A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.

Abstract: An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive signals from the interconnect and to apply the signals from the interconnect to affect the content of the cache, and to receive signals from the mass storage and to apply the signals from the mass storage to affect the content of the cache. The content of the mass storage and cache of a particular node may also be provided to other nodes of the system, via the interconnect.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for migrating a persistent cache. A priming request is received at an intermediary to prime the persistent cache of a first partition. Data is moved from a disk to the persistent cache and, responsive to the data being moved to the persistent cache, an unmounting command is issued to unmount a first file system in the first partition from the persistent cache. A mounting command is then issued to mount a second file system in a second partition to the persistent cache, wherein the second partition may now use the data contained in the persistent cache.

Abstract: A processing device included on a single chip includes processors capable of executing tasks in parallel and a cache memory shared by the processors, wherein the cache memory includes single-port memories and read data selection units, each of the single-port memories have one data output port, and each of the read data selection units is in a one-to-one association with each of the processors and selects a single-port memory which stores data to be read to a associated processor, from among the single-port memories.

Abstract: Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.

Abstract: A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a second path controller, and a synchronizer. The arbiter is configured to receive the memory requests from the plurality of requesters and identify requests for processing responsive to the requested memory banks. The first and second path controllers are coupled to the arbiter and the plurality of memory banks with the first path controller configured to process the first memory request and the second path controller configured to process the second memory request. The synchronizer is coupled between the first path controller and the second path controller for synchronizing the first and second path controllers such that the first and second memory requests processed by the first and second path controllers, respectively, do not conflict.

Abstract: In a computer system with a multi-core processor having a shared cache memory level, an operating system scheduler adjusts the CPU latency of a thread running on one of the cores to be equal to the fair CPU latency which that thread would experience when the cache memory was equally shared by adjusting the CPU time quantum of the thread. In particular, during a reconnaissance time period, the operating system scheduler gathers information regarding the threads via conventional hardware counters and uses an analytical model to estimate a fair cache miss rate that the thread would experience if the cache memory was equally shared. During a subsequent calibration period, the operating system scheduler computes the fair CPU latency using runtime statistics and the previously computed fair cache miss rate value to determine the fair CPI value.

Abstract: Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in response to a cache miss at a local cache. A shared cache structure may provide at least one speculative data fill and a coherent data fill of the desired data to at least one of the plurality of processor cores in response to a request from the at least one processor core. A processor scoreboard arbitrates the requests for the desired data. A speculative data fill of the desired data is provided to the at least one processor core. The coherent data fill of the desired data may be provided to the at least one processor core in a determined order.

Abstract: Cache management strategies are described for retrieving information from a storage medium, such as an optical disc, using a cache memory including multiple cache segments. A first group of cache segments can be devoted to handling the streaming transfer of a first type of information, and a second group of cache segments can be devoted to handling the bulk transfer of a second type of information. A host system can provide hinting information that identifies which group of cache segments that a particular read request targets. A circular wrap-around fill strategy can be used to iteratively supply new information to the cache segments upon cache hits by performing pre-fetching. Various eviction algorithms can be used to select a cache segment for flushing and refilling upon a cache miss, such as a least recently used (LRU) algorithm or a least frequently used (LFU) algorithm.

Abstract: A method for detecting and repairing cloud splits in a distributed system such as a peer-to-peer (P2P) system is presented. Nodes in a cloud maintain a multilevel cache of entries for a subset of nodes in the cloud. The multilevel cache is built on a circular number space, where each node in the cloud is assigned a unique identifier (ID). Nodes are recorded in levels of the cache according to the distance from the host node. The size of the cloud is estimated using the cache, and cloud-split tests are performed with a frequency inversely proportional to the size of the cloud. Cloud splits are initially detected by polling a seed server in the cloud for a node N having an ID equal to the host ID+1. The request is redirected to another node in the cloud, and a best match for N is resolved. If the best-match is closer to the host than any node in the host's cache, a cloud split is presumed.

Abstract: A computer has a plurality of processors with a cache memory. When a spinwait detecting unit provided to a processor detects execution of a spinwait command, it instructs monitoring of a variable value as a spinwait end condition and changes an operating state of a processor. A value change detecting unit provided to the cache memory monitors the variable value specified by the spinwait detecting unit, and when it detects that the variable value is changed, it posts the value change to the processor so as to return the operating state into its original state.

Abstract: A channel adapter connected to a host has a local cache memory. The channel adapter duplexes and writes the write-data in the local cache memory in response to a data-write request from the host. Then, the channel adapter sends the write-completion to the host and transfers all of the write-data within the local cache memory to the main cache memory in asynchronous timing. The channel adapter manages directory information of the data within the local cache memory. In response to a data-read request from the host, the channel adapter checks whether the read-data hits or not in the local cache memory based on the directory information. If the read-data hits, the read-data is transferred from the local cache memory to the host.

Abstract: Methods and apparatuses enable separate management of shared data structures and shared data objects referenced by the shared data structures. The shared data structures are stored in a first memory, and the shared data structures are separately managed from the referenced shared data objects. The shared data objects can be accessed by the shared data structures via direct and/or indirect reference. A separation agent can detect references to data objects in an application to indicate which data objects are shared and are to be stored in the separate cache.

Abstract: One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.

Abstract: An extended data queue is added to the cache circuitry of a processor to handle extended data when the processor operates on a different architecture than the system it resides on. The extended data for each word coming into the processor is stored in the queue. If the extended data has some valid information, the word is replaced to ensure the information is not lost. If there is no valid information in the extended data, then the bits of the extended data are simply set to zero.

Abstract: Avoiding cache-line sharing in virtual machines can be implemented in a system running a host and multiple guest operating systems. The host facilitates hardware access by a guest operating system and oversees memory access by the guest. Because cache lines are associated with memory pages that are spaced at regular intervals, the host can direct guest memory access to only select memory pages, and thereby restrict guest cache use to one or more cache lines. Other guests can be restricted to different cache lines by directing memory access to a separate set of memory pages.

Abstract: In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.

Abstract: Disclosed is a multiprocessor system in which even if contention occurs when a common memory is accessed from each of a plurality of processors, the number of times the common memory is accessed is capable of being reduced. The common memory of the multiprocessor system is provided with a number of data areas that store data and with a control information area that stores control information indicating whether each of the data areas is in use, and each processor is provided with a storage unit equivalent to the common memory and with an access controller. The access controller of a processor that does not have access privilege monitors data and addresses that flow on the common bus, accepts data written to the common memory and data read from the common memory, and stores this data in the storage unit of its own processor, thereby storing content identical with that of the common memory.

Abstract: A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface units provided with an interface with a magnetic disk unit respectively, a cache memory unit, and a shared memory unit. The number of access paths connected to said cache memory unit is less than the number of access paths connected to the shared memory unit.