Abstract: A memory system according to the present technology includes a nonvolatile memory area, a buffer memory area temporarily storing data, and a plurality of cores configured to store, in the nonvolatile memory area, the data stored in the buffer memory area in response to a sudden power off, each of the plurality of cores outputting an interrupt signal indicating that the sudden power off is sensed.

Abstract: An apparatus comprises at least one processing device configured to receive, by at least one network switch, a communication comprising a virtual logical device tag. The processing device is also configured, responsive to determining that the virtual logical device tag is a host-specific virtual logical device tag associated with a given host-specific virtual logical device of a given host device that is part of a multi-host link aggregation bond, to direct the communication to a given link for the given host device. The processing device is further configured, responsive to determining that the virtual logical device tag is a service-generic virtual logical device tag for a service provided by host devices which are part of the multi-host link aggregation bond) collectively, to select one of the host devices in accordance with a distribution algorithm and to direct the communication to a selected link for the selected host device.

Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

Abstract: Infrastructure resource capacity management techniques in an information processing system are disclosed. For example, a method comprises the following steps. Data associated with at least one resource of one or more computing platforms is obtained. Each of the one or more computing platforms is deployed at one or more locations associated with one or more entities. One or more resource expansion trigger threshold values are computed based on at least a portion of the obtained data for each of the one or more computing platforms. A resource expansion operation is initiated for the one or more computing platforms based on the one or more resource expansion trigger threshold values.

Abstract: A method for enabling enable use of multiple active paths for TDM traffic over a packet switched network, comprises: receiving at least two copies of a replicated packet including TDM information via at least two paths through the packet switched network, the at least two copies of the replicated packet including at least a first copy of the replicated packet received via a first of the at least two paths, and a second copy of the replicated packet received via a second of the at least two paths; selecting a copy of the replicated packet from among the at least two copies of the replicated packet; inputting the selected copy of the replicated packet to a jitter buffer; discarding unselected ones of the at least two copies of the replicated packet; and outputting the selected copy of the replicated packet from the jitter buffer to a TDM endpoint device.

Abstract: A method comprises maintaining a mapping data structure comprising a plurality of mapping entries, each such mapping entry associating an assigned name of a corresponding logical storage device of a storage system with a unique identifier of that logical storage device, a given such mapping entry further comprising a timestamp associated with the logical storage device. The method further comprises identifying a source logical storage device for a migration process, accessing the mapping data structure to determine a timestamp of the source logical storage device and one or more additional timestamps of one or more respective candidate target logical storage devices for the migration process, selecting based at least in part on the determined timestamps a particular one of the one or more candidate target logical storage devices, and initiating the migration process to migrate the source logical storage device to the selected target logical storage device.

Abstract: Systems and methods for managing host virtual addresses in a system call are disclosed. In one implementation, a processing device may receive, by a supervisor managing a first application), a system call initiated by the first application, wherein a first parameter of the system call specifies a memory buffer virtual address of the first application and a second parameter of the system call specifies the memory buffer virtual address of the second application. The processing device may also translate the memory buffer virtual address of the first application to a first physical address and may translate the memory buffer virtual address of the second application to a second physical address. The processing device may further compare the first physical address to the second physical address and responsive to determining that the first physical address matches the second physical address, the processing device may execute the system call using the memory buffer virtual address of the second application.

Abstract: A cluster compute server stores different types of data at different storage volumes in order to reduce data duplication at the storage volumes. The storage volumes are categorized into two classes: common storage volumes and dedicated storage volumes, wherein the common storage volumes store data to be accessed and used by multiple compute nodes (or multiple virtual servers) of the cluster compute server. The dedicated storage volumes, in contrast, store data to be accessed only by a corresponding compute node (or virtual server).

Abstract: Disclosed is a data recording unit and a data recording system for use in connection with a vehicle, such as a train, a locomotive, a railcar of a train, and the like.

Abstract: An approach is disclosed that identifies a home node of a data granule. The process is performed by an information handling system (a local node) that retrieves a global virtual address directory. The global virtual address directory maps shared virtual addresses to a number nodes that includes the local node with one of the nodes being the home node. The shared virtual addresses correspond to a plurality of memory addresses that are stored in a shared virtual memory that is shared amongst the plurality of nodes. The approach receives a selected shared virtual address, retrieves, from the global virtual address directory, the home node associated with the selected shared virtual address, and accesses the data granule corresponding to the selected shared virtual address from the home node.

Abstract: A variety of device interfaces may be connected to a test platform in a fast and efficient manner using multi-pin cables and connectors to support high-volume processing of devices to be tested. The multi-pin cables and connectors may aggregate a plurality of specific device interfaces into a single cable that can be connected via a connector to a test shelf and via a connector to a test platform, reducing the time to setup for device testing and facilitating high-volume processing of devices to be tested.

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

Abstract: A technique involves determining, in redundant array of independent disks (RAID) stripes, source slices for restriping, and allocating, from a reserved capacity for file system check (FSCK), destination slices for restriping. The technique further involves performing restriping for the RAID stripes by copying data in the source slices into the destination slices. Accordingly, using the reserved capacity for FSCK as the destination slices for restriping may mitigate the influence on an available capacity of a mapper during restriping, thereby improving the performance of a storage system.

Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.

Abstract: Systems and methods for managing library-based memory deduplication are disclosed. In one implementation, a processing device may start a first instance of an application on a host computer system. Responsive to detecting that the first instance completed an initialization stage, the processing device may create a data structure referencing a first plurality of memory pages created by the first instance of the application. The processing device may further identify, among a second plurality of memory pages associated with the application, a first memory page. The processing device may also identify, among the first plurality of memory pages referenced by the data structure, a second memory page identical to the first memory page. The processing device may further modify a pointer referencing the first memory page to reference the second memory page and may release the first memory page.

Abstract: This application discloses a method and an apparatus, an electronic device, and a computer-readable storage medium for implementing data transmission.

Abstract: A first mode setting signal is received from a host system. The first mode setting signal indicates a first mode. A memory component is memory component to the first mode based on the first mode setting signal. In the first mode, memory cells of the memory component are exposed to the host system. A second mode setting signal is received from the host system. The second mode setting signal indicates a second mode. The memory component is set to the second mode based on the second mode setting signal. In the second mode, a machine learning operation component of the memory component is exposed to the host system.

Abstract: Systems and methods for controlling management operations and shared memory space are disclosed. A cloud cache management controller may receive multiple sets of service attributes. Each set of the multiple sets of service attributes may be related to a cloud cache service instance. The cloud cache management controller may receive a first cloud cache management request. The cloud cache management request may comprise a cloud cache management operation. The cloud cache management controller may retrieve a set of service attributes from the multiple sets of service attributes based on an evaluation of the cloud cache management operation. The cloud cache management controller may send the first cloud cache management request to a corresponding CCSI based on a priority value for the first cloud cache management request calculated based on the retrieved set of service attributes.

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

Abstract: Methods, systems and articles of manufacture for using one or more predictive models to predict which tax matters are relevant to a particular taxpayer during preparation of an electronic tax return. A tax return preparation system accesses taxpayer data such as personal data and/or tax data regarding the particular taxpayer. The system executes a predictive model which receives the taxpayer data as inputs to the predictive model. The predictive model generates as output(s) one or more predicted tax matters which are determined to be likely to be relevant to the taxpayer. The system may then determine tax questions to present to the user based at least in part upon the predicted tax matters determined by the predictive model.

Abstract: An information handling system may include at least one processor; and a non-transitory memory coupled to the at least one processor; wherein the information handling system is configured to manage an information handling system cluster by providing a command line interface between a user and a daemon service configured to execute user commands; wherein the command line interface implements a proxy subcommand that is configured to accept other commands; and wherein, when an other command is received, the daemon service is configured to parse the other command and dispatch the parsed other command to a particular backend service.

Abstract: Snaps are distributed among data nodes for load balancing and overload avoidance. A snap is initially associated with a first VNAS server on a first data node that hosts the primary volume being snapped. A second data node is selected based on loading. The second data node may be in the same or a different cluster. A second VNAS server is instantiated on the second data node. The snap is then mounted on the second VNAS server. The second VNAS server may be configured as the target for all reads to the snap. If the second data node is in a different cluster than the snap may be copied or moved from a first SAN node to a second SAN node. Multiple copies of snaps may be distributed, and individual snaps and copies may be associated with different SLOs.

Abstract: An electronic device includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal, and a command/address signal and receives and outputs a first data and a second data. The semiconductor device is synchronized with the clock signal to receive or output the first data through a first memory region that is selected by the command/address signal when the chip selection signal and the command/address signal have a logic level combination to perform a first active operation. In addition, the semiconductor device is synchronized with the clock signal to receive or output the second data through the first memory region and a second memory region that are selected by the command/address signal based on the chip selection signal during a second active operation after the first active operation.

Abstract: Various multi-processor unified memory management systems and methods are detailed herein. In embodiments detailed herein, inter-chip memory management modules may be executed by processors that are in communication via an inter-chip link. A flat memory map may be used across the multiple processors of the system. Each inter-chip memory management module may analyze memory transactions. If the memory transaction is directed to a portion of the flat memory map managed by another processor, the memory-transaction may be translated to a non-memory mapped transaction and transmitted via an inter-chip communication link.

Abstract: A memory system is provided to include a first storage device including a first memory device and a first memory controller configured to receive, from a host external to the first storage device, a request including a logical address corresponding to the request; and a second storage device including a second memory device and a second memory controller coupled to receive a request from the first storage device and to control the second memory device, wherein the first memory controller is configured to select a target address among candidate addresses and map the logical address received from the host to the target address, and wherein the candidate addresses include first physical addresses corresponding to the first memory blocks and virtual addresses corresponding to the second memory blocks included in the second memory device.

Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache locations buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.

Abstract: Systems and methods for managing host virtual addresses in a hypercall are disclosed. In one implementation, a processing device may receive, by a hypervisor managing a virtual machine (VM), a hypercall initiated by the VM, wherein a first parameter of the hypercall specifies a guest physical address (GPA) of a memory buffer and a second parameter of the hypercall specifies a host virtual address (HVA) of the memory buffer. The processing device may also translate the GPA to a first host physical address (HPA) and may translate the HVA to a second HPA. The processing device may further compare the first HPA to the second HPA and responsive to determining that the first HPA matches the second HPA, the processing device may execute the hypercall using the HVA.

Abstract: A data storage device includes a storage medium, a first buffer memory, a second buffer memory, and a controller. The controller is configured to control data input/output for the storage medium according to requests received from a host device and to store write data in the first and second buffer memories in response to a write request received from the host device.

Abstract: In a distributed computing system, a bottleneck for performance of a network is avoided and a high-performance scalable resource management function is achieved. The distributed computing system includes a plurality of components connected to each other via a network. Each of the components includes a plurality of compute nodes, a plurality of drive casings, and a plurality of storage devices. The network includes a plurality of network switches and is configured in layers. When a storage region is to be allocated to a compute node among the compute nodes, a managing unit selects, from the storage devices, a storage device related to the storage region to be allocated or selects, from the drives, a drive casing related to the storage region to be allocated, based on a network distance between two of the compute node, the storage device, and the drive casing.

Abstract: As disclosed herein a computer-implemented method includes providing a plurality of resource allocation zones corresponding to a plurality of resource preparation operations, receiving a request from a requester for a resource, determining a selected resource allocation zone for a tenant from the plurality of resource allocation zones, and determining a resource usage pattern from historical usage data corresponding to the tenant. The method further includes provisioning the requested resource from the selected resource allocation zone based on the resource usage pattern, executing a resource preparation operation corresponding to the selected resource allocation zone in conjunction with provisioning the requested resource, and providing the requested resource to the tenant. A computer program product and a computer system corresponding to the above method are also disclosed herein.

Abstract: Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Abstract: A consumption request, for consuming storage assets, is parsed to determine if it can be matched to an existing deployment of one or more storage assets, to correspond to matching storage assets that satisfy the consumption request. If the consumption request cannot be matched to the existing deployment of one or more storage assets, a determination is made whether the existing deployment of one or more storage assets can be modified to satisfy the consumption request. If the existing deployment of one or more storage assets cannot be modified to satisfy the consumption request, a determination is made to see if other other storage assets can be deployed or reconfigured to satisfy the consumption request. At least one storage asset is modified, deployed, or reconfigured, to satisfy the consumption request.

Abstract: To avoid degradation of access performance and resource use efficiency when a multi-node system utilizing a resource-disaggregated architecture makes data access across nodes under the control of software and the like which are not compatible with the resource-disaggregated architecture, an access control unit 410-1 is a unit included in an access control system 2, wherein remote access from a first processor 420-1 to a second information processing resource 440-2 is made via first and second communication networks, and is equipped with: a determination part 411-1 for determining whether or not the access made by the first processor 420-1 is remote access; and an access conversion part 412-1 for converting, when the access is remote access, the remote access to local access by updating access destination management information 432-1 such that the second information processing resource is associated with a first information processing device.

Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.

Abstract: An aspect includes memory access optimization in a processor complex. A non-limiting example includes determining one or more offload criteria for offloading memory movement in the processor complex. A memory movement process parameter corresponding to the one or more offload criteria is identified. Movement of a block of memory from a first block location at a first host to a second block location at a second host is scheduled as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria. The block of memory is moved from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed at least one of the offload criteria.

Abstract: Secure communication is established between a hyper-process of the virtualization layer (e.g., host) and an agent process in the guest operating system (e.g., guest) using a virtual communication device which, in an embodiment, is implemented as shared memory having two memory buffers. A guest-to-host buffer is used as a first message box configured to provide unidirectional communication from the agent to the virtualization layer and a host-to-guest buffer is used as a second message box configured to provide unidirectional communication from the virtualization layer to the agent. The buffers cooperate to transform the virtual device into a low-latency, high-bandwidth communication interface configured for bi-directional transfer of information between the agent process and the hyper-process of the virtualization layer, wherein the communication interface also includes a signaling (doorbell) mechanism configured to notify the processes that information is available for transfer over the interface.

Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

Abstract: Various aspects provide for managing memory in virtual computer system. For example, a system can include a first network node and a second network node. The first network node receives a data packet via a first hardware network controller. The first network node also transmits the data packet over a communication channel via a second hardware network controller in response to a determination that memory data for the data packet is not mapped to the first network node. The second network node receives the data packet via the communication channel and provides the data packet to an operating system associated with the first network node and the second network node.

Abstract: Provided are a computer program product, method, and system to transfer storage input/output (I/O) requests to host and target systems on different fabrics. An origination packet is received from an originating node over a first network to a destination node having a storage device. The origination packet includes a first fabric layer for transport through a first network, a command in a transport protocol with a storage Input/Output (I/O) request, with respect to the storage device at the destination node, and a host memory address. A destination packet is constructed including a second fabric layer for transport through a second network and the command in the transport protocol to send the storage I/O request and a transfer memory address that maps to the host memory address. The destination packet is sent over the second network to the destination node to perform the storage I/O request.

Abstract: A data processing system includes a host device including a first volatile memory which includes an exclusive region and a shared region, and a first control unit; and a data storage device including a second control unit, and configured to store data to be accessed by the host device, wherein the first control unit adds a header information including an identification information and a state information, to data to be stored in the data storage device, and stores the data added with the header information, in the shared region, according to a request of the second control unit.

Abstract: A controlling device includes a controller that executes control to functionally activate of, at least, a part of transmission lanes in multiple transmission lanes connecting a plurality of subsystems which run based on a lock-step method and an embedder that executes an embedding operation to realize a multiplexing state using the part of transmission lanes controlled to functionally activate by the controller and the plurality of the subsystems, wherein, the controller determines whether or not the embedding operation succeeds, determines, when the embedding operation fails, whether or not an embedding operation using another part of transmission lanes, of the multiple transmission lanes, different from the part of transmission lanes used in the failure embedding operation, and executes, when the corporation processing succeeds, control to functionally activate the another part of transmission lanes.

Abstract: According to examples, a storage node may include storage devices and a controller that may determine whether all of a plurality of data chunks of a first intra-node portion of a stripe have been stored on the storage node. Based on a determination that all of the data chunks have been stored, a first intra-node parity chunk may be stored at a second one of the storage devices, in which the first intra-node parity chunk may be determined from at least one of the data chunks of the first intra-node portion. Based on a determination that at least one of the data chunks has not been stored, storage of a first intra-node parity chunk of the stripe on the storage node may be delayed until a determination is made that all of the data chunks of the first intra-node portion have been stored at the storage node.

Abstract: A method for processing network data traffic includes obtaining a first distributed structure corresponding to a program based on a first storage structure, wherein the program is configured to process network data traffic; dividing a network device based on a second storage structure into a plurality of execution units, wherein the plurality of execution units is configured to execute the program; mapping the first distributed structure and the plurality of execution units to obtain a second distributed structure; and controlling the plurality of execution units to process network data traffic based on the second distributed structure.

Abstract: Techniques for processing I/O operations may include: receiving, at a first data storage system from a host, a write operation that writes data to a logical device; sending the write operation in a synchronous manner to a plurality of other data storage systems, wherein the first data storage system and the plurality of other data storage systems form a linear chain over which the write operation is transmitted; and sending an acknowledgement to the host regarding completion of the write operation only after the first data storage system and each of the plurality of other data storage systems have acknowledged completion of the write operation.

Abstract: A fault-tolerant process control system includes a first and second master process controller, each including a first and second serial communication engine. A first bus switch couples the first serial communication engine to a shared SPI bus and a second bus switch couples the second communication engine to shared SPI bus. The shared SPI bus transmits SPI signals received from the first serial communication engine when the first bus switch is enabled to a first target device, and transmits SPI signals received from the second serial communication engine when the second bus switch is enabled to a second target device. An arbiter block receives a select control signal from the master process controllers and is coupled to both the first and second bus switch for single bus switch selection so that only one master process controller is granted access to the shared SPI bus.

Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.

Abstract: Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.