Plural Shared Memories Patents (Class 711/148)
  • Patent number: 11221869
    Abstract: Systems and methods for managing host virtual addresses in a hypercall are disclosed. In one implementation, a processing device may receive, by a hypervisor managing a virtual machine (VM), a hypercall initiated by the VM, wherein a first parameter of the hypercall specifies a guest physical address (GPA) of a memory buffer and a second parameter of the hypercall specifies a host virtual address (HVA) of the memory buffer. The processing device may also translate the GPA to a first host physical address (HPA) and may translate the HVA to a second HPA. The processing device may further compare the first HPA to the second HPA and responsive to determining that the first HPA matches the second HPA, the processing device may execute the hypercall using the HVA.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 11, 2022
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11210015
    Abstract: A data storage device includes a storage medium, a first buffer memory, a second buffer memory, and a controller. The controller is configured to control data input/output for the storage medium according to requests received from a host device and to store write data in the first and second buffer memories in response to a write request received from the host device.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: December 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyung Min Kim, Do Hun Kim, Jae Han Park, Hyoung Suk Jang, Hyun Mo Kang
  • Patent number: 11201788
    Abstract: In a distributed computing system, a bottleneck for performance of a network is avoided and a high-performance scalable resource management function is achieved. The distributed computing system includes a plurality of components connected to each other via a network. Each of the components includes a plurality of compute nodes, a plurality of drive casings, and a plurality of storage devices. The network includes a plurality of network switches and is configured in layers. When a storage region is to be allocated to a compute node among the compute nodes, a managing unit selects, from the storage devices, a storage device related to the storage region to be allocated or selects, from the drives, a drive casing related to the storage region to be allocated, based on a network distance between two of the compute node, the storage device, and the drive casing.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: December 14, 2021
    Assignee: HITACHI, LTD.
    Inventors: Ryosuke Tatsumi, Akira Yamamoto, Shugo Ogawa, Yoshinori Ohira, Koji Hosogi
  • Patent number: 11075979
    Abstract: As disclosed herein a computer-implemented method includes providing a plurality of resource allocation zones corresponding to a plurality of resource preparation operations, receiving a request from a requester for a resource, determining a selected resource allocation zone for a tenant from the plurality of resource allocation zones, and determining a resource usage pattern from historical usage data corresponding to the tenant. The method further includes provisioning the requested resource from the selected resource allocation zone based on the resource usage pattern, executing a resource preparation operation corresponding to the selected resource allocation zone in conjunction with provisioning the requested resource, and providing the requested resource to the tenant. A computer program product and a computer system corresponding to the above method are also disclosed herein.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashish Billore, Sudheesh S. Kairali, Muthu A. Muthiah
  • Patent number: 10978427
    Abstract: Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jian Li, Steven K. Groothuis
  • Patent number: 10951469
    Abstract: A consumption request, for consuming storage assets, is parsed to determine if it can be matched to an existing deployment of one or more storage assets, to correspond to matching storage assets that satisfy the consumption request. If the consumption request cannot be matched to the existing deployment of one or more storage assets, a determination is made whether the existing deployment of one or more storage assets can be modified to satisfy the consumption request. If the existing deployment of one or more storage assets cannot be modified to satisfy the consumption request, a determination is made to see if other other storage assets can be deployed or reconfigured to satisfy the consumption request. At least one storage asset is modified, deployed, or reconfigured, to satisfy the consumption request.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: William J. Elliott, IV
  • Patent number: 10909044
    Abstract: To avoid degradation of access performance and resource use efficiency when a multi-node system utilizing a resource-disaggregated architecture makes data access across nodes under the control of software and the like which are not compatible with the resource-disaggregated architecture, an access control unit 410-1 is a unit included in an access control system 2, wherein remote access from a first processor 420-1 to a second information processing resource 440-2 is made via first and second communication networks, and is equipped with: a determination part 411-1 for determining whether or not the access made by the first processor 420-1 is remote access; and an access conversion part 412-1 for converting, when the access is remote access, the remote access to local access by updating access destination management information 432-1 such that the second information processing resource is associated with a first information processing device.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: February 2, 2021
    Assignee: NEC CORPORATION
    Inventors: Masaki Kan, Jun Suzuki, Yuki Hayashi, Akira Tsuji
  • Patent number: 10877695
    Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 29, 2020
    Assignee: III Holdings 2, LLC
    Inventors: Mark Bradley Davis, Prashant R. Chandra
  • Patent number: 10846125
    Abstract: An aspect includes memory access optimization in a processor complex. A non-limiting example includes determining one or more offload criteria for offloading memory movement in the processor complex. A memory movement process parameter corresponding to the one or more offload criteria is identified. Movement of a block of memory from a first block location at a first host to a second block location at a second host is scheduled as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria. The block of memory is moved from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed at least one of the offload criteria.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patricia G. Driever, Jerry W. Stevens
  • Patent number: 10846117
    Abstract: Secure communication is established between a hyper-process of the virtualization layer (e.g., host) and an agent process in the guest operating system (e.g., guest) using a virtual communication device which, in an embodiment, is implemented as shared memory having two memory buffers. A guest-to-host buffer is used as a first message box configured to provide unidirectional communication from the agent to the virtualization layer and a host-to-guest buffer is used as a second message box configured to provide unidirectional communication from the virtualization layer to the agent. The buffers cooperate to transform the virtual device into a low-latency, high-bandwidth communication interface configured for bi-directional transfer of information between the agent process and the hyper-process of the virtualization layer, wherein the communication interface also includes a signaling (doorbell) mechanism configured to notify the processes that information is available for transfer over the interface.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 24, 2020
    Assignee: FireEye, Inc.
    Inventor: Udo Steinberg
  • Patent number: 10838865
    Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Leidel, Richard C Murphy
  • Patent number: 10819783
    Abstract: Various aspects provide for managing memory in virtual computer system. For example, a system can include a first network node and a second network node. The first network node receives a data packet via a first hardware network controller. The first network node also transmits the data packet over a communication channel via a second hardware network controller in response to a determination that memory data for the data packet is not mapped to the first network node. The second network node receives the data packet via the communication channel and provides the data packet to an operating system associated with the first network node and the second network node.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 27, 2020
    Assignee: AMPERE COMPUTING LLC
    Inventors: Ankit Jindal, Pranavkumar Sawargaonkar, Keyur Chudgar
  • Patent number: 10769081
    Abstract: Provided are a computer program product, method, and system to transfer storage input/output (I/O) requests to host and target systems on different fabrics. An origination packet is received from an originating node over a first network to a destination node having a storage device. The origination packet includes a first fabric layer for transport through a first network, a command in a transport protocol with a storage Input/Output (I/O) request, with respect to the storage device at the destination node, and a host memory address. A destination packet is constructed including a second fabric layer for transport through a second network and the command in the transport protocol to send the storage I/O request and a transfer memory address that maps to the host memory address. The destination packet is sent over the second network to the destination node to perform the storage I/O request.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 8, 2020
    Assignee: INTEL CORPORATION
    Inventors: Jay E. Sternberg, Phil C. Cayton, James P. Freyensee
  • Patent number: 10747462
    Abstract: A data processing system includes a host device including a first volatile memory which includes an exclusive region and a shared region, and a first control unit; and a data storage device including a second control unit, and configured to store data to be accessed by the host device, wherein the first control unit adds a header information including an identification information and a state information, to data to be stored in the data storage device, and stores the data added with the header information, in the shared region, according to a request of the second control unit.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Soong Sun Shin
  • Patent number: 10740199
    Abstract: A controlling device includes a controller that executes control to functionally activate of, at least, a part of transmission lanes in multiple transmission lanes connecting a plurality of subsystems which run based on a lock-step method and an embedder that executes an embedding operation to realize a multiplexing state using the part of transmission lanes controlled to functionally activate by the controller and the plurality of the subsystems, wherein, the controller determines whether or not the embedding operation succeeds, determines, when the embedding operation fails, whether or not an embedding operation using another part of transmission lanes, of the multiple transmission lanes, different from the part of transmission lanes used in the failure embedding operation, and executes, when the corporation processing succeeds, control to functionally activate the another part of transmission lanes.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 11, 2020
    Assignee: NEC CORPORATION
    Inventor: Yasuyuki Shirano
  • Patent number: 10705911
    Abstract: According to examples, a storage node may include storage devices and a controller that may determine whether all of a plurality of data chunks of a first intra-node portion of a stripe have been stored on the storage node. Based on a determination that all of the data chunks have been stored, a first intra-node parity chunk may be stored at a second one of the storage devices, in which the first intra-node parity chunk may be determined from at least one of the data chunks of the first intra-node portion. Based on a determination that at least one of the data chunks has not been stored, storage of a first intra-node parity chunk of the stripe on the storage node may be delayed until a determination is made that all of the data chunks of the first intra-node portion have been stored at the storage node.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Murali Krishna Vishnumolakala, Umesh Maheshwari
  • Patent number: 10678727
    Abstract: A method for processing network data traffic includes obtaining a first distributed structure corresponding to a program based on a first storage structure, wherein the program is configured to process network data traffic; dividing a network device based on a second storage structure into a plurality of execution units, wherein the plurality of execution units is configured to execute the program; mapping the first distributed structure and the plurality of execution units to obtain a second distributed structure; and controlling the plurality of execution units to process network data traffic based on the second distributed structure.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 9, 2020
    Assignee: HILLSTONE NETWORKS CORP.
    Inventors: Dongyi Jiang, Linyang Shu, Jiangbo Nie, Ye Zhang, Yu Jia, Qijun Yang, Juxi Li
  • Patent number: 10613766
    Abstract: Techniques for processing I/O operations may include: receiving, at a first data storage system from a host, a write operation that writes data to a logical device; sending the write operation in a synchronous manner to a plurality of other data storage systems, wherein the first data storage system and the plurality of other data storage systems form a linear chain over which the write operation is transmitted; and sending an acknowledgement to the host regarding completion of the write operation only after the first data storage system and each of the plurality of other data storage systems have acknowledged completion of the write operation.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 7, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Bhaskar Bora, Toufic Tannous
  • Patent number: 10579563
    Abstract: A fault-tolerant process control system includes a first and second master process controller, each including a first and second serial communication engine. A first bus switch couples the first serial communication engine to a shared SPI bus and a second bus switch couples the second communication engine to shared SPI bus. The shared SPI bus transmits SPI signals received from the first serial communication engine when the first bus switch is enabled to a first target device, and transmits SPI signals received from the second serial communication engine when the second bus switch is enabled to a second target device. An arbiter block receives a select control signal from the master process controllers and is coupled to both the first and second bus switch for single bus switch selection so that only one master process controller is granted access to the shared SPI bus.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Honeywell International Inc.
    Inventor: Aad van Wensen
  • Patent number: 10545862
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10547680
    Abstract: Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Robert G. Blankenship
  • Patent number: 10534735
    Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 14, 2020
    Assignee: VMware, Inc.
    Inventors: Mallik Mahalingam, Michael Nelson
  • Patent number: 10534686
    Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Jason M. Brown, Derek R. May, Jeffrey E. Koelling, Roger D. Norwood
  • Patent number: 10489210
    Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 26, 2019
    Assignee: NETAPP, INC.
    Inventors: Dheeraj Raghavender Sangamkar, Ajay Bakre, Vladimir Radu Avram, Emalayan Vairavanathan, Viswanath Chandrasekara Bharathi
  • Patent number: 10416916
    Abstract: A Memory Merging Function “MMF” for merging memory pages. A hardware system comprises a set of memory blades and a set of computing pools. At least one instance of an operating system executes on the hardware system. The MMF is independent of the operating system. The MMF finds a first and a second memory page. The first and second memory pages include identical information. The first and second memory pages are associated with at least one computing unit of the computing units. The MMF obtains a respective memory blade parameter relating to memory blade of the first and second memory pages and a respective latency parameter relating to latency for accessing the first and second memory pages. The MMF releases at least one of the first and second memory pages based on the respective memory blade and latency parameters.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: September 17, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Amir Roozbeh, Joao Monteiro Soares, Daniel Turull
  • Patent number: 10387464
    Abstract: In one embodiment, a method includes receiving text query that includes n-grams. A vector representation of each n-gram is determined using a deep-learning model. A nonlinear combination of the vector representations of the n-grams is determined, and an embedding of the text query is determined based on the nonlinear combination. The embedding of the text query corresponds to a point in an embedding space, and the embedding space includes a plurality of points corresponding to a plurality of label embeddings. Each label embedding is based on a vector representation of a respective label determined using the deep-learning model. Label embeddings are identified as being relevant to the text query by applying a search algorithm to the embedding space. Points corresponding to the identified label embeddings are within a threshold distance of the point corresponding to the embedding of the text query in the embedding space.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: August 20, 2019
    Assignee: Facebook, Inc.
    Inventors: Jason E. Weston, Keith Adams, Sumit Chopra
  • Patent number: 10387666
    Abstract: Disclosed are system and method for synchronization of large amounts of data while maintaining control over access rights to such data in electronic data storage. An exemplary method comprises: partitioning a volume of data into a plurality of data blocks; assigning a synchronization status to at least one data block in the plurality of data blocks; determining access rights to the data contained in the at least one data block, based upon at least one of information identifying an owner or administrator associated with the at least one data block, or a set of allowed or prohibited operations that may be performed on the at least one data block; controlling access to the data contained in the at least one data block based upon the determination of access rights; and updating the synchronization status of the at least one data block.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: August 20, 2019
    Assignee: Acronis International GmbH
    Inventors: Serguei Beloussov, Alexander Tormasov, Stanislav Protasov, Mark Shmulevich
  • Patent number: 10379746
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, and a second memory. The processing device executes first processing on first data. The second memory stores the first data and has a data access latency higher than that of the first memory. The first data includes first and second pages, the first page being read/written times not less than a threshold in a certain period shorter than a period for executing the first processing, the second page being read/written times less than the threshold in the certain period. The processing device includes a controller configured to execute first access to move the first page to the first memory and then read/write data from/to the moved first page, and execute second access to directly read/write data from/to the second page of the second memory.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura
  • Patent number: 10331603
    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: June 25, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Cameron Buschardt, James Leroy Deming, Brian Fahs, Mark Hairgrove, John Mashey
  • Patent number: 10333860
    Abstract: In accordance with a method a plurality of subscriber systems are provided, the systems being coupled via a Wide Area Network (WAN) and comprising a first subscriber system. The first subscriber system has processing and non-volatile storage and is suitably programmed for providing a subscriber service to a first subscriber. The first system is disposed in an unsecured location, which is associated with the first subscriber. Subsequently, the subscriber service is provided to the first subscriber. Separately, a task is provided to the first subscriber system via the WAN and is executed on the first subscriber system. An activity record for the execution of the task is logged, based on an amount of at least one of the processing and the non-volatile storage consumed on the first subscriber system during execution of the task.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: June 25, 2019
    Assignee: LEONOVUS USA
    Inventors: Daniel Willis, Paul Master, Gordon Campbell, Sean O'Hagan, Derek Noble
  • Patent number: 10318431
    Abstract: Examples herein disclose a cache controller to receive a cache signal. A physical unclonable function (PUF) circuit is coupled to the cache controller. The PUF circuit obscures the cache signal in response to the cache signal receipt.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 11, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: Anys Bacha
  • Patent number: 10313471
    Abstract: Data can be stored in a persistent-memory device, rather than a hard drive, of a computing device. A copy of the data can also be stored in another persistent-memory device of a remote computing device. For example, a central processing unit (of the computing device) can perform a first write operation to cause a file to be stored in the persistent-memory device. A memory controller can perform a second write operation to cause another memory controller of the remote computing device to store a copy of the file in the other persistent-memory device of the remote computing device.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 4, 2019
    Assignee: Red Hat, Inc.
    Inventors: Luis Pablo Pabon, Jeffrey Alan Brown, Henry Dan Lambright
  • Patent number: 10310983
    Abstract: An operating method for a data storage device may include: reading data from a first memory region of a storage medium; storing the read data in a data buffer; and writing the data stored in the data buffer to a second memory region of the storage medium, based on a read count for the first memory region.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Byeong Gyu Park
  • Patent number: 10296245
    Abstract: A method of rebuild operation of a memory controller, the method includes: searching a reference page information stored in a first memory block when a power is restored after occurrence of a sudden power off; identifying a reference page of a second memory block and storing the reference page information of the reference page into the first memory block when the reference page information is determined not to be stored in the first memory block; and performing a rebuild operation to data stored in the second memory block based on the reference page information stored in the first memory block.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventor: JangHwan Jun
  • Patent number: 10289319
    Abstract: A method begins by determining whether at least one encoded data slice of a corresponding set of encoded data slices associated with a primary storage unit requires rebuilding and includes one or more excess encoded data slices of the set of encoded data slices stored in a secondary storage unit. The method continues by identifying the excess encoded data slices based on scan response messages from the secondary storage units. The method continues by assigning, for each data segment associated with at least one of an encoded data slice requiring rebuilding and an excess encoded data slice, a priority level in accordance with a prioritization scheme. The method continues by facilitating, for each data segment, rebuilding of the encoded data slices requiring rebuilding and deletion of excess encoded data slices requiring deletion in accordance with the assigned priority level of the data segment.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10277686
    Abstract: In one embodiment, a method comprises generating, by a network device in a network, a Bloom filter bit vector representing services provided by service provider devices in the network; and the network device executing a service discovery operation based on identifying, relative to the Bloom filter bit vector, whether an identified service in a received message is executed in the network.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: April 30, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Shwetha Subray Bhandari, Pascal Thubert, Selvaraj Mani
  • Patent number: 10261813
    Abstract: A data processing system comprising an accelerator that acts as a common shared resource for plural applications executing in respective virtual machines. The data processing system includes an interface mapping unit that facilitates the submission of tasks from applications to the accelerator. The interface mapping unit includes physical registers that act as physical register input/output interfaces for the accelerator. The interface mapping unit exposes a plurality of virtual accelerator input/output interfaces to the applications that are then dynamically mapped to the physical register input/output interfaces by the interface mapping unit to allow applications to access, and thereby submit a task to, a given physical register input/output interface.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 16, 2019
    Assignee: Arm Limited
    Inventors: Hakan Persson, Wade Walker
  • Patent number: 10235198
    Abstract: A mass storage device for providing persistent storage. The system includes a plurality of instances of virtual flash translation layers, each associated with a namespace and configured to provide, to one or more virtual machines executing in a host connected to the mass storage device, access to read and write operations in the persistent storage.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sheng Qiu, Yang Seok Ki
  • Patent number: 10235422
    Abstract: A system includes reception of a value, determination of whether the value is associated with a respective value identifier in a dictionary index associating each of a plurality of values with a respective value identifier, and in response to a determination that the value is not associated with a respective value identifier in the dictionary index: reservation of a slot of a reservation array comprising a plurality of slots, writing of the value into the reserved slot, insertion of a reserved value identifier of the reserved slot and a version counter of the reserved slot into a position of the dictionary index corresponding to the value, insertion of the value into a position of a dictionary vector storing a respective value in each of a plurality of vector positions, insertion of a first value identifier corresponding to the position of the dictionary vector into the position of the dictionary index corresponding to the value, and returning of the first value identifier.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 19, 2019
    Assignee: SAP SE
    Inventor: Ivan Schreter
  • Patent number: 10209921
    Abstract: A method for execution by a computing device of a dispersed storage network (DSN). The method begins with identifying an encoded data slice for rebuilding, wherein a data segment of a data object is dispersed storage error encoded to produce a set of encoded data slices that is stored in a set of storage units of the DSN, wherein the set of encoded data slices includes the encoded data slice, wherein in a storage unit of the set of storage units includes a memory device that stores the encoded data slice. The method continues by identifying an issue with the memory device and by identifying sets of encoded data slices. The method continues by generating an additional encoded data slice for each of the sets of encoded data slices to produce a group of encoded data slices and storing the group of encoded data slices in memory of the DSN.
    Type: Grant
    Filed: August 27, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Andrew G. Peake
  • Patent number: 10198187
    Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 5, 2019
    Assignee: Rambus Inc.
    Inventor: David Wang
  • Patent number: 10176249
    Abstract: A system, and corresponding method, for retrieving image and metadata from multiple sources in response to a query received from an originator having a corresponding clearance level. The query is received through an interface and then any errors or ambiguities in the received query are determined and corrected to create a parsed query. A standardized query is created from the parsed query and has a system usable format including corresponding query processing limitations and the standardized query is stored for later processing. The standardized query comprises one or more terms not accessible to the originator. The stored standardized query is processed to collect resulting corresponding image and metadata information. The query results are presented to the originator if a corresponding clearance level of the query results is at or below the clearance level of the originator.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 8, 2019
    Assignee: Raytheon Company
    Inventor: James E. Taber
  • Patent number: 10171563
    Abstract: Systems and methods for intelligent memory sharing and contextual retrieval across multiple devices and multiple applications are provided. The systems and methods do not just show a user what he or she has stored across his or her different devices but intelligently suggests relevant topics and/or information based on what is contained in a shared working memory compiled from the temporary memories on all of the user devices.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: January 1, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Deepinder S. Gill, Vipindeep Vangala, Govind Saoji
  • Patent number: 10152377
    Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 11, 2018
    Assignee: NetApp, Inc.
    Inventors: Dheeraj Raghavender Sangamkar, Ajay Bakre, Vladimir Radu Avram, Emalayan Vairavanathan, Viswanath Chandrasekara Bharathi
  • Patent number: 10120810
    Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
  • Patent number: 10114742
    Abstract: A first write data and a second write data destined for a first solid state storage channel and a second solid state storage channel, respectively, is received. The first write data is chopped using a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel. The second write data is chopped using the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 30, 2018
    Assignee: SK Hynix Inc.
    Inventors: Wei-Hao Yuan, Chun Hok Ho, Johnson Yen
  • Patent number: 10061692
    Abstract: Example embodiments of the present invention include a method, a system, and a computer-program product for storage automation. The method includes receiving a request for storage, determining a storage allocation for provisioning according to the request for storage and available storage resources, and provisioning storage according to the determined storage allocation.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: August 28, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Shawn R. Nicklin, Brent J. Rhymes
  • Patent number: 10049723
    Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10007614
    Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 26, 2018
    Assignee: Cavium, Inc.
    Inventors: Xiaodong Wang, Srilatha Manne, Bryan Wai Chin, Isam Akkawi, David Asher
  • Patent number: 9990291
    Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 5, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hien Minh Le, Thuong Quang Truong, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez