Shared Memory Area Patents (Class 711/147)
  • Patent number: 10445009
    Abstract: Systems and methods that manage memory usage by a virtual machine are provided. These systems and methods compact the virtual machine's memory footprint, thereby promoting efficient use of memory and gaining performance benefits of increased data locality. In some embodiments, a guest operating system running within the virtual machine is enhanced to allocate its VM memory in a compact manner. The guest operating system includes a memory manager that is configured to reference an artificial access cost when identifying memory areas to allocate for use by applications. These access costs are described as being artificial because they are not representative of actual, hardware based access costs, but instead are fictitious costs that increase as the addresses of the memory areas increase. Because of these increasing artificial access costs, the memory manager identifies memory areas with lower addresses for allocation and use prior to memory areas with higher addresses.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Graham Whaley, Adriaan van de Ven, Manohar R. Castelino, Jose C. Venegas Munoz, Samuel Ortiz
  • Patent number: 10437728
    Abstract: Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. The instructions comprise a branchless instruction set. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Instructions are provided to logical elements, such as processing elements, via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 8, 2019
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10423790
    Abstract: Some embodiments provide a method for preventing stressed end machines from being scanned for security check on a host machine that executes several different end machines scheduled to be scanned for security check. The method collects, at one of the end machines, a set of measurement data from a set of resources of the end machine. The method then determines whether a measurement data collected from a particular resource has exceeded a threshold. When the measurement data has exceeded the threshold, the method tags the end machine as a stressed machine so that the end machine will not participate in any future security check scans.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 24, 2019
    Assignee: NICIRA, INC.
    Inventors: Amit Vasant Patil, Vasantha Kumar
  • Patent number: 10423446
    Abstract: Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configur
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Curtis Glenn Dunham, Jonathan Curtis Beard, Roxana Rusitoru
  • Patent number: 10423415
    Abstract: Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: September 24, 2019
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Patent number: 10409678
    Abstract: A method begins by receiving a first read request of a plurality of read requests, from a user device of a plurality of user devices of a dispersed storage network, for a first data segment. The method continues by determining, for each read request, a read ahead scheme based on one or more read ahead parameters to produce a plurality of read ahead schemes. The method continues by determining a data retrieval scheme based on the plurality of read ahead schemes and retrieving, for each read request, one or more read ahead sets of encoded data slices. The method continues by receiving a second read request for a second data segment and verifying that read ahead data includes the second data segment. When the read ahead data includes the second data segment, the method continues by sending a representation of the read ahead data to the user device.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 10, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Wesley B. Leggette, Jason K. Resch
  • Patent number: 10394477
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for allocating memory. A computer receives a request for memory to be allocated to a computer node and determines if the allocation request needs to be carried out on a cluster level, a server rack level, or on a server level. The computer retrieves a memory policy associated with the determined level the allocation request needs to be carried out on from a memory policy database and determines how much available memory may be allocated and if there enough available memory to meet the request. The computer reallocates the available memory to address the received the received request based on the retrieved memory policy.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhong Li, Xian Dong Meng
  • Patent number: 10394475
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for allocating memory. A computer receives a request for memory to be allocated to a computer node and determines if the allocation request needs to be carried out on a cluster level, a server rack level, or on a server level. The computer retrieves a memory policy associated with the determined level the allocation request needs to be carried out on from a memory policy database and determines how much available memory may be allocated and if there enough available memory to meet the request. The computer reallocates the available memory to address the received the received request based on the retrieved memory policy.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhong Li, Xian Dong Meng
  • Patent number: 10394605
    Abstract: Causing a computing system to process events from a sequence of events that defines a correct order for said events independent from an order in which those events are received includes: defining a first variable, defining, for the first variable, a chronology of operations on the first variable associated with received events, receiving a first event that pertains to the first variable, executing a first operation on said first variable that results in a first update of the chronology, receiving a delayed event that pertains to the first variable, executing a second operation on said first variable that results in a second update of the chronology, and determining whether the first update is valid or invalid, wherein the delayed event precedes the first event in the sequence, the first update is based on the first event, and the second update is based on the delayed event.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 27, 2019
    Assignee: Ab Initio Technology LLC
    Inventor: Craig W. Stanfill
  • Patent number: 10387061
    Abstract: Techniques herein perform coprocessor assisted memory filling in a pipeline. A computer receives a request to fill multiple ranges of memory addresses with a value. The computer selects a first subset of the multiple ranges and distributes the first subset of ranges to multiple coprocessors. The coprocessors begin to fill the memory locations of the first subset of ranges with the value. At the same time as the coprocessors fill the first subset of ranges, the computer selects a second subset of the multiple ranges of memory addresses. Also while the coprocessors are still filling the first subset of ranges, the computer distributes the second subset of ranges to the coprocessors This overlapping activity achieves a processing pipeline that can be extended for any amount of additional subsets of memory ranges.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 20, 2019
    Assignee: Oracle International Corporation
    Inventors: Kishore Pusukuri, Robert D. Gardner
  • Patent number: 10387055
    Abstract: Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. The method can include, responsive to determining the particular endianness format is a first endianness format, reordering bits of each byte of the plurality of bytes on a bytewise basis, storing the reordered plurality of bytes in an array of memory cells, and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array. The method can include, responsive to determining the particular endianness format is a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jeremiah J. Willcock, Kyle B. Wheeler, Timothy P. Finkbeiner
  • Patent number: 10387194
    Abstract: A system includes a topology monitoring unit to generate a topology map of a machine where the machine includes node boards in host computers. The topology map is indicative of interconnections of resources of the machine. The topology monitoring unit queries the machine to identify elements of the machine, stores all the elements of the machine in a string array, generates a key for each element as an array of integers where each integer in the array represents an offset into the string array, and generates the topology map of the machine using the generated keys.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Igor Shpigelman
  • Patent number: 10386904
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Christophe Denis Bernard Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik, Steven John Halter, Jaya Prakash Subramaniam Ganasan, Myil Ramkumar, Dipti Ranjan Pal
  • Patent number: 10372606
    Abstract: A memory device includes a memory interface to a host computer and a memory overprovisioning logic configured to provide a virtual memory capacity to a host operating system (OS). A kernel driver module of the host OS is configured to manage the virtual memory capacity of the memory device provided by the memory overprovisioning logic of the memory device and provide a fast swap of anonymous pages to a frontswap space and file pages to a cleancache space of the memory device based on the virtual memory capacity of the memory device.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Krishna Malladi, Jongmin Gim, Hongzhong Zheng
  • Patent number: 10360145
    Abstract: A system includes writing of log data in chunks over a first range of heap log sequence positions of a heap log stored in the non-volatile memory system, and writing of a heap anchor marker in a first anchor stream of a transaction log stored in the non-volatile memory system, at a first transaction log sequence position of the transaction log, wherein the first anchor stream is associated with a first stream of the transaction log, and the heap anchor marker identifies the first range of heap log sequence positions of the heap log.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 23, 2019
    Assignee: SAP SE
    Inventors: Jeffrey Pound, Nathan Auch, Peter Bumbulis, Anil Kumar Goel, Scott MacLean, Eric Garber
  • Patent number: 10346311
    Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
  • Patent number: 10338818
    Abstract: The disclosed computer-implemented method for enabling safe memory de-duplication in shared-computing environments may include (i) identifying a first virtual machine and a second virtual machine, (ii) calculating a trustworthiness score for the first virtual machine based on a trustworthiness score of each binary of the first virtual machine, (iii) calculating a trustworthiness score for the second virtual machine based on a trustworthiness score of each binary of the second virtual machine, and (iv) enabling the first virtual machine and the second virtual machine to share a page frame of physical memory by assigning, based on the trustworthiness scores of the first virtual machine and the second virtual machine being above a predetermined threshold, the first virtual machine and the second virtual machine to a trusted group of virtual machines that can share physical memory. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: July 2, 2019
    Assignee: Symantec Corporation
    Inventors: William E. Sobel, Bruce McCorkendale
  • Patent number: 10310897
    Abstract: Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Tracy Garrett Drysdale, Vinodh Gopal, James D. Guilford
  • Patent number: 10296264
    Abstract: A method of selecting among a plurality of I/O streams through which data is to be written to a multi-streaming flash storage device is presented. According to an example embodiment, the method comprises: assigning write sequences of similar length to the same I/O streams; receiving instructions for a write operation, the instructions including a starting logical block address (LBA) and a number of blocks of data to be written; determining whether the write operation is part of an existing write sequence; identifying an I/O stream associated with an existing write sequence; and providing a stream ID of the identified I/O stream to the multi-streaming flash storage device.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sina Hassani, Anahita Shayesteh, Vijay Balakrishnan
  • Patent number: 10298782
    Abstract: An electronic device and data processing method thereof is provided. The electronic device of the present disclosure includes a first processor which acquires image data from a camera and generates a data frame based on the image data and a second processor which receives the data frame from the first processor, checks attribute information of the data frame, and supplies information on the data frame to at least one of a plurality of applications corresponding to the attribute information.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungsoon Kim, Yongchan Keh, Hyowon Kim, Byeonghoon Park, Kisuk Sung, Jungkee Lee, Kihuk Lee, Changryong Heo
  • Patent number: 10290035
    Abstract: In one aspect, this application describes a method for determining a version of a software application targeted for a computing device. The method includes receiving, at an application marketplace system and from a user associated with a computing device that operates remotely from the application marketplace system, a request that corresponds to a software application distributed by the application marketplace system, the software application having multiple versions on the application marketplace system. The method also includes determining one or more device attributes that are associated with the computing device, and identifying a particular version of the software application, from among the multiple versions on the application marketplace system, that is targeted for the computing device based on the device attributes. The method also includes providing, for display to the user and in response to the request, information related to the particular version of the software application.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 14, 2019
    Assignee: Google LLC
    Inventors: Ilya Firman, Jasper S. Lin, Mark D. Womack, Yu-Kuan Lin, Sheng-chi Hsieh, Juliana Tsang
  • Patent number: 10282138
    Abstract: A method to optimize primary and secondary read cache in a data replication environment includes determining contents of a primary read cache at a primary site. The method updates a primary cache map describing the contents and transmits the primary cache map from the primary site to a secondary site. At the secondary site, the method uses the primary cache map to substantially synchronize a secondary read cache with the primary read cache. The method further monitors for updates to the primary read cache and updates the primary cache map accordingly. When a difference between a current primary cache map and a previously transmitted primary cache map reaches a threshold, the method transmits the current primary cache map from the primary site to the secondary site. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventor: Xue Qiang Zhou
  • Patent number: 10268588
    Abstract: A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Vijayalakshmi Srinivasan, Jason Zebchuk
  • Patent number: 10223013
    Abstract: Examples of techniques for processing I/O operations in a channel are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: copying, by a system assist processor, a subchannel of the channel into a lower portion of a channel communication area responsive to receiving the I/O operation; copying, by the system assist processor, channel program information from a designated starting location in a customer memory into a control block; building, by the system assist processor, a starting channel communication area into a top portion of the control block; queuing, by the system assist processor, the control block to a queue for the channel; processing, by the channel, the I/O operation responsive to retrieving the control block from the queue.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Craig A. Bickelman, Daniel Casper, Christopher Colonna, John Flanagan, Francis Gassert, Elke G. Nass, Kenneth J. Oakes, Mooheng Zee
  • Patent number: 10223001
    Abstract: When receiving a write command from a host, a memory system according to one embodiment updates first correspondence information indicating the correspondence relationship between a logical address corresponding to user data and a position in a first memory and transmits the user data which has been stored in a second memory to the first memory. When the transmission is completed, the memory system writes the user data to the first memory. When the update and the transmission are completed, the memory system releases a memory area which stores the user data such that the memory area can be used as a memory area for other data.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: March 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiki Saito, Kiyotaka Iwasaki
  • Patent number: 10223295
    Abstract: A data processing machine is configured to automatically keep track of hypervisor given pointers pointing to respective and newly allocated areas of memory and to automatically keep track of corresponding copies or derivatives of the given pointers. A unique allocation identifier is generated for each newly allocated area. The allocation identifier is appended to a valid ID's holding list. All pointers pointing to the allocated area are tracked by a protected pointers tracking table. Additionally, a multi-input associative cache stores entries for recently used ones of the protected pointers where the entries include the respective allocation identifiers of the pointers. All pointers to a given, de-allocated area can be invalidated by deleting their entries form the multi-input associative cache and by deleting the corresponding unique allocation identifier from the valid ID's holding list.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 5, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: John Victor Sell
  • Patent number: 10223260
    Abstract: According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn M. O'Brien, John K. O'Brien, Zehra N. Sura
  • Patent number: 10216489
    Abstract: An approach to selecting statements for inlining in a COBOL program involving creating a PERFORM Graph (PG), determining whether the PG is a Directed Acyclic Graph (DAG), responsive to determining the PG is not a DAG, identifying a maximum sub-graph DAG corresponding to the PG, computing one or more infeasible paths associated with a Control Flow Graph (CFG), wherein the infeasible paths are induced by PERFORM range calls associated with a plurality of edges corresponding to the PG or the maximum sub-graph DAG, ordering the plurality of edges corresponding to the PG or the maximum sub-graph DAG in a list, selecting one or more edges, based on traversing the list of the plurality of edges and generating an indicator of the one or more selected edges.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Iain A. Ireland, Allan H. Kielstra, Artur Kink, Muntasir A. Mallick
  • Patent number: 10210095
    Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
  • Patent number: 10204195
    Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tracy Bashore, Ahmed Gheith, Aditya Kumar, Andrew R. Malota, Ronald L. Rockhold
  • Patent number: 10204194
    Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tracy Bashore, Ahmed Gheith, Aditya Kumar, Andrew R. Malota, Ronald L. Rockhold
  • Patent number: 10198206
    Abstract: Example implementations relate to memory mode categorization. An example memory mode categorization can include determining local and remote data bandwidths received at each of a first processor and a second processor for a data sample, comparing the local and the remote data bandwidths to a first threshold bandwidth and a second threshold bandwidth, respectively, creating a traffic pattern for the data sample based on the comparison, and categorizing the data sample as being a candidate for a particular memory mode based on the created traffic pattern.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: February 5, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Raphael Gay, Kirsten Olsen
  • Patent number: 10192065
    Abstract: A data storage management system comprises enhanced capabilities for automatically discovering operational characteristics of data storage devices installed in the system. A user interface enables end-users to submit requests for storage resources ranging from a simple request for a certain amount of storage space to more complex requests that specify the type of storage technology, the manufacturer, the I/O speed of the storage device, etc. The end-user also may include an expiration timeframe for the requested storage space. The system identifies storage devices that are suitable to the end-user's request, automatically provisions the storage space (e.g., LUN), and assigns it to the requestor. The assigned storage space may automatically expire, based on user-requested or system-provided expiration timeframes. Expired storage space is returned to a logical pool of available resources so that it may be assigned in response to other requests.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 29, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Sudha Krishnan Iyer, Duncan Alden Littlefield
  • Patent number: 10192593
    Abstract: Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 29, 2019
    Assignee: SK hynix Inc.
    Inventor: Haeng Seon Chae
  • Patent number: 10185744
    Abstract: In a general aspect, a computer-implemented method for executing a query on a table of a database, where the table has multiple partitions, can include receiving a query requesting a view on the table. The view on the table can be based on data included in a partition of the multiple partitions of the table. The method can also include determining a cached result to the query is not available in the database and generating a result to the query from, at least, the data of the partition of the multiple partitions. After the generating, the method can include building a cache including the result to the query, associating a transaction identifier for the query with the result to the query result in the cache; and returning the result to the query.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 22, 2019
    Assignee: SAP SE
    Inventors: Christian Bensberg, Norman May, Sung Heun Wi, Sang Il Song, Christian Kraus
  • Patent number: 10169250
    Abstract: A method and apparatus for controlling access to a hash-based disk is provided, the disk comprising a storage object, the storage object comprising a set of records and a hash value, the method comprising constructing a Bloom filter for the storage object; reading the set of records in the storage object; and filtering an access request to the storage object using the Bloom filter. In accordance with embodiments of the present invention, access requests to storage objects on the disk are filtered by a Bloom filter to reduce unnecessary accesses to the disk, and input and output accesses to the disk are reduced.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 1, 2019
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yaqing Li, Jianping Zhu
  • Patent number: 10157145
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andre L. Albot, Vishal C. Aslot, Mark Rogers, Randal C. Swanberg
  • Patent number: 10157144
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andre L. Albot, Vishal C. Aslot, Mark Rogers, Randal C. Swanberg
  • Patent number: 10152317
    Abstract: A method and system are described updating software packages in a storage system. The method includes receiving software packages for upgradation of the software packages of storage arrays from the plurality of storage arrays. Each of the received software packages correspond to a storage array of the plurality of storage arrays. A time window for updating software packages of the one or more storage arrays is identified, based on an average count of input/output operations per second (IOPS) associated with each storage array. Virtual memories are allocated, within the identified time window, to a set of storage arrays from one or more storage arrays, for uploading each of the software packages. The software packages are uploaded in the allocated virtual memories. The software packages of each storage array of the set are simultaneously updated, by receiving each of the software package from the allocated virtual memory of corresponding storage array.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 11, 2018
    Assignee: WIPRO LIMITED
    Inventors: Rishav Das, Karanjit Singh
  • Patent number: 10152612
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for secure memory page mapping in a virtual machine (VM) environment. The system may include a processor configured to execute a virtual machine monitor (VMM). The VMM may be configured to maintain a table of cryptographic keys and associate a token with one of the memory pages to be mapped from a guest linear address (GLA) to a guest physical address (GPA). The token may include a key identifier (key ID) associated with one of the cryptographic keys, and an authentication code based on the GLA, the GPA, and one of the cryptographic keys. The system may also include a page walk processor configured to validate the token to indicate that the memory page associated with the token is authorized to be mapped from the GLA to the GPA.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventor: Michael Lemay
  • Patent number: 10152260
    Abstract: An information system according to one embodiment of this invention includes a first computer which is an SDS (Software Defined Storage) having a virtualization function and a second computer which is an SDS. The first computer can provide a logical volume using a volume in the second computer as a storage region by the virtualization function. When the information system receives a direction to install a storage control program to the second computer, the information system specifies the logical volume using the volume of the second computer as the storage region among logical volumes in the first computer, and then moves data stored in the volume of the second computer used by the specified logical volume as the storage region to a storage device in the first computer. Thereafter, the storage control program is installed in the second computer.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: December 11, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takahiro Yamamoto
  • Patent number: 10146696
    Abstract: A data storage system includes compute engines each including a CPU complex, physical memory, interfaces to host computers and physical storage devices, and a fabric interface. A non-cache-coherent fabric interconnects the compute engines as cluster members of a cluster, the fabric supporting a global lock enabling each cluster member to obtain temporary exclusive access to addressable units of non-virtual memory. The CPU complexes implement a global virtual memory (GVM) on top of the non-virtual memory, including (1) a globally shared GVM page table of global page table entries, each identifying the cluster members having a corresponding GVM page mapped, and (2) GVM page management functionality including (i) use of the global lock to obtain exclusive access to the global page table entries for page management operations, and (ii) transfer of underlying data of the pages of the GVM among the cluster members.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 4, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Louis Krigovski, David Reese, Clifford Lim, Steven T. McClure
  • Patent number: 10146684
    Abstract: Techniques for copying forward live data within storage regions used by a file system to new storage regions are provided. Storage regions refer to ranges of persistent storage within a storage medium. One or more live-clump-identifying workers identify a set of live-clump-references. The live-clump references are references to live clumps that belong to live objects. Live clumps represent a unit of data. After identifying the set of live-clump-references, one or more container-identifying workers identify a set of storage regions that contain clumps that correspond to the set of live-clump references. After identifying the set of storage regions corresponding to the set of live-clump-references, a plurality of copy-forward task workers perform copy-forward operations on the set of storage regions to copy live data to new storage regions.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 4, 2018
    Assignee: Datrium, Inc.
    Inventors: Windsor Hsu, R. Hugo Patterson
  • Patent number: 10146538
    Abstract: Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Roman Dementiev, Ravi Rajwar, Ady Tal, Alex Gerber
  • Patent number: 10140158
    Abstract: A method and a Host Machine Allocating Module (HMAM) for allocating a host machine. The HMAM is configured for managing information about latency ratings for pairs of groups comprising CPUs and memory units. Said each pair is associated with a respective latency rating. The HMAM receives a request for allocation, wherein the request indicates a first number of CPUs and a second number of memory units and a policy. The policy defines a distribution of the first number of CPUs and the second number of memory units with respect to sets of latency ratings. The HMAM distributes, based on the distribution, the first number of CPUs and the second number of memory units into clusters. The HMAM allocates said each cluster to at least one of said pairs of groups, wherein the respective latency rating of said at least one of said pairs is found to match, according to the policy, the respective one of the sets of latency ratings for said each cluster. A Latency Rating Information Generating Module and a method therein.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: November 27, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Daniel Turull, Vinay Yadhav
  • Patent number: 10135557
    Abstract: A method (10) of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code (12); b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal (14); c. decoding the input digital communications traffic to obtain information bits and non-information bits (16); d. removing the non-information bits (18); e. adding service channel bits for monitoring or maintenance (20); f. assembling the service channel bits and information bits into frames (22); and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link (24), wherein steps c. to g. are performed using the timing of the recovered clock signal. A communications network receiver configured to implement the method is also provided.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: November 20, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Stefano Stracca, Fabio Cavaliere
  • Patent number: 10114744
    Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kamyar Souri, Andrew J. Tomlin, Dmitry S. Obukhov, Jing Booth, Mei-Man L. Syu
  • Patent number: 10109353
    Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koki Ueno, Yasuhiro Shiino, Asuka Kaneda
  • Patent number: 10109570
    Abstract: A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example, the pattern comprises a central power connector area having a plurality of power connectors to provide power to an attached chip, a signal area having a plurality of signal connectors to communicate signals to the attached chip, an edge area surrounding the signal area and the central power connector area, and a plurality of traces each coupled to a signal connector, the traces extending from the respective coupled signal connector away from the central power connector to connect to an external component, wherein the signal connectors are placed in rows, the rows having a greater separation near the edge area than near the central area.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Eng Fook Chan, Wei Chung Lee, Zhi Wei Low
  • Patent number: 10102146
    Abstract: Methods may include after a power loss, determining a most recently saved section of a logical block addressing (LBA) table, a previous section saved prior to the most recently saved section of the LBA table, and a least recently saved section of the LBA table, reading an open super block and updating entries in the LBA table from the most recently saved section through to the least recently saved section, reading a newest closed super block from a plurality of closed super blocks and updating entries in the LBA table from the previous section saved prior to the most recently saved section through to the least recently saved section, and reading an oldest super block and updating entries in the LBA table in the least recently saved section.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 16, 2018
    Assignee: SK Hynix Inc.
    Inventors: Shwetashree Virajamangala, Nagabhushan Hegde, Frederick K. H. Lee