Shared Memory Area Patents (Class 711/147)
  • Patent number: 11163715
    Abstract: A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ronald Peter Luijten, Gagandeep Singh, Joost VandeVondele
  • Patent number: 11157422
    Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Daniel Rivas Barragan, Kshitij A. Doshi, Mark A. Schmisseur
  • Patent number: 11157184
    Abstract: A host system performs I/O processing using metadata for a storage system, where none or some of the metadata is stored on the host system. The host system may be coupled to the global memory of the storage system along a communication path that includes an internal switching fabric of the storage system and does not include a network located externally to the storage system. The host system may exchange communications over the communication path to access indirection layers on the storage system to determine a global memory address of metadata corresponding to an I/O operation. The host system may include a host metadata table of global memory addresses for metadata of logical locations logical devices. The host system may query the host metadata table for a global memory address of metadata corresponding to a logical location specified in an I/O operation.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 26, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew L. Chanler, Kevin M. Tobin, Gabi Benhanokh
  • Patent number: 11132460
    Abstract: An apparatus and method control access to user information by generating a record of user information that includes the user information and appending the record of user information to a blockchain. A hash is assigned to the user information and the record of user information is encrypted prior to appending the record of user information to the blockchain. A record of authorization is received and appended to the blockchain. The record of authorization includes the user information, an identification of a third-party application authorized to read the record of authorization, and an access expiration parameter that places a restriction or limitation on access to the user information.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 28, 2021
    Assignee: MO AC BLOCKCHAIN TECH INC.
    Inventor: Xiaohu Chen
  • Patent number: 11106800
    Abstract: A kernel is monitored for occurrence of a set of Kprobes. A determination is made that a Strategy that makes use of at least one Kprobe included in the set of Kprobes has been matched. A remedial action is taken in response to the determination. Examples of such remedial actions include generating an alert and terminating a network connection.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Capsule8, Inc.
    Inventor: Peter Laurence Markowsky
  • Patent number: 11099994
    Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: August 24, 2021
    Assignee: Texas Instmments Incorporated
    Inventors: Matthew David Pierson, Daniel Wu, Kai Chirca
  • Patent number: 11099746
    Abstract: A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 24, 2021
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Dror Bromberg, Roi Sherman
  • Patent number: 11100019
    Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Hayakawa, Toshiyuki Hiraki, Sho Yamanaka
  • Patent number: 11093414
    Abstract: A computing system includes a plurality of nodes including a first node, the first node including at least one core, a memory controller, a node-track register (MSR), and a monitoring counter array including a plurality of counters. The memory controller is to access a plurality of bits of the node-track MSR to determine a subset of nodes to be tracked, wherein the subset of nodes includes the first node and a second node. The memory controller is further to allocate a first counter of the plurality of counters to track memory requests sent to a local system memory by the first node; and allocate a second counter of the plurality of counters to track a memory response associated with a memory request sent by the first node to the second node.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Yao Jin, Ashok Raj, Anthony E. G. Luck
  • Patent number: 11093396
    Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 17, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric Francis Robinson, Derek Bachand, Jason Panavich, Kevin Neal Magill, Michael B. Mitchell, Michael P. Wilson
  • Patent number: 11054998
    Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Facebook, Inc.
    Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
  • Patent number: 11055184
    Abstract: A log unit provides a shared log for recording updates on data objects. Garbage collection is performed locally and in-place by the log unit. In a marking portion of the garbage collection process, the log unit identifies and marks log entries that record supersedable updates. In a deallocation portion of the process, the log unit deallocates at least portions of the marked log entries that contain supersedable updates.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 6, 2021
    Assignee: VMWARE, INC.
    Inventors: Michael Wei, Maithem Munshed, Anny Martinez Manzanilla, Zeeshan Altaf Lokhandwala, Saeed A Behnam, Medhavi Dhawan, Dahlia Malkhi
  • Patent number: 11048587
    Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
  • Patent number: 11042409
    Abstract: A processing device receives request from a process of a plurality of processes of a clusterized service, to attempt to obtain exclusive access to a predetermined resource associated with a leader state of the plurality of processes. Responsive to successfully obtaining the exclusive access to the predetermined resource, the processing device enables the process to enter the leader state. The processing device enables the process to stay in the leader state for the lifetime of the process.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 22, 2021
    Assignee: Red Hat, Inc.
    Inventor: Michael John Hrivnak
  • Patent number: 11036599
    Abstract: Embodiments for disaster recovery in a disaggregated computing system. A memory pool is allocated including allocated memory elements at a secondary, disaster recovery site for data received from memory pool elements within the memory pool at a primary site. Data is continuously replicated to the allocated memory elements at the disaster recovery site. During a disaster recovery failover, a determination is made whether there are sufficient resources in the disaggregated computing system for performing workloads of a certain type. If insufficient resources are available, a disaster recovery process is initiated to re-allocate the resources for performing given workloads of the certain type.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valentina Salapura, John A. Bivens, Min Li, Ruchi Mahindru, Eugen Schenfeld
  • Patent number: 11029863
    Abstract: Techniques for using non-volatile random access memory (NVM) as volatile random access memory (RAM) are provided. In one set of embodiments, a computer system can detect that an amount of free space in a volatile RAM of the computer system has become low and, in response, can add one or more memory pages from an unused portion of an NVM of the computer system to the system's volatile RAM pool. Conversely, the computer system can detect that an amount of free space in the NVM has become low and, in response, can return the one or more memory pages from the volatile RAM pool back to the NVM.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 8, 2021
    Assignee: VMware, Inc.
    Inventors: Kiran Tati, Preeti Agarwal, Julien Freche, Xavier Deguillard, Rajesh Venkatasubramanian, Ishan Banerjee
  • Patent number: 11023605
    Abstract: Data access threat detection and prevention modules are implemented proximate to data storage, e.g. in disk array controllers. The modules may be implemented in hardware or firmware. The modules monitor IOs from the disk array controllers to access managed drives. IOs exhibiting access parameters that deviate from a whitelist or match a blacklist are deemed to be suspicious. The whitelist may be created from monitoring normal, safe IOs and storing associated access patterns. In response to detection of suspicious activity the modules may halt or slow subsequent IOs, e.g. IOs to the same data, all data, an associated logical device, or the managed drive.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 1, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Victor Salamon, John Afaganis
  • Patent number: 11014689
    Abstract: An aircraft control or interface unit with a programmable controller includes an isolated, non-volatile command memory containing the complete, fixed set of non-compiled, text-format commands used for every application programmed into an instance of the aircraft control or interface unit. A command interpreter automatically and sequentially interprets and executes the command set in a continuous loop, where the command set encompasses all commands necessary for the ability to activate, implement and disable all available input, output and processing capabilities within the hardware configuration of the aircraft control or interface unit.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Applied Avionics, Inc.
    Inventors: Steven A. Edwards, Craig Jay Coley, Trang Tran Myers
  • Patent number: 11010313
    Abstract: A method, apparatus, and system for an architecture for machine learning acceleration is presented. An apparatus includes a plurality of processing elements, each including a tightly-coupled memory, and a memory system coupled to the processing elements. A global synchronization manager is coupled to the plurality of the processing elements and to the memory system. The processing elements do not implement a coherency protocol with respect to the memory system. The processing elements implement direct memory access with respect to the memory system, and the global synchronization manager is configured to synchronize operations of the plurality of processing elements through the TCMs.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Colin Beaton Verrilli, Natarajan Vaidhyanathan, Rexford Alan Hill
  • Patent number: 11003590
    Abstract: A memory system includes: a memory device storing host data provided from a host; and a memory controller managing and transferring the host data between the host and the memory device, wherein the memory controller comprises: a write buffer temporarily storing the host data to be transferred to the memory device; a buffer monitoring device checking a usage amount of the write buffer during a predetermined period; a buffer usage comparing device generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and a first flush device transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Min-O Song
  • Patent number: 10990528
    Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 27, 2021
    Assignee: Macronix International Co., Ltd.
    Inventor: Yi-Chun Liu
  • Patent number: 10983931
    Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 20, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter
  • Patent number: 10983881
    Abstract: Embodiments for disaster recovery in a disaggregated computing system. Memory resources are allocated at a secondary, disaster recovery site for data received from a primary site. The data from the primary site is continuously replicated to the allocated memory resources at the disaster recovery site without requiring any compute resources to be attached to the allocated memory resources. Responsive to determining a disaster recovery failover is in progress, the compute resources are assigned to the allocated memory resources for performing a failover workload, and the failover workload is executed at the disaster recovery site.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valentina Salapura, John A. Bivens, Min Li, Ruchi Mahindru, Eugen Schenfeld
  • Patent number: 10983926
    Abstract: A driver associated with a host peripheral component interconnect (PCI) device may be initiated, the host PCI device to be accessed by an application executed by a guest operating system (OS) of a guest using user space memory of the guest. A host page table switching instruction may be executed using the driver to cause a switch from a first host page table structure to a second host page table structure. The host PCI device may be accessed using the driver via a PCI alias address that is mapped to a host PCI address in the second host page table structure. Application code associated with the application may be prevented from accessing a host memory address in the second host page table structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 20, 2021
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 10977124
    Abstract: A distributed storage system includes a plurality of storage nodes including: a storage device for storing data in such a way that the data can be written thereto and read therefrom; a memory in which a software program is recorded; and a CPU for executing the software program. The memory stores group management information in which a group configured with a plurality of storage nodes and the storage nodes that configure the group are associated with each other and recorded. The CPU converts data into a plurality of data blocks so that the data is redundant at a predetermined data protection level, and stores the data blocks into each of a plurality of storage nodes belonging to the same group based on the group management information.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 13, 2021
    Assignee: HITACHI, LTD.
    Inventors: Mitsuo Hayasaka, Keiichi Matsuzawa
  • Patent number: 10969992
    Abstract: Systems, methods, and devices can include a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index physical address and virtual address translations; and a memory controller logic implemented at least partially in hardware, the memory controller logic to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine. The processing engine can use the physical address for memory transactions in response to a streaming workload job request.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Saurabh Gayen, Dhananjay A. Joshi, Philip R. Lantz, Rajesh M. Sankaran
  • Patent number: 10970253
    Abstract: Embodiments for data deduplication in a data deduplication environment by one or more processors. A data extent, existing on a remote server instance, may be denoted as a virtual base extent to eliminate redundant transfer of the data extent for fast data deduplication in a distributed data protection environment. A synchronization operation is performed to replace the virtual base extent with actual data via a replication process.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Xu, Jing Wen, Yu Meng Li
  • Patent number: 10956240
    Abstract: A memory block is provided that is shared between two endpoints. This first endpoint is either a host for a virtual machine or the virtual machine. The second endpoint is either the host or another virtual machine. The shared memory block includes a buffer, a post counter, and an acknowledgment counter. The block is employed for communicating data from the first endpoint to the second endpoint. Sending data to the second endpoint includes identifying the buffer as being currently owned by the first endpoint and storing data in the buffer. It is then detected that the acknowledgment counter is equal to the post counter. The post counter is then incremented to signal that data has been stored for receipt by the second endpoint. Receiving the data by the second endpoint includes detecting that the post counter has changed and then incrementing the acknowledgment counter to acknowledge receipt of the data.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 23, 2021
    Assignee: BlackBerry Limited
    Inventors: Xiaoyong Sun, Mikhail Nefedov
  • Patent number: 10942864
    Abstract: Examples herein involve processing data in a distributed data processing system using an off-heap memory store. An example involves allocating a shared memory region of a shared memory to store attributes corresponding to a first partition of a distributed data system, and updating, in the shared memory region, the attributes corresponding to updates to the local data from process iterations of the first partition, such that a second partition of the distributed data system has access to the updated attributes.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mijung Kim, Alexander Ulanov, Jun Li
  • Patent number: 10929065
    Abstract: Techniques coordinate access operations. Such techniques involve: obtaining first statistical data of a first set of access operations associated with a first storage resource pool in the RAID and second statistical data of a second set of access operations associated with a second storage resource pool in the RAID, the first set of access operations including a background access operation and a user access operation, and the second set of access operations including at least a user access operation; determining, based on the first and second statistical data, availability of a memory shared by the first and second storage resource pools; and adjusting, based on the availability, the background access operation in the first set of access operations to control a capacity of the memory occupied by the background access operation. Accordingly, the response time of the storage system for the user access operations can be shortened, etc.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Hongpo Gao, Jian Gao, Geng Han, Jianbin Kang, Jibing Dong
  • Patent number: 10915449
    Abstract: Systems, methods, and software described herein facilitate servicing of data requests based on quality of service assigned to processing jobs. In one example, a method of prioritizing data requests in a computing system based on quality of service includes identifying a plurality of data requests from a plurality of processing jobs. The method further includes prioritizing the plurality of data requests based on a quality of service assessed to each of the plurality of processing jobs, and assigning cache memory in the computing system to each of the plurality of data requests based on the prioritization.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Thomas A. Phelan, Michael J. Moretti, Joel Baxter, Gunaseelan Lakshminarayanan
  • Patent number: 10915458
    Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 9, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
  • Patent number: 10908939
    Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics eng
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Altug Koker, David Puffer, Murali Ramadoss, Bryan R. White, Hema C. Nalluri, Aditya Navale
  • Patent number: 10908959
    Abstract: A computer-implemented method, system or product, the method comprising receiving, by a memory management system, a first memory request from a first thread in a multi-threaded computing environment, the memory request including a target value associated with a size of memory requested by the first thread; in response to receiving the first memory request, retrieving a header referencing a first node in a linked list data structure having a plurality of connected nodes, the header comprising a first pointer value, referring to a free first memory block, and a first size value associated with a size of the first memory block; reading, by way of an atomic operation, the first pointer value and the first size value from the linked list data structure.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 2, 2021
    Assignee: SAP SE
    Inventors: Daniel Booss, Robert Kettler
  • Patent number: 10909053
    Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: February 2, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Maggie Chan, Philip Ng, Paul Blinzer
  • Patent number: 10909033
    Abstract: Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 2, 2021
    Assignee: NVIDIA Corporation
    Inventors: Kun Fang, James M. Van Dyke
  • Patent number: 10896128
    Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 19, 2021
    Assignee: Facebook, Inc.
    Inventors: Narsing Vijayrao, Keith Adams
  • Patent number: 10891206
    Abstract: Embodiments for disaster recovery in a disaggregated computing system. A memory pool is allocated including allocated memory elements at a secondary, disaster recovery site for data received from memory pool elements within the memory pool at a primary site. Data is continuously replicated to the allocated memory elements at the disaster recovery site without requiring any compute resources to be attached to the allocated memory elements during the replicating. An orchestration mechanism is used to regulate an available amount of resources to be assigned to the allocated memory elements at the disaster recovery site during a failover operation for performing failover workloads associated with the replicated data upon the primary site becoming inoperable.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valentina Salapura, John A. Bivens, Min Li, Ruchi Mahindru, Eugen Schenfeld
  • Patent number: 10884900
    Abstract: A method for processing distributed breakpoints when debugging a distributed application includes establishing a breakpoint in source code of a distributed computer program and executing the distributed computer program. Thereafter, an encountering of the breakpoint is detected in one of the processes, and execution of the one of the processes halted. However, halting execution of any other of the processes is delayed for a delay period during which a list both is generated of others of the processes in which the breakpoint is encountered and also is sorted in accordance with prioritization criteria. Finally, the sorted list is presented after the lapse of the delay period, individual ones of the processes selected in the list, and execution of the selected individual ones of the processes in the sorted list halted while halting of execution of non-selected ones of the processes in the sorted list is bypassed.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Jay S. Bryant, James E. Carey, Joseph W. Cropper, John M. Santosuosso
  • Patent number: 10884741
    Abstract: Techniques for providing high-performance buffer caches for transactional input/output (I/O) systems are disclosed. The techniques include obtaining a first logical creation time of a resource to be acquired by the first transaction during a pre-commit phase of a first transaction with an I/O system. When the first logical creation time exceeds a latest logical creation time from a set of resources previously acquired by the first transaction, the first logical creation time of the resource is compared with an earliest logical termination time from the set of resources. When the first logical creation time of the resource exceeds the earliest logical termination time from the set of resources, a conflict between the resource and the set of resources is detected, and a restart of the first transaction is triggered.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: January 5, 2021
    Assignee: Oracle International Corporation
    Inventors: Unmesh Rathi, Arjun Sharma, Suresh Kumar Neelakanda Iyer, Vijayan Satyamoorthy Srinivasa
  • Patent number: 10877804
    Abstract: A computing apparatus, an electronic device, and an information processing method are provided. The computing apparatus includes an executor, a driver, and a proxy component. The executor executes a computing operation based on a driving command to generate an execution result, the driver generates the driving command, and the proxy component is respectively connected to the executor and the driver. Further, the proxy component sends the driving command from the driver to the executor, and sends the execution result from the executor to the driver.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 29, 2020
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventor: Dong Li
  • Patent number: 10866902
    Abstract: Processor, apparatus, and method for reordering a stream of memory access requests to establish locality are described herein. One embodiment of a method includes: storing in a request queue memory access requests generated by a plurality of execution units, the memory access requests comprising a first request to access a first memory page in a memory and a second request to access a second memory page in the memory; maintaining a list of unique memory pages, each unique memory page associated with one or more memory access requests stored the request queue and is to be accessed by the one or more memory access requests; selecting a current memory page from the list of unique memory pages; and dispatching from the request queue to the memory, all memory access requests associated with the current memory page before any other memory access request in the request queue is dispatched.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Ishwar S. Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney
  • Patent number: 10853297
    Abstract: A method includes: by an application executed by a first node, determining whether a non-transparent bridge between the first node and a second node is in a disconnected state; sending a re-initialization request from the application to a driver executed by the first node when the NTB is in the disconnected state; re-initializing a memory of the first node upon the driver receiving the re-initialization request; transmitting a result message related to the re-initialization of the memory to the second node; and implementing a memory-sharing procedure upon completing the re-initialization of the memory and receiving, from the second node, another result message related to re-initialization of a memory of the second node.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 1, 2020
    Assignee: Mitac Computing Technology Corporation
    Inventors: Thanh-Tu Thai, Hung-Tar Lin, Ching-Wen Hsu
  • Patent number: 10824574
    Abstract: A multi-port storage device multi-socket memory access system includes a plurality of processing subsystems interconnected by at least one processing subsystem interconnect, a respective local memory subsystem for each of the processing subsystems, and a storage system that provides a respective connection to each of the processing subsystems. The storage system receives a memory access command and uses it to determine a first local memory subsystem that includes a memory location that is identified in the memory access command. The storage system then uses a connection mapping to identify a first connection to a first processing subsystem for which the first local memory subsystem is provided. The storage system then accesses the first memory subsystem through the first connection, via the first processing system, and without utilizing the at least one processing subsystem interconnect, in order to execute the memory access command.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 3, 2020
    Assignee: Dell Products L.P.
    Inventors: Kevin Thomas Marks, Austin Patrick Bolen, William Price Dawkins, William Emmett Lynn, Gary Benedict Kotzur, Robert W. Hormuth
  • Patent number: 10810220
    Abstract: A system deploys visualization tools, business analytics software, and big data software in a multi-instance mode on a large, coherent shared memory many-core computing system. The single machine solution provides or high performance and scalability and may be implemented remotely as a large capacity server (i.e., in the cloud) or locally to a user. Most big data software running in a single instance mode has limitations in scalability when running on a many-core and large coherent shared memory system. A configuration and deployment technique using a multi-instance approach, which also includes visualization tools and business analytics software, maximizes system performance and resource utilization, reduces latency and provides scalability as needed, for end-user applications in the cloud.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 20, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Sanhita Sarkar
  • Patent number: 10802729
    Abstract: A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 13, 2020
    Assignee: ARM Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
  • Patent number: 10802974
    Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 13, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew David Pierson, Daniel Wu, Kai Chirca
  • Patent number: 10783046
    Abstract: Computing cluster system management. Embodiments implement fine-grained rule-based approaches to error recovery. A service dispatches tasks to components of the computing cluster. At the time of task dispatching, entries are made into a write-ahead log. The write-ahead log entries serve for recording task and component attributes. A monitor detects a failure event raised by one or more of the components of the computing cluster. Responses to the failure event include determining a set of conditions that are present in the computing cluster at the time of the detection, and then using the failure event and the determined conditions in combination with a set of fine-grained failure processing rules to determine one or more recovery actions to take. Recovery actions include redistributing the failed task to a different node or to different service. Certain conditions and rules initiate actions that rollback the state of a component to a previous success point.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 22, 2020
    Assignee: Nutanix, Inc.
    Inventors: Ranjan Parthasarathy, Vinod Gupta, Digvijay Dalapathi
  • Patent number: 10776229
    Abstract: Database processing engines of a single cluster are configured such that each engine is a primary engine and a dedicated fallback engine to one other engine of the cluster. In an embodiment, the cluster includes more than two processing engines.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 15, 2020
    Assignee: Teradata US, Inc.
    Inventors: Tirunagari Venkata Rama Krishna, Srinath Boppudi, Frederick Stuart Kaufmann, Donald Raymond Pederson
  • Patent number: 10776292
    Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 15, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter